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49 lines
1.8 KiB
Diff
49 lines
1.8 KiB
Diff
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From bbd3778da16b3d448832b843f80bcde1aff26290 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 20 Oct 2023 16:11:42 +0200
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Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USB3 host controller
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RK3588 has three USB3 controllers. This adds the host-only controller,
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which is using the naneng-combphy shared with PCIe and SATA.
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The other two are dual-role and using a different PHY that is not yet
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supported upstream.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20231020150022.48725-4-sebastian.reichel@collabora.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -443,6 +443,27 @@
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status = "disabled";
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};
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+ usb_host2_xhci: usb@fcd00000 {
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+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
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+ reg = <0x0 0xfcd00000 0x0 0x400000>;
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+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
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+ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
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+ <&cru CLK_PIPEPHY2_PIPE_U3_G>;
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+ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
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+ dr_mode = "host";
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+ phys = <&combphy2_psu PHY_TYPE_USB3>;
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+ phy-names = "usb3-phy";
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+ phy_type = "utmi_wide";
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+ resets = <&cru SRST_A_USB3OTG2>;
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,dis-tx-ipgap-linecheck-quirk;
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+ snps,dis_rxdet_inp3_quirk;
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+ status = "disabled";
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+ };
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+
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pmu1grf: syscon@fd58a000 {
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compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xfd58a000 0x0 0x10000>;
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