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86 lines
2.3 KiB
Diff
86 lines
2.3 KiB
Diff
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From 83afcf14edb9217e58837eb119da96d734a4b3b1 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 21 Oct 2023 14:00:07 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM
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IPQ6018 comes in multiple SKU-s and some of them dont support all of the
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OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
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supported OPP-s based on the SoC dynamically.
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As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
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goes up to 1.5GHz and is marked as such via an eFuse.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Link: https://lore.kernel.org/r/20231021120048.231239-1-robimarko@gmail.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
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1 file changed, 13 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -95,42 +95,49 @@
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};
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cpu_opp_table: opp-table-cpu {
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- compatible = "operating-points-v2";
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+ compatible = "operating-points-v2-kryo-cpu";
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+ nvmem-cells = <&cpu_speed_bin>;
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opp-shared;
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opp-864000000 {
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opp-hz = /bits/ 64 <864000000>;
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opp-microvolt = <725000>;
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+ opp-supported-hw = <0xf>;
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clock-latency-ns = <200000>;
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};
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <787500>;
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+ opp-supported-hw = <0xf>;
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clock-latency-ns = <200000>;
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};
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opp-1320000000 {
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opp-hz = /bits/ 64 <1320000000>;
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opp-microvolt = <862500>;
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+ opp-supported-hw = <0x3>;
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clock-latency-ns = <200000>;
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};
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opp-1440000000 {
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opp-hz = /bits/ 64 <1440000000>;
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opp-microvolt = <925000>;
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+ opp-supported-hw = <0x3>;
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clock-latency-ns = <200000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <987500>;
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+ opp-supported-hw = <0x1>;
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clock-latency-ns = <200000>;
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};
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opp-1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1062500>;
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+ opp-supported-hw = <0x1>;
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clock-latency-ns = <200000>;
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};
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};
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@@ -321,6 +328,11 @@
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reg = <0x0 0x000a4000 0x0 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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+
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+ cpu_speed_bin: cpu-speed-bin@135 {
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+ reg = <0x135 0x1>;
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+ bits = <7 1>;
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+ };
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};
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prng: qrng@e3000 {
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