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kernel/qualcommax: Restore kernel files for v6.1

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This is an automatically generated commit which aids following Kernel patch history,
as git will see the move and copy as a rename thus defeating the purpose.

See: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
for the original discussion.

Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko 2024-03-22 10:01:17 +01:00
parent e28492c81a
commit e8e7b3c106
97 changed files with 23959 additions and 0 deletions
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540
target/linux/qualcommax/config-6.1 Normal file
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@ -0,0 +1,540 @@
CONFIG_64BIT=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
CONFIG_ARM64_ERRATUM_2077057=y
CONFIG_ARM64_ERRATUM_2658417=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_ARM64_SME=y
CONFIG_ARM64_SVE=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_ARM_MHU_V2 is not set
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
CONFIG_AT803X_PHY=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
# CONFIG_COMPAT_32BIT_TIME is not set
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_COREDUMP=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
CONFIG_CRC16=y
CONFIG_CRC8=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DEV_QCE=y
CONFIG_CRYPTO_DEV_QCE_AEAD=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
CONFIG_CRYPTO_DEV_QCE_SHA=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
CONFIG_DEV_COREDUMP=y
CONFIG_DMADEVICES=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_IIO=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IPQ_APSS_6018=y
CONFIG_IPQ_APSS_PLL=y
# CONFIG_IPQ_GCC_4019 is not set
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_KPSS_XCC is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_IPQ4019=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_QCOM_RPM is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_CQHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_RELA=y
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8909 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8976 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_QCOMSMEM_PARTS=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_QCOM_QFPROM=y
# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_U_BOOT_ENV=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_PME=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
# CONFIG_PHY_QCOM_EDP is not set
# CONFIG_PHY_QCOM_IPQ4019_USB is not set
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
CONFIG_PHY_QCOM_QMP=y
CONFIG_PHY_QCOM_QUSB2=y
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_IPQ6018 is not set
# CONFIG_PINCTRL_IPQ8074 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8976 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
# CONFIG_PINCTRL_QCM2290 is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SC8280XP is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM6350 is not set
# CONFIG_PINCTRL_SM6375 is not set
# CONFIG_PINCTRL_SM8150 is not set
# CONFIG_PINCTRL_SM8250 is not set
# CONFIG_PINCTRL_SM8450 is not set
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_OPP=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_MSM is not set
CONFIG_POWER_SUPPLY=y
CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_QCA807X_PHY=y
CONFIG_QCA808X_PHY=y
# CONFIG_QCM_DISPCC_2290 is not set
# CONFIG_QCM_GCC_2290 is not set
# CONFIG_QCOM_A53PLL is not set
# CONFIG_QCOM_AOSS_QMP is not set
CONFIG_QCOM_APCS_IPC=y
# CONFIG_QCOM_APM is not set
# CONFIG_QCOM_APR is not set
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QCOM_CLK_APCC_MSM8996 is not set
# CONFIG_QCOM_CLK_APCS_MSM8916 is not set
# CONFIG_QCOM_CLK_APCS_SDX55 is not set
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_FASTRPC is not set
# CONFIG_QCOM_GENI_SE is not set
# CONFIG_QCOM_GSBI is not set
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_ICC_BWMON is not set
# CONFIG_QCOM_IPCC is not set
# CONFIG_QCOM_LLCC is not set
CONFIG_QCOM_MDT_LOADER=y
# CONFIG_QCOM_MPM is not set
CONFIG_QCOM_NET_PHYLIB=y
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_PIL_INFO=y
# CONFIG_QCOM_Q6V5_ADSP is not set
CONFIG_QCOM_Q6V5_COMMON=y
# CONFIG_QCOM_Q6V5_MSS is not set
# CONFIG_QCOM_Q6V5_PAS is not set
CONFIG_QCOM_Q6V5_WCSS=y
# CONFIG_QCOM_RMTFS_MEM is not set
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_RPROC_COMMON=y
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
# CONFIG_QCOM_SMD_RPM is not set
CONFIG_QCOM_SMEM=y
CONFIG_QCOM_SMEM_STATE=y
CONFIG_QCOM_SMP2P=y
# CONFIG_QCOM_SMSM is not set
CONFIG_QCOM_SOCINFO=y
# CONFIG_QCOM_SPM is not set
# CONFIG_QCOM_STATS is not set
# CONFIG_QCOM_SYSMON is not set
CONFIG_QCOM_TSENS=y
# CONFIG_QCOM_WCNSS_CTRL is not set
# CONFIG_QCOM_WCNSS_PIL is not set
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_CPR3 is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
CONFIG_RELOCATABLE=y
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
# CONFIG_RPMSG_CTRL is not set
# CONFIG_RPMSG_NS is not set
CONFIG_RPMSG_QCOM_GLINK=y
CONFIG_RPMSG_QCOM_GLINK_RPM=y
CONFIG_RPMSG_QCOM_GLINK_SMEM=y
CONFIG_RPMSG_QCOM_SMD=y
# CONFIG_RPMSG_TTY is not set
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SCHED_CORE is not set
CONFIG_SCHED_MC=y
CONFIG_SCHED_SMT=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_PROC_FS is not set
# CONFIG_SC_CAMCC_7280 is not set
# CONFIG_SC_DISPCC_7180 is not set
# CONFIG_SC_GCC_7180 is not set
# CONFIG_SC_GCC_8280XP is not set
# CONFIG_SC_GPUCC_7180 is not set
# CONFIG_SC_LPASSCC_7280 is not set
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_LPASS_CORECC_7280 is not set
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SC_VIDEOCC_7180 is not set
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
# CONFIG_SDX_GCC_65 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
# CONFIG_SM_CAMCC_8450 is not set
# CONFIG_SM_GCC_8150 is not set
# CONFIG_SM_GCC_8250 is not set
# CONFIG_SM_GCC_8450 is not set
# CONFIG_SM_GPUCC_6350 is not set
# CONFIG_SM_GPUCC_8150 is not set
# CONFIG_SM_GPUCC_8250 is not set
# CONFIG_SM_GPUCC_8350 is not set
# CONFIG_SM_VIDEOCC_8150 is not set
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SRCU=y
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UCLAMP_TASK is not set
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_VIRTIO=y
CONFIG_VIRTIO_ANCHOR=y
# CONFIG_VIRTIO_BLK is not set
# CONFIG_VIRTIO_NET is not set
CONFIG_VMAP_STACK=y
CONFIG_WANT_DEV_COREDUMP=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

32
target/linux/qualcommax/patches-6.1/0001-v6.2-arm64-dts-qcom-ipq8074-add-A53-PLL-node.patch Normal file
View File

@ -0,0 +1,32 @@
From 6463c10bfdbd684ec7ecfd408ea541283215a088 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:06:28 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add A53 PLL node
Add the required node for A53 PLL which will be used to provide the CPU
clock via APCS for APSS scaling.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-9-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -677,6 +677,14 @@
#mbox-cells = <1>;
};
+ a53pll: clock@b116000 {
+ compatible = "qcom,ipq8074-a53pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo>;
+ clock-names = "xo";
+ };
+
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;

134
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@ -0,0 +1,134 @@
From e593e834fe8ba9bf314d8215ac05d8787f81efda Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:42 +0200
Subject: [PATCH] thermal/drivers/tsens: Add support for combined interrupt
Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
signaling both up/low and critical trips.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220245.338396-2-robimarko@gmail.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 1 +
drivers/thermal/qcom/tsens-v0_1.c | 1 +
drivers/thermal/qcom/tsens-v1.c | 1 +
drivers/thermal/qcom/tsens-v2.c | 1 +
drivers/thermal/qcom/tsens.c | 38 ++++++++++++++++++++++++++-----
drivers/thermal/qcom/tsens.h | 2 ++
6 files changed, 38 insertions(+), 6 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
static struct tsens_features tsens_8960_feat = {
.ver_major = VER_0,
.crit_int = 0,
+ .combo_int = 0,
.adc = 1,
.srot_split = 0,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v0_1.c
+++ b/drivers/thermal/qcom/tsens-v0_1.c
@@ -549,6 +549,7 @@ static int __init init_8939(struct tsens
static struct tsens_features tsens_v0_1_feat = {
.ver_major = VER_0_1,
.crit_int = 0,
+ .combo_int = 0,
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v1.c
+++ b/drivers/thermal/qcom/tsens-v1.c
@@ -273,6 +273,7 @@ static int calibrate_8976(struct tsens_p
static struct tsens_features tsens_v1_feat = {
.ver_major = VER_1_X,
.crit_int = 0,
+ .combo_int = 0,
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -31,6 +31,7 @@
static struct tsens_features tsens_v2_feat = {
.ver_major = VER_2_X,
.crit_int = 1,
+ .combo_int = 0,
.adc = 0,
.srot_split = 1,
.max_sensors = 16,
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -532,6 +532,27 @@ static irqreturn_t tsens_irq_thread(int
return IRQ_HANDLED;
}
+/**
+ * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
+ * @irq: irq number
+ * @data: tsens controller private data
+ *
+ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
+ * critical handler first and then the up/low one.
+ *
+ * Return: IRQ_HANDLED
+ */
+static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
+{
+ irqreturn_t ret;
+
+ ret = tsens_critical_irq_thread(irq, data);
+ if (ret != IRQ_HANDLED)
+ return ret;
+
+ return tsens_irq_thread(irq, data);
+}
+
static int tsens_set_trips(struct thermal_zone_device *tz, int low, int high)
{
struct tsens_sensor *s = tz->devdata;
@@ -1074,13 +1095,18 @@ static int tsens_register(struct tsens_p
tsens_mC_to_hw(priv->sensor, 0));
}
- ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
- if (ret < 0)
- return ret;
+ if (priv->feat->combo_int) {
+ ret = tsens_register_irq(priv, "combined",
+ tsens_combined_irq_thread);
+ } else {
+ ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
+ if (ret < 0)
+ return ret;
- if (priv->feat->crit_int)
- ret = tsens_register_irq(priv, "critical",
- tsens_critical_irq_thread);
+ if (priv->feat->crit_int)
+ ret = tsens_register_irq(priv, "critical",
+ tsens_critical_irq_thread);
+ }
return ret;
}
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -493,6 +493,7 @@ enum regfield_ids {
* struct tsens_features - Features supported by the IP
* @ver_major: Major number of IP version
* @crit_int: does the IP support critical interrupts?
+ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
* @adc: do the sensors only output adc code (instead of temperature)?
* @srot_split: does the IP neatly splits the register space into SROT and TM,
* with SROT only being available to secure boot firmware?
@@ -502,6 +503,7 @@ enum regfield_ids {
struct tsens_features {
unsigned int ver_major;
unsigned int crit_int:1;
+ unsigned int combo_int:1;
unsigned int adc:1;
unsigned int srot_split:1;
unsigned int has_watchdog:1;

101
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@ -0,0 +1,101 @@
From 7805365fee582056b32c69cf35aafbb94b14a8ca Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:43 +0200
Subject: [PATCH] thermal/drivers/tsens: Allow configuring min and max trips
IPQ8074 and IPQ6018 dont support negative trip temperatures and support
up to 204 degrees C as the max trip temperature.
So, instead of always setting the -40 as min and 120 degrees C as max
allow it to be configured as part of the features.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220818220245.338396-3-robimarko@gmail.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 2 ++
drivers/thermal/qcom/tsens-v0_1.c | 2 ++
drivers/thermal/qcom/tsens-v1.c | 2 ++
drivers/thermal/qcom/tsens-v2.c | 2 ++
drivers/thermal/qcom/tsens.c | 4 ++--
drivers/thermal/qcom/tsens.h | 4 ++++
6 files changed, 14 insertions(+), 2 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_
.adc = 1,
.srot_split = 0,
.max_sensors = 11,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
struct tsens_plat_data data_8960 = {
--- a/drivers/thermal/qcom/tsens-v0_1.c
+++ b/drivers/thermal/qcom/tsens-v0_1.c
@@ -553,6 +553,8 @@ static struct tsens_features tsens_v0_1_
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
--- a/drivers/thermal/qcom/tsens-v1.c
+++ b/drivers/thermal/qcom/tsens-v1.c
@@ -277,6 +277,8 @@ static struct tsens_features tsens_v1_fe
.adc = 1,
.srot_split = 1,
.max_sensors = 11,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_fe
.adc = 0,
.srot_split = 1,
.max_sensors = 16,
+ .trip_min_temp = -40000,
+ .trip_max_temp = 120000,
};
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -573,8 +573,8 @@ static int tsens_set_trips(struct therma
dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
hw_id, __func__, low, high);
- cl_high = clamp_val(high, -40000, 120000);
- cl_low = clamp_val(low, -40000, 120000);
+ cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
+ cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
high_val = tsens_mC_to_hw(s, cl_high);
low_val = tsens_mC_to_hw(s, cl_low);
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -499,6 +499,8 @@ enum regfield_ids {
* with SROT only being available to secure boot firmware?
* @has_watchdog: does this IP support watchdog functionality?
* @max_sensors: maximum sensors supported by this version of the IP
+ * @trip_min_temp: minimum trip temperature supported by this version of the IP
+ * @trip_max_temp: maximum trip temperature supported by this version of the IP
*/
struct tsens_features {
unsigned int ver_major;
@@ -508,6 +510,8 @@ struct tsens_features {
unsigned int srot_split:1;
unsigned int has_watchdog:1;
unsigned int max_sensors;
+ int trip_min_temp;
+ int trip_max_temp;
};
/**

74
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@ -0,0 +1,74 @@
From 0164d794cbc58488a7321272e95958d10cf103a4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:44 +0200
Subject: [PATCH] thermal/drivers/tsens: Add IPQ8074 support
Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP
it only has one IRQ, that is used for up/low as well as critical.
It also does not support negative trip temperatures.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220818220245.338396-4-robimarko@gmail.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++
drivers/thermal/qcom/tsens.c | 3 +++
drivers/thermal/qcom/tsens.h | 2 +-
3 files changed, 21 insertions(+), 1 deletion(-)
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_fe
.trip_max_temp = 120000,
};
+static struct tsens_features ipq8074_feat = {
+ .ver_major = VER_2_X,
+ .crit_int = 1,
+ .combo_int = 1,
+ .adc = 0,
+ .srot_split = 1,
+ .max_sensors = 16,
+ .trip_min_temp = 0,
+ .trip_max_temp = 204000,
+};
+
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
/* ----- SROT ------ */
/* VERSION */
@@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = {
.fields = tsens_v2_regfields,
};
+struct tsens_plat_data data_ipq8074 = {
+ .ops = &ops_generic_v2,
+ .feat = &ipq8074_feat,
+ .fields = tsens_v2_regfields,
+};
+
/* Kept around for backward compatibility with old msm8996.dtsi */
struct tsens_plat_data data_8996 = {
.num_sensors = 13,
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -981,6 +981,9 @@ static const struct of_device_id tsens_t
.compatible = "qcom,ipq8064-tsens",
.data = &data_8960,
}, {
+ .compatible = "qcom,ipq8074-tsens",
+ .data = &data_ipq8074,
+ }, {
.compatible = "qcom,mdm9607-tsens",
.data = &data_9607,
}, {
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -597,6 +597,6 @@ extern struct tsens_plat_data data_8916,
extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
/* TSENS v2 targets */
-extern struct tsens_plat_data data_8996, data_tsens_v2;
+extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
#endif /* __QCOM_TSENS_H__ */

130
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@ -0,0 +1,130 @@
From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:02:45 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
IPQ8074 has a tsens v2.3.0 peripheral which monitors
temperatures around the various subsystems on the
die.
So lets add the tsens and thermal zone nodes, passive
CPU cooling will come in later patches after CPU frequency
scaling is supported.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -276,6 +276,16 @@
status = "disabled";
};
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,ipq8074-tsens";
+ reg = <0x4a9000 0x1000>, /* TM */
+ <0x4a8000 0x1000>; /* SROT */
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "combined";
+ #qcom,sensors = <16>;
+ #thermal-sensor-cells = <1>;
+ };
+
cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;
@@ -876,4 +886,90 @@
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
+
+ thermal-zones {
+ nss-top-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 4>;
+ };
+
+ nss0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 5>;
+ };
+
+ nss1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 6>;
+ };
+
+ wcss-phya0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 7>;
+ };
+
+ wcss-phya1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 8>;
+ };
+
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 9>;
+ };
+
+ cpu1_thermal: cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 10>;
+ };
+
+ cpu2_thermal: cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 11>;
+ };
+
+ cpu3_thermal: cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 12>;
+ };
+
+ cluster_thermal: cluster-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 13>;
+ };
+
+ wcss-phyb0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 14>;
+ };
+
+ wcss-phyb1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 15>;
+ };
+ };
};

29
target/linux/qualcommax/patches-6.1/0006-v6.2-arm64-dts-qcom-ipq8074-add-clocks-to-APCS.patch Normal file
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@ -0,0 +1,29 @@
From 0df592a0a1a3fff9133977192677aa915afc174f Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:08:49 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add clocks to APCS
APCS now has support for providing the APSS clocks as the child device
for IPQ8074.
So, add the A53 PLL and XO clocks in order to use APCS as the CPU
clocksource for APSS scaling.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -682,6 +682,8 @@
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
reg = <0x0b111000 0x1000>;
+ clocks = <&a53pll>, <&xo>;
+ clock-names = "pll", "xo";
#clock-cells = <1>;
#mbox-cells = <1>;

3601
target/linux/qualcommax/patches-6.1/0007-v6.2-clk-qcom-ipq8074-convert-to-parent-data.patch Normal file
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File diff suppressed because it is too large Load Diff

28
target/linux/qualcommax/patches-6.1/0008-v6.2-arm64-dts-qcom-ipq6018-fix-NAND-node-name.patch Normal file
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@ -0,0 +1,28 @@
From 8857b0ab6a562c473c5bded0efda9390b82a84d4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 27 Sep 2022 22:12:17 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: fix NAND node name
Per schema it should be nand-controller@79b0000 instead of nand@79b0000.
Fix it to match nand-controller.yaml requirements.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220927201218.1264506-1-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -348,7 +348,7 @@
status = "disabled";
};
- qpic_nand: nand@79b0000 {
+ qpic_nand: nand-controller@79b0000 {
compatible = "qcom,ipq6018-nand";
reg = <0x0 0x079b0000 0x0 0x10000>;
#address-cells = <1>;

39
target/linux/qualcommax/patches-6.1/0009-v6.2-dt-bindings-clock-qcom-ipq8074-add-missing-networkin.patch Normal file
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@ -0,0 +1,39 @@
From e78a40eb24187a8b4f9b89e2181f674df39c2013 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 7 Nov 2022 14:29:00 +0100
Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add missing networking
resets
Add bindings for the missing networking resets found in IPQ8074 GCC.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107132901.489240-2-robimarko@gmail.com
---
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -367,6 +367,20 @@
#define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
+#define GCC_PPE_FULL_RESET 132
+#define GCC_UNIPHY0_SOFT_RESET 133
+#define GCC_UNIPHY0_XPCS_RESET 134
+#define GCC_UNIPHY1_SOFT_RESET 135
+#define GCC_UNIPHY1_XPCS_RESET 136
+#define GCC_UNIPHY2_SOFT_RESET 137
+#define GCC_UNIPHY2_XPCS_RESET 138
+#define GCC_EDMA_HW_RESET 139
+#define GCC_NSSPORT1_RESET 140
+#define GCC_NSSPORT2_RESET 141
+#define GCC_NSSPORT3_RESET 142
+#define GCC_NSSPORT4_RESET 143
+#define GCC_NSSPORT5_RESET 144
+#define GCC_NSSPORT6_RESET 145
#define USB0_GDSC 0
#define USB1_GDSC 1

41
target/linux/qualcommax/patches-6.1/0010-v6.2-clk-qcom-ipq8074-add-missing-networking-resets.patch Normal file
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@ -0,0 +1,41 @@
From da76cb63d04dc22ed32123b8c1d084c006d67bfb Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 7 Nov 2022 14:29:01 +0100
Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets
Downstream QCA 5.4 kernel defines networking resets which are not present
in the mainline kernel but are required for the networking drivers.
So, port the downstream resets and avoid using magic values for mask,
construct mask for resets which require multiple bits to be set/cleared.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
---
drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4665,6 +4665,20 @@ static const struct qcom_reset_map gcc_i
[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
+ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
+ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
+ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
+ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
+ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
+ [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
+ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
+ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
+ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
+ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
+ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
+ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
+ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
+ [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
};
static struct gdsc *gcc_ipq8074_gdscs[] = {

152
target/linux/qualcommax/patches-6.1/0011-v6.2-clk-qcom-ipq8074-populate-fw_name-for-all-parents.patch Normal file
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@ -0,0 +1,152 @@
From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 16 Nov 2022 22:46:55 +0100
Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
It appears that having only .name populated in parent_data for clocks
which are only globally searchable currently will not work as the clk core
won't copy that name if there is no .fw_name present as well.
So, populate .fw_name for all parent clocks in parent_data.
Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
---
drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
1 file changed, 26 insertions(+), 26 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -674,7 +674,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
};
static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
- { .name = "pcie20_phy0_pipe_clk" },
+ { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
@@ -727,7 +727,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
};
static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
- { .name = "pcie20_phy1_pipe_clk" },
+ { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
@@ -1131,7 +1131,7 @@ static const struct freq_tbl ftbl_nss_no
static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "bias_pll_nss_noc_clk" },
+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
@@ -1356,7 +1356,7 @@ static const struct freq_tbl ftbl_nss_pp
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &nss_crypto_pll.clkr.hw },
@@ -1407,10 +1407,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_rx_clk" },
- { .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
@@ -1459,10 +1459,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_tx_clk" },
- { .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
@@ -1690,12 +1690,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_rx_clk" },
- { .name = "uniphy0_gcc_tx_clk" },
- { .name = "uniphy1_gcc_rx_clk" },
- { .name = "uniphy1_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -1752,12 +1752,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy0_gcc_tx_clk" },
- { .name = "uniphy0_gcc_rx_clk" },
- { .name = "uniphy1_gcc_tx_clk" },
- { .name = "uniphy1_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -1814,10 +1814,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy2_gcc_rx_clk" },
- { .name = "uniphy2_gcc_tx_clk" },
+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
@@ -1871,10 +1871,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo", .name = "xo" },
- { .name = "uniphy2_gcc_tx_clk" },
- { .name = "uniphy2_gcc_rx_clk" },
+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {

36
target/linux/qualcommax/patches-6.1/0012-v6.2-arm64-dts-qcom-ipq8074-pass-XO-and-sleep-clocks-to-G.patch Normal file
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@ -0,0 +1,36 @@
From 9033c3c86ea0dd35bd2ab957317573b755967298 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 30 Oct 2022 18:57:03 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: pass XO and sleep clocks to GCC
Pass XO and sleep clocks to the GCC controller so it does not have to
find them by matching globaly by name.
If not passed directly, driver maintains backwards compatibility by then
falling back to global lookup.
Since we are here, set cell numbers in decimal instead of hex.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -363,9 +363,11 @@
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
- #clock-cells = <0x1>;
+ clocks = <&xo>, <&sleep_clk>;
+ clock-names = "xo", "sleep_clk";
+ #clock-cells = <1>;
#power-domain-cells = <1>;
- #reset-cells = <0x1>;
+ #reset-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {

149
target/linux/qualcommax/patches-6.1/0013-v6.2-arm64-dts-qcom-add-PMP8074-DTSI.patch Normal file
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@ -0,0 +1,149 @@
From fb76b808f8628215afebaf0f8af0bde635302590 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:18:14 +0200
Subject: [PATCH] arm64: dts: qcom: add PMP8074 DTSI
PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is
controlled via SPMI.
Add DTSI for it providing GPIO, regulator, RTC and VADC support.
RTC is disabled by default as there is no built-in battery so it will
loose time unless board vendor added a battery, so make it optional.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ pmic@0 {
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmp8074_adc: adc@3100 {
+ compatible = "qcom,spmi-adc-rev2";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref-vadc@2 {
+ reg = <ADC5_VREF_VADC>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmic_die: die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm: xo-temp@76 {
+ reg = <ADC5_XO_THERM_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1: thermistor1@77 {
+ reg = <ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2: thermistor2@78 {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm3: thermistor3@79 {
+ reg = <ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph-pwr@131 {
+ reg = <ADC5_VPH_PWR>;
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
+ pmp8074_rtc: rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ allow-set-time;
+ status = "disabled";
+ };
+
+ pmp8074_gpios: gpio@c000 {
+ compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmp8074_gpios 0 0 12>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@1 {
+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+
+ regulators {
+ compatible = "qcom,pmp8074-regulators";
+
+ s3: s3 {
+ regulator-name = "vdd_s3";
+ regulator-min-microvolt = <592000>;
+ regulator-max-microvolt = <1064000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ s4: s4 {
+ regulator-name = "vdd_s4";
+ regulator-min-microvolt = <712000>;
+ regulator-max-microvolt = <992000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ l11: l11 {
+ regulator-name = "l11";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};

37
target/linux/qualcommax/patches-6.1/0014-v6.2-arm64-dts-qcom-ipq8074-hk01-add-VQMMC-supply.patch Normal file
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@ -0,0 +1,37 @@
From 2c394cfc1779886048feca7dc7f4075da5f6328c Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 19 Aug 2022 00:18:15 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply
Since now we have control over the PMP8074 PMIC providing various system
voltages including L11 which provides the SDIO/eMMC I/O voltage set it as
the SDHCI VQMMC supply.
This allows SDHCI controller to switch to 1.8V I/O mode and support high
speed modes like HS200 and HS400.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -3,6 +3,7 @@
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#include "ipq8074.dtsi"
+#include "pmp8074.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
@@ -84,6 +85,7 @@
&sdhc_1 {
status = "okay";
+ vqmmc-supply = <&l11>;
};
&qusb_phy_0 {

42
target/linux/qualcommax/patches-6.1/0015-v6.2-arm64-dts-qcom-hk01-use-GPIO-flags-for-tlmm.patch Normal file
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@ -0,0 +1,42 @@
From 82ceb86227b1fc15c76d5fc691b2bf425f1a63b3 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Mon, 7 Nov 2022 10:29:30 +0100
Subject: [PATCH] arm64: dts: qcom: hk01: use GPIO flags for tlmm
Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of
harcoding the cell value.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107092930.33325-3-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -4,6 +4,7 @@
*/
#include "ipq8074.dtsi"
#include "pmp8074.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
@@ -52,12 +53,12 @@
&pcie0 {
status = "okay";
- perst-gpios = <&tlmm 61 0x1>;
+ perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 58 0x1>;
+ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie_qmp0 {

82
target/linux/qualcommax/patches-6.1/0016-v6.2-arm64-dts-qcom-ipq8074-Fix-up-comments.patch Normal file
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@ -0,0 +1,82 @@
From 1b1c1423ca3e740984aa883512a72c4ea08fbe28 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 7 Nov 2022 15:55:17 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074-*: Fix up comments
Make sure all multiline C-style commends begin with just '/*' with
the comment text starting on a new line.
Also, fix up some whitespace within comments.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107145522.6706-8-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 3 ++-
arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts | 3 ++-
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts | 3 ++-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++------
4 files changed, 12 insertions(+), 9 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#include "ipq8074.dtsi"
#include "pmp8074.dtsi"
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
/dts-v1/;
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#include "ipq8074-hk10.dtsi"
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -129,10 +129,10 @@
status = "disabled";
usb1_ssphy: phy@58200 {
- reg = <0x00058200 0x130>, /* Tx */
+ reg = <0x00058200 0x130>, /* Tx */
<0x00058400 0x200>, /* Rx */
- <0x00058800 0x1f8>, /* PCS */
- <0x00058600 0x044>; /* PCS misc*/
+ <0x00058800 0x1f8>, /* PCS */
+ <0x00058600 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
@@ -172,10 +172,10 @@
status = "disabled";
usb0_ssphy: phy@78200 {
- reg = <0x00078200 0x130>, /* Tx */
+ reg = <0x00078200 0x130>, /* Tx */
<0x00078400 0x200>, /* Rx */
- <0x00078800 0x1f8>, /* PCS */
- <0x00078600 0x044>; /* PCS misc*/
+ <0x00078800 0x1f8>, /* PCS */
+ <0x00078600 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;

60
target/linux/qualcommax/patches-6.1/0017-v6.2-arm64-dts-qcom-ipq8074-align-TLMM-pin-configuration-.patch Normal file
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@ -0,0 +1,60 @@
From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Tue, 8 Nov 2022 15:23:57 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
DT schema
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -320,35 +320,35 @@
interrupt-controller;
#interrupt-cells = <0x2>;
- serial_4_pins: serial4-pinmux {
+ serial_4_pins: serial4-state {
pins = "gpio23", "gpio24";
function = "blsp4_uart1";
drive-strength = <8>;
bias-disable;
};
- i2c_0_pins: i2c-0-pinmux {
+ i2c_0_pins: i2c-0-state {
pins = "gpio42", "gpio43";
function = "blsp1_i2c";
drive-strength = <8>;
bias-disable;
};
- spi_0_pins: spi-0-pins {
+ spi_0_pins: spi-0-state {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
bias-disable;
};
- hsuart_pins: hsuart-pins {
+ hsuart_pins: hsuart-state {
pins = "gpio46", "gpio47", "gpio48", "gpio49";
function = "blsp2_uart";
drive-strength = <8>;
bias-disable;
};
- qpic_pins: qpic-pins {
+ qpic_pins: qpic-state {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",

56
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@ -0,0 +1,56 @@
From 20afb6751739264ea41993877de93923911dfdc3 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Thu, 6 Oct 2022 14:46:27 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: align TLMM pin configuration with
DT schema
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221006124659.217540-3-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++--
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -51,13 +51,13 @@
};
&tlmm {
- i2c_1_pins: i2c-1-pins {
+ i2c_1_pins: i2c-1-state {
pins = "gpio42", "gpio43";
function = "blsp2_i2c";
drive-strength = <8>;
};
- spi_0_pins: spi-0-pins {
+ spi_0_pins: spi-0-state {
pins = "gpio38", "gpio39", "gpio40", "gpio41";
function = "blsp0_spi";
drive-strength = <8>;
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -218,14 +218,14 @@
interrupt-controller;
#interrupt-cells = <2>;
- serial_3_pins: serial3-pinmux {
+ serial_3_pins: serial3-state {
pins = "gpio44", "gpio45";
function = "blsp2_uart";
drive-strength = <8>;
bias-pull-down;
};
- qpic_pins: qpic-pins {
+ qpic_pins: qpic-state {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",

24
target/linux/qualcommax/patches-6.1/0019-v6.3-arm64-dts-qcom-ipq8074-set-Gen2-PCIe-pcie-max-link-s.patch Normal file
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@ -0,0 +1,24 @@
From a4748d2850783d36f77ccf2b5fcc86ccf1800ef1 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 16 Nov 2022 22:48:36 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed
Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
generation limit.
This allows the generic DWC code to configure the link speed correctly.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -768,6 +768,7 @@
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
+ max-link-speed = <2>;
#address-cells = <3>;
#size-cells = <2>;

26
target/linux/qualcommax/patches-6.1/0020-v6.3-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch Normal file
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@ -0,0 +1,26 @@
From f356132229b18ceef5d5ef9103bbaa9bdeb84c8d Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 13 Jan 2023 17:44:47 +0100
Subject: [PATCH] PCI: qcom: Add IPQ8074 Gen3 port support
IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
Add compatible for Gen3 port which uses the same controller as IPQ6018.
Link: https://lore.kernel.org/r/20230113164449.906002-7-robimarko@gmail.com
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1762,6 +1762,7 @@ static const struct of_device_id qcom_pc
{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
+ { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },

38
target/linux/qualcommax/patches-6.1/0021-v6.3-clk-qcom-ipq8074-populate-fw_name-for-usb3phy-s.patch Normal file
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@ -0,0 +1,38 @@
From 614d31c231c7707322b643f409eeb7e28adc7f8c Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 8 Jan 2023 13:36:28 +0100
Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for usb3phy-s
Having only .name populated in parent_data for clocks which are only
globally searchable currently will not work as the clk core won't copy
that name if there is no .fw_name present as well.
So, populate .fw_name for usb3phy clocks in parent_data as they were
missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/clk/qcom/gcc-ipq8074.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -928,7 +928,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
};
static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
- { .name = "usb3phy_0_cc_pipe_clk" },
+ { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};
@@ -996,7 +996,7 @@ static struct clk_rcg2 usb1_mock_utmi_cl
};
static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
- { .name = "usb3phy_1_cc_pipe_clk" },
+ { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
{ .fw_name = "xo", .name = "xo" },
};

26
target/linux/qualcommax/patches-6.1/0022-v6.4-arm64-dts-qcom-ipq8074-add-compatible-fallback-to.patch Normal file
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@ -0,0 +1,26 @@
From d93bd4630ce163f3761aedc0b342b072bee6db6b Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 22 Mar 2023 18:41:40 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: add compatible fallback to mailbox
IPQ8074 mailbox is compatible with IPQ6018.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-4-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -682,7 +682,8 @@
};
apcs_glb: mailbox@b111000 {
- compatible = "qcom,ipq8074-apcs-apps-global";
+ compatible = "qcom,ipq8074-apcs-apps-global",
+ "qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
clocks = <&a53pll>, <&xo>;
clock-names = "pll", "xo";

199
target/linux/qualcommax/patches-6.1/0023-v6.5-arm64-dts-qcom-ipq8074-add-critical-thermal-trips.patch Normal file
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@ -0,0 +1,199 @@
From 56d3067cb694ba60d654e7f5ef231b6fabc4697f Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 7 Jun 2023 20:44:48 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add critical thermal trips
According to bindings, thermal zones must have associated trips as well.
Since we currently dont have CPUFreq support and thus no passive cooling
lets start by defining critical trips to protect the devices against
severe overheating.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -899,6 +899,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
+
+ trips {
+ nss-top-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
nss0-thermal {
@@ -906,6 +914,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
+
+ trips {
+ nss-0-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
nss1-thermal {
@@ -913,6 +929,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 6>;
+
+ trips {
+ nss-1-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
wcss-phya0-thermal {
@@ -920,6 +944,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
+
+ trips {
+ wcss-phya0-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
wcss-phya1-thermal {
@@ -927,6 +959,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
+
+ trips {
+ wcss-phya1-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
cpu0_thermal: cpu0-thermal {
@@ -934,6 +974,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 9>;
+
+ trips {
+ cpu0-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
cpu1_thermal: cpu1-thermal {
@@ -941,6 +989,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 10>;
+
+ trips {
+ cpu1-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
cpu2_thermal: cpu2-thermal {
@@ -948,6 +1004,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 11>;
+
+ trips {
+ cpu2-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
cpu3_thermal: cpu3-thermal {
@@ -955,6 +1019,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 12>;
+
+ trips {
+ cpu3-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
cluster_thermal: cluster-thermal {
@@ -962,6 +1034,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 13>;
+
+ trips {
+ cluster-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
wcss-phyb0-thermal {
@@ -969,6 +1049,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 14>;
+
+ trips {
+ wcss-phyb0-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
wcss-phyb1-thermal {
@@ -976,6 +1064,14 @@
polling-delay = <1000>;
thermal-sensors = <&tsens 15>;
+
+ trips {
+ wcss-phyb1-crit {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
};
};
};

29
target/linux/qualcommax/patches-6.1/0024-v6.7-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ8174-family.patch Normal file
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@ -0,0 +1,29 @@
From 93e161c8f4b9b051e5e746814138cb5520b4b897 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 1 Sep 2023 20:10:04 +0200
Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ8174 family
IPQ8174 (Oak) family is part of the IPQ8074 family, but the ID-s for it
are missing so lets add them.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Kathiravan T <quic_kathirav@quicinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230901181041.1538999-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
include/dt-bindings/arm/qcom,ids.h | 3 +++
1 file changed, 3 insertions(+)
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -121,6 +121,9 @@
#define QCOM_ID_SM6125 394
#define QCOM_ID_IPQ8070A 395
#define QCOM_ID_IPQ8071A 396
+#define QCOM_ID_IPQ8172 397
+#define QCOM_ID_IPQ8173 398
+#define QCOM_ID_IPQ8174 399
#define QCOM_ID_IPQ6018 402
#define QCOM_ID_IPQ6028 403
#define QCOM_ID_IPQ6000 421

123
target/linux/qualcommax/patches-6.1/0025-v6.7-cpufreq-qcom-nvmem-add-support-for-IPQ6018.patch Normal file
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@ -0,0 +1,123 @@
From 47e161a7873b0891f4e01a69a839f6161d816ea8 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 25 Oct 2023 14:57:57 +0530
Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ6018
IPQ6018 SoC series comes in multiple SKU-s, and not all of them support
high frequency OPP points.
SoC itself does however have a single bit in QFPROM to indicate the CPU
speed-bin.
That bit is used to indicate frequency limit of 1.5GHz, but that alone is
not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to
limit it further.
IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device
will get created by NVMEM CPUFreq driver.
Signed-off-by: Robert Marko <robimarko@gmail.com>
[ Viresh: Fixed rebase conflict. ]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++
2 files changed, 59 insertions(+)
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -163,6 +163,7 @@ static const struct of_device_id blockli
{ .compatible = "ti,dra7", },
{ .compatible = "ti,omap3", },
+ { .compatible = "qcom,ipq6018", },
{ .compatible = "qcom,ipq8064", },
{ .compatible = "qcom,apq8064", },
{ .compatible = "qcom,msm8974", },
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -31,6 +31,8 @@
#include <dt-bindings/arm/qcom,ids.h>
+#define IPQ6000_VERSION BIT(2)
+
struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
@@ -204,6 +206,57 @@ len_error:
return ret;
}
+static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
+ struct qcom_cpufreq_drv *drv)
+{
+ u32 msm_id;
+ int ret;
+ u8 *speedbin;
+ *pvs_name = NULL;
+
+ ret = qcom_smem_get_soc_id(&msm_id);
+ if (ret)
+ return ret;
+
+ speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
+ if (IS_ERR(speedbin))
+ return PTR_ERR(speedbin);
+
+ switch (msm_id) {
+ case QCOM_ID_IPQ6005:
+ case QCOM_ID_IPQ6010:
+ case QCOM_ID_IPQ6018:
+ case QCOM_ID_IPQ6028:
+ /* Fuse Value Freq BIT to set
+ * ---------------------------------
+ * 2’b0 No Limit BIT(0)
+ * 2’b1 1.5 GHz BIT(1)
+ */
+ drv->versions = 1 << (unsigned int)(*speedbin);
+ break;
+ case QCOM_ID_IPQ6000:
+ /*
+ * IPQ6018 family only has one bit to advertise the CPU
+ * speed-bin, but that is not enough for IPQ6000 which
+ * is only rated up to 1.2GHz.
+ * So for IPQ6000 manually set BIT(2) based on SMEM ID.
+ */
+ drv->versions = IPQ6000_VERSION;
+ break;
+ default:
+ dev_err(cpu_dev,
+ "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
+ msm_id);
+ drv->versions = IPQ6000_VERSION;
+ break;
+ }
+
+ kfree(speedbin);
+ return 0;
+}
+
static const struct qcom_cpufreq_match_data match_data_kryo = {
.get_version = qcom_cpufreq_kryo_name_version,
};
@@ -218,6 +271,10 @@ static const struct qcom_cpufreq_match_d
.genpd_names = qcs404_genpd_names,
};
+static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
+ .get_version = qcom_cpufreq_ipq6018_name_version,
+};
+
static int qcom_cpufreq_probe(struct platform_device *pdev)
{
struct qcom_cpufreq_drv *drv;
@@ -362,6 +419,7 @@ static const struct of_device_id qcom_cp
{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
+ { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },

113
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@ -0,0 +1,113 @@
From 0b9cd949136f1b63f7aa9424b6e583a1ab261e36 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 13 Oct 2023 19:20:02 +0200
Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
IPQ8074 comes in 3 families:
* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz
* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
So, in order to be able to share one OPP table lets add support for IPQ8074
family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
will get created by NVMEM CPUFreq driver.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[ Viresh: Fixed rebase conflict. ]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -165,6 +165,7 @@ static const struct of_device_id blockli
{ .compatible = "qcom,ipq6018", },
{ .compatible = "qcom,ipq8064", },
+ { .compatible = "qcom,ipq8074", },
{ .compatible = "qcom,apq8064", },
{ .compatible = "qcom,msm8974", },
{ .compatible = "qcom,msm8960", },
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -33,6 +33,11 @@
#define IPQ6000_VERSION BIT(2)
+enum ipq8074_versions {
+ IPQ8074_HAWKEYE_VERSION = 0,
+ IPQ8074_ACORN_VERSION,
+};
+
struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
@@ -257,6 +262,44 @@ static int qcom_cpufreq_ipq6018_name_ver
return 0;
}
+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
+ struct qcom_cpufreq_drv *drv)
+{
+ u32 msm_id;
+ int ret;
+ *pvs_name = NULL;
+
+ ret = qcom_smem_get_soc_id(&msm_id);
+ if (ret)
+ return ret;
+
+ switch (msm_id) {
+ case QCOM_ID_IPQ8070A:
+ case QCOM_ID_IPQ8071A:
+ case QCOM_ID_IPQ8172:
+ case QCOM_ID_IPQ8173:
+ case QCOM_ID_IPQ8174:
+ drv->versions = BIT(IPQ8074_ACORN_VERSION);
+ break;
+ case QCOM_ID_IPQ8072A:
+ case QCOM_ID_IPQ8074A:
+ case QCOM_ID_IPQ8076A:
+ case QCOM_ID_IPQ8078A:
+ drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
+ break;
+ default:
+ dev_err(cpu_dev,
+ "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
+ msm_id);
+ drv->versions = BIT(IPQ8074_ACORN_VERSION);
+ break;
+ }
+
+ return 0;
+}
+
static const struct qcom_cpufreq_match_data match_data_kryo = {
.get_version = qcom_cpufreq_kryo_name_version,
};
@@ -275,6 +318,10 @@ static const struct qcom_cpufreq_match_d
.get_version = qcom_cpufreq_ipq6018_name_version,
};
+static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
+ .get_version = qcom_cpufreq_ipq8074_name_version,
+};
+
static int qcom_cpufreq_probe(struct platform_device *pdev)
{
struct qcom_cpufreq_drv *drv;
@@ -421,6 +468,7 @@ static const struct of_device_id qcom_cp
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
{ .compatible = "qcom,msm8960", .data = &match_data_krait },

43
target/linux/qualcommax/patches-6.1/0027-v6.7-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch Normal file
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@ -0,0 +1,43 @@
From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001
From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Date: Thu, 14 Sep 2023 12:29:57 +0530
Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock
provider
While the kernel is booting up, APSS PLL will be running at 800MHz with
GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
configured and select the rate based on the opp table and the source will
be changed to APSS_PLL_EARLY.
Without this patch, CPU Freq driver reports that CPU is running at 24MHz
instead of the 800MHz.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
drivers/clk/qcom/apss-ipq6018.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/clk/qcom/apss-ipq6018.c
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -20,16 +20,19 @@
enum {
P_XO,
+ P_GPLL0,
P_APSS_PLL_EARLY,
};
static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
{ .fw_name = "xo" },
+ { .fw_name = "gpll0" },
{ .fw_name = "pll" },
};
static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
{ P_XO, 0 },
+ { P_GPLL0, 4 },
{ P_APSS_PLL_EARLY, 5 },
};

32
target/linux/qualcommax/patches-6.1/0028-v6.7-arm64-dts-qcom-ipq8074-include-the-GPLL0-as-clock-pr.patch Normal file
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@ -0,0 +1,32 @@
From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001
From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Date: Thu, 14 Sep 2023 12:29:58 +0530
Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock
provider for mailbox
While the kernel is booting up, APSS PLL will be running at 800MHz with
GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
configured to the rate based on the opp table and the source also will
be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
with this inclusion, CPU Freq correctly reports that CPU is running at
800MHz rather than 24MHz.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -685,8 +685,8 @@
compatible = "qcom,ipq8074-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
- clocks = <&a53pll>, <&xo>;
- clock-names = "pll", "xo";
+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
#clock-cells = <1>;
#mbox-cells = <1>;

27
target/linux/qualcommax/patches-6.1/0029-v6.3-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ5332-and-its.patch Normal file
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@ -0,0 +1,27 @@
From c0877a26b7ee54ef30d16ffdcdd37f2bcffe518e Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Wed, 8 Feb 2023 11:27:08 +0530
Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ5332 and its
variant
Add SOC ID for Qualcomm IPQ5332 and IPQ5322 variants.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208055709.13162-2-quic_kathirav@quicinc.com
---
include/dt-bindings/arm/qcom,ids.h | 2 ++
1 file changed, 2 insertions(+)
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -143,6 +143,8 @@
#define QCOM_ID_SC7280 487
#define QCOM_ID_SC7180P 495
#define QCOM_ID_SM6375 507
+#define QCOM_ID_IPQ5332 592
+#define QCOM_ID_IPQ5322 593
/*
* The board type and revision information, used by Qualcomm bootloaders and

33
target/linux/qualcommax/patches-6.1/0030-v6.4-dt-bindings-arm-qcom-ids-Add-IDs-for-IPQ9574-and-its.patch Normal file
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@ -0,0 +1,33 @@
From 725352e15e1d030885611a546eb1f2884851a407 Mon Sep 17 00:00:00 2001
From: Varadarajan Narayanan <quic_varada@quicinc.com>
Date: Tue, 14 Mar 2023 11:43:33 +0530
Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ9574 and its
variants
Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550,
IPQ9514 and IPQ9510
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1678774414-14414-2-git-send-email-quic_varada@quicinc.com
---
include/dt-bindings/arm/qcom,ids.h | 6 ++++++
1 file changed, 6 insertions(+)
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -143,6 +143,12 @@
#define QCOM_ID_SC7280 487
#define QCOM_ID_SC7180P 495
#define QCOM_ID_SM6375 507
+#define QCOM_ID_IPQ9514 510
+#define QCOM_ID_IPQ9550 511
+#define QCOM_ID_IPQ9554 512
+#define QCOM_ID_IPQ9570 513
+#define QCOM_ID_IPQ9574 514
+#define QCOM_ID_IPQ9510 521
#define QCOM_ID_IPQ5332 592
#define QCOM_ID_IPQ5322 593

28
target/linux/qualcommax/patches-6.1/0031-v6.5-dt-bindings-arm-qcom-ids-add-SoC-ID-for-IPQ5312-and-.patch Normal file
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@ -0,0 +1,28 @@
From 614c778cf0d570642c50715adfa0b70930d8cf29 Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Tue, 9 May 2023 09:05:30 +0530
Subject: [PATCH] dt-bindings: arm: qcom,ids: add SoC ID for IPQ5312 and
IPQ5302
Add the SoC ID for IPQ5312 and IPQ5302, which belong to the family of
IPQ5332 SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230509033531.21468-2-quic_kathirav@quicinc.com
---
include/dt-bindings/arm/qcom,ids.h | 2 ++
1 file changed, 2 insertions(+)
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -151,6 +151,8 @@
#define QCOM_ID_IPQ9510 521
#define QCOM_ID_IPQ5332 592
#define QCOM_ID_IPQ5322 593
+#define QCOM_ID_IPQ5312 594
+#define QCOM_ID_IPQ5302 595
/*
* The board type and revision information, used by Qualcomm bootloaders and

25
target/linux/qualcommax/patches-6.1/0032-v6.5-dt-bindings-arm-qcom-ids-add-SoC-ID-for-IPQ5300.patch Normal file
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@ -0,0 +1,25 @@
From b3c72f2795467e3d43ee429b0ebd5f523ec08f60 Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Mon, 5 Jun 2023 13:35:28 +0530
Subject: [PATCH] dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300
Add the SoC ID for IPQ5300, which belong to the family of IPQ5332 SoC.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230605080531.3879-2-quic_kathirav@quicinc.com
---
include/dt-bindings/arm/qcom,ids.h | 1 +
1 file changed, 1 insertion(+)
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -153,6 +153,7 @@
#define QCOM_ID_IPQ5322 593
#define QCOM_ID_IPQ5312 594
#define QCOM_ID_IPQ5302 595
+#define QCOM_ID_IPQ5300 624
/*
* The board type and revision information, used by Qualcomm bootloaders and

52
target/linux/qualcommax/patches-6.1/0033-v6.2-arm64-dts-qcom-ipq6018-move-ARMv8-timer-out-of-SoC.patch Normal file
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@ -0,0 +1,52 @@
From feeef118fda562cf9081edef8ad464d89db070f4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 27 Sep 2022 22:12:18 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node
The ARM timer is usually considered not part of SoC node, just like
other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220927201218.1264506-2-robimarko@gmail.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -510,14 +510,6 @@
clock-names = "xo";
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -769,6 +761,14 @@
};
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
wcss: wcss-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;

605
target/linux/qualcommax/patches-6.1/0034-v6.3-arm64-dts-qcom-ipq6018-Sort-nodes-properly.patch Normal file
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@ -0,0 +1,605 @@
From 2c6e322a41c5e1ca45be50b9d5fbcda62dc23a0d Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 2 Jan 2023 10:46:28 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: Sort nodes properly
Order nodes by unit address if one exists and alphabetically otherwise.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 562 +++++++++++++-------------
1 file changed, 281 insertions(+), 281 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -87,6 +87,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq6018", "qcom,scm";
+ };
+ };
+
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
@@ -123,12 +129,6 @@
};
};
- firmware {
- scm {
- compatible = "qcom,scm-ipq6018", "qcom,scm";
- };
- };
-
pmuv8: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
@@ -166,6 +166,28 @@
};
};
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: glink-channel {
+ compatible = "qcom,rpm-ipq6018";
+ qcom,glink-channels = "rpm_requests";
+
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq6018_s2: s2 {
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1062500>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
@@ -179,6 +201,102 @@
dma-ranges;
compatible = "simple-bus";
+ qusb_phy_1: qusb@59000 {
+ compatible = "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x00059000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
+ status = "disabled";
+ };
+
+ ssphy_0: ssphy@78000 {
+ compatible = "qcom,ipq6018-qmp-usb3-phy";
+ reg = <0x0 0x00078000 0x0 0x1c4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb0_ssphy: phy@78200 {
+ reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
+ <0x0 0x00078400 0x0 0x200>, /* Rx */
+ <0x0 0x00078800 0x0 0x1f8>, /* PCS */
+ <0x0 0x00078600 0x0 0x044>; /* PCS misc */
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_usb0_pipe_clk_src";
+ };
+ };
+
+ qusb_phy_0: qusb@79000 {
+ compatible = "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x00079000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ pcie_phy: phy@84000 {
+ compatible = "qcom,ipq6018-qmp-pcie-phy";
+ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+
+ pcie_phy0: phy@84200 {
+ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
+ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
+ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
+ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie0_pipe_clk_src";
+ #clock-cells = <0>;
+ };
+ };
+
+ mdio: mdio@90000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
+ reg = <0x0 0x00090000 0x0 0x64>;
+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
+ clock-names = "gcc_mdio_ahb_clk";
+ status = "disabled";
+ };
+
prng: qrng@e1000 {
compatible = "qcom,prng-ee";
reg = <0x0 0x000e3000 0x0 0x1000>;
@@ -257,6 +375,41 @@
reg = <0x0 0x01937000 0x0 0x21000>;
};
+ usb2: usb@70f8800 {
+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+ reg = <0x0 0x070F8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_USB1_MASTER_CLK>,
+ <&gcc GCC_USB1_SLEEP_CLK>,
+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ clock-names = "core",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <24000000>;
+ resets = <&gcc GCC_USB1_BCR>;
+ status = "disabled";
+
+ dwc_1: usb@7000000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x07000000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_1>;
+ phy-names = "usb2-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07884000 0x0 0x2b000>;
@@ -366,6 +519,49 @@
status = "disabled";
};
+ usb3: usb@8af8800 {
+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
+ reg = <0x0 0x08af8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <133330000>,
+ <133330000>,
+ <24000000>;
+
+ resets = <&gcc GCC_USB0_BCR>;
+ status = "disabled";
+
+ dwc_0: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x08a00000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ clocks = <&xo>;
+ clock-names = "ref";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
#address-cells = <2>;
@@ -386,105 +582,6 @@
};
};
- pcie_phy: phy@84000 {
- compatible = "qcom,ipq6018-qmp-pcie-phy";
- reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&gcc GCC_PCIE0_AUX_CLK>,
- <&gcc GCC_PCIE0_AHB_CLK>;
- clock-names = "aux", "cfg_ahb";
-
- resets = <&gcc GCC_PCIE0_PHY_BCR>,
- <&gcc GCC_PCIE0PHY_PHY_BCR>;
- reset-names = "phy",
- "common";
-
- pcie_phy0: phy@84200 {
- reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
- <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
- <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
- <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "gcc_pcie0_pipe_clk_src";
- #clock-cells = <0>;
- };
- };
-
- pcie0: pci@20000000 {
- compatible = "qcom,pcie-ipq6018";
- reg = <0x0 0x20000000 0x0 0xf1d>,
- <0x0 0x20000f20 0x0 0xa8>,
- <0x0 0x20001000 0x0 0x1000>,
- <0x0 0x80000 0x0 0x4000>,
- <0x0 0x20100000 0x0 0x1000>;
- reg-names = "dbi", "elbi", "atu", "parf", "config";
-
- device_type = "pci";
- linux,pci-domain = <0>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
- max-link-speed = <3>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- phys = <&pcie_phy0>;
- phy-names = "pciephy";
-
- ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
- <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
-
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 75
- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 78
- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 79
- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 83
- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-
- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
- <&gcc GCC_PCIE0_AXI_M_CLK>,
- <&gcc GCC_PCIE0_AXI_S_CLK>,
- <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
- <&gcc PCIE0_RCHNG_CLK>;
- clock-names = "iface",
- "axi_m",
- "axi_s",
- "axi_bridge",
- "rchng";
-
- resets = <&gcc GCC_PCIE0_PIPE_ARES>,
- <&gcc GCC_PCIE0_SLEEP_ARES>,
- <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
- <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
- <&gcc GCC_PCIE0_AHB_ARES>,
- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
- <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
- reset-names = "pipe",
- "sleep",
- "sticky",
- "axi_m",
- "axi_s",
- "ahb",
- "axi_m_sticky",
- "axi_s_sticky";
-
- status = "disabled";
- };
-
watchdog@b017000 {
compatible = "qcom,kpss-wdt";
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
@@ -617,147 +714,74 @@
};
};
- mdio: mdio@90000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
- reg = <0x0 0x00090000 0x0 0x64>;
- clocks = <&gcc GCC_MDIO_AHB_CLK>;
- clock-names = "gcc_mdio_ahb_clk";
- status = "disabled";
- };
-
- qusb_phy_1: qusb@59000 {
- compatible = "qcom,ipq6018-qusb2-phy";
- reg = <0x0 0x00059000 0x0 0x180>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "cfg_ahb", "ref";
-
- resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
- status = "disabled";
- };
-
- usb2: usb@70f8800 {
- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
- reg = <0x0 0x070F8800 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- clocks = <&gcc GCC_USB1_MASTER_CLK>,
- <&gcc GCC_USB1_SLEEP_CLK>,
- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
- clock-names = "core",
- "sleep",
- "mock_utmi";
-
- assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
- assigned-clock-rates = <133330000>,
- <24000000>;
- resets = <&gcc GCC_USB1_BCR>;
- status = "disabled";
-
- dwc_1: usb@7000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x07000000 0x0 0xcd00>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_1>;
- phy-names = "usb2-phy";
- tx-fifo-resize;
- snps,is-utmi-l1-suspend;
- snps,hird-threshold = /bits/ 8 <0x0>;
- snps,dis_u2_susphy_quirk;
- snps,dis_u3_susphy_quirk;
- dr_mode = "host";
- };
- };
+ pcie0: pci@20000000 {
+ compatible = "qcom,pcie-ipq6018";
+ reg = <0x0 0x20000000 0x0 0xf1d>,
+ <0x0 0x20000f20 0x0 0xa8>,
+ <0x0 0x20001000 0x0 0x1000>,
+ <0x0 0x80000 0x0 0x4000>,
+ <0x0 0x20100000 0x0 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
- ssphy_0: ssphy@78000 {
- compatible = "qcom,ipq6018-qmp-usb3-phy";
- reg = <0x0 0x00078000 0x0 0x1c4>;
- #address-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ max-link-speed = <3>;
+ #address-cells = <3>;
#size-cells = <2>;
- ranges;
-
- clocks = <&gcc GCC_USB0_AUX_CLK>,
- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
-
- resets = <&gcc GCC_USB0_PHY_BCR>,
- <&gcc GCC_USB3PHY_0_PHY_BCR>;
- reset-names = "phy","common";
- status = "disabled";
-
- usb0_ssphy: phy@78200 {
- reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
- <0x0 0x00078400 0x0 0x200>, /* Rx */
- <0x0 0x00078800 0x0 0x1f8>, /* PCS */
- <0x0 0x00078600 0x0 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "gcc_usb0_pipe_clk_src";
- };
- };
- qusb_phy_0: qusb@79000 {
- compatible = "qcom,ipq6018-qusb2-phy";
- reg = <0x0 0x00079000 0x0 0x180>;
- #phy-cells = <0>;
+ phys = <&pcie_phy0>;
+ phy-names = "pciephy";
- clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "cfg_ahb", "ref";
+ ranges = <0x81000000 0 0x20200000 0 0x20200000
+ 0 0x10000>, /* downstream I/O */
+ <0x82000000 0 0x20220000 0 0x20220000
+ 0 0xfde0000>; /* non-prefetchable memory */
- resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
- status = "disabled";
- };
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
- usb3: usb@8af8800 {
- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
- reg = <0x0 0x8af8800 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
- clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
- <&gcc GCC_USB0_MASTER_CLK>,
- <&gcc GCC_USB0_SLEEP_CLK>,
- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
- clock-names = "cfg_noc",
- "core",
- "sleep",
- "mock_utmi";
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+ <&gcc PCIE0_RCHNG_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
- assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
- <&gcc GCC_USB0_MASTER_CLK>,
- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
- assigned-clock-rates = <133330000>,
- <133330000>,
- <24000000>;
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky",
+ "axi_s_sticky";
- resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
-
- dwc_0: usb@8a00000 {
- compatible = "snps,dwc3";
- reg = <0x0 0x8a00000 0x0 0xcd00>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_0>, <&usb0_ssphy>;
- phy-names = "usb2-phy", "usb3-phy";
- clocks = <&xo>;
- clock-names = "ref";
- tx-fifo-resize;
- snps,is-utmi-l1-suspend;
- snps,hird-threshold = /bits/ 8 <0x0>;
- snps,dis_u2_susphy_quirk;
- snps,dis_u3_susphy_quirk;
- dr_mode = "host";
- };
};
};
@@ -792,26 +816,4 @@
#interrupt-cells = <2>;
};
};
-
- rpm-glink {
- compatible = "qcom,glink-rpm";
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&apcs_glb 0>;
-
- rpm_requests: glink-channel {
- compatible = "qcom,rpm-ipq6018";
- qcom,glink-channels = "rpm_requests";
-
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq6018_s2: s2 {
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1062500>;
- regulator-always-on;
- };
- };
- };
- };
};

92
target/linux/qualcommax/patches-6.1/0035-v6.3-arm64-dts-qcom-ipq6018-Add-remove-some-newlines.patch Normal file
View File

@ -0,0 +1,92 @@
From 6db9ed9a128cbae1423d043f3debd8bfa77783fd Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 2 Jan 2023 10:46:29 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: Add/remove some newlines
Some lines were broken very aggresively, presumably to fit under 80 chars
and some places could have used a newline, particularly between subsequent
nodes. Address all that and remove redundant comments near PCIe ranges
while at it so as not to exceed 100 chars needlessly.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++--------------
1 file changed, 12 insertions(+), 14 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -102,26 +102,31 @@
opp-microvolt = <725000>;
clock-latency-ns = <200000>;
};
+
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <787500>;
clock-latency-ns = <200000>;
};
+
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt = <862500>;
clock-latency-ns = <200000>;
};
+
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
opp-microvolt = <925000>;
clock-latency-ns = <200000>;
};
+
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <987500>;
clock-latency-ns = <200000>;
};
+
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1062500>;
@@ -131,8 +136,7 @@
pmuv8: pmu {
compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci: psci {
@@ -734,24 +738,18 @@
phys = <&pcie_phy0>;
phy-names = "pciephy";
- ranges = <0x81000000 0 0x20200000 0 0x20200000
- 0 0x10000>, /* downstream I/O */
- <0x82000000 0 0x20220000 0 0x20220000
- 0 0xfde0000>; /* non-prefetchable memory */
+ ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
+ <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 75
- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 78
- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 79
- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 83
- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
<&gcc GCC_PCIE0_AXI_M_CLK>,

25
target/linux/qualcommax/patches-6.1/0036-v6.3-arm64-dts-qcom-ipq6018-Use-lowercase-hex.patch Normal file
View File

@ -0,0 +1,25 @@
From 7356ae3e10abd1d71f06ff0b8a8e72aa7c955c57 Mon Sep 17 00:00:00 2001
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 2 Jan 2023 10:46:30 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: Use lowercase hex
One value escaped my previous lowercase hexification. Take care of it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-6-konrad.dybcio@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -381,7 +381,7 @@
usb2: usb@70f8800 {
compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
- reg = <0x0 0x070F8800 0x0 0x400>;
+ reg = <0x0 0x070f8800 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges;

28
target/linux/qualcommax/patches-6.1/0037-v6.3-arm64-dts-qcom-ipq6018-align-RPM-G-Link-node-with.patch Normal file
View File

@ -0,0 +1,28 @@
From 679ee73bbee28cab441008f8cca38160cc8f3d05 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 8 Feb 2023 11:15:39 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018: align RPM G-Link node with
bindings
Bindings expect (and most of DTS use) the RPM G-Link node name to be
"rpm-requests".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230208101545.45711-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -176,7 +176,7 @@
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
- rpm_requests: glink-channel {
+ rpm_requests: rpm-requests {
compatible = "qcom,rpm-ipq6018";
qcom,glink-channels = "rpm_requests";

27
target/linux/qualcommax/patches-6.1/0038-v6.4-arm64-dts-qcom-ipq6018-cp01-c1-drop-SPI-cs-select.patch Normal file
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@ -0,0 +1,27 @@
From afa8eb675fc6dd606783ed2350de90927d6fb9d3 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 8 Mar 2023 13:59:01 +0100
Subject: [PATCH] arm64: dts: qcom: ipq6018-cp01-c1: drop SPI cs-select
The SPI controller nodes do not use/allow cs-select property:
ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-6-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -36,7 +36,6 @@
};
&blsp1_spi1 {
- cs-select = <0>;
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";

92
target/linux/qualcommax/patches-6.1/0039-v6.5-arm64-dts-qcom-add-few-more-reserved-memory-region.patch Normal file
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@ -0,0 +1,92 @@
From 0cd4e90cb2dec02ff859f5c98f744f43a23aea65 Mon Sep 17 00:00:00 2001
From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Date: Fri, 26 May 2023 16:36:53 +0530
Subject: [PATCH] arm64: dts: qcom: add few more reserved memory region
In IPQ SoCs, bootloader will collect the system RAM contents upon crash
for the post morterm analysis. If we don't reserve the memory region used
by bootloader, obviously linux will consume it and upon next boot on
crash, bootloader will be loaded in the same region, which will lead to
loose some of the data, sometimes we may miss out critical information.
So lets reserve the region used by the bootloader.
Similarly SBL copies some data into the reserved region and it will be
used in the crash scenario. So reserve 1MB for SBL as well.
While at it, drop the size padding in the reserved memory region,
wherever applicable.
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526110653.27777-4-quic_viswanat@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++--
2 files changed, 25 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -154,18 +154,28 @@
no-map;
};
+ bootloader@4a100000 {
+ reg = <0x0 0x4a100000 0x0 0x400000>;
+ no-map;
+ };
+
+ sbl@4a500000 {
+ reg = <0x0 0x4a500000 0x0 0x100000>;
+ no-map;
+ };
+
tz: memory@4a600000 {
- reg = <0x0 0x4a600000 0x0 0x00400000>;
+ reg = <0x0 0x4a600000 0x0 0x400000>;
no-map;
};
smem_region: memory@4aa00000 {
- reg = <0x0 0x4aa00000 0x0 0x00100000>;
+ reg = <0x0 0x4aa00000 0x0 0x100000>;
no-map;
};
q6_region: memory@4ab00000 {
- reg = <0x0 0x4ab00000 0x0 0x05500000>;
+ reg = <0x0 0x4ab00000 0x0 0x5500000>;
no-map;
};
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -85,17 +85,27 @@
#size-cells = <2>;
ranges;
+ bootloader@4a600000 {
+ reg = <0x0 0x4a600000 0x0 0x400000>;
+ no-map;
+ };
+
+ sbl@4aa00000 {
+ reg = <0x0 0x4aa00000 0x0 0x100000>;
+ no-map;
+ };
+
smem@4ab00000 {
compatible = "qcom,smem";
- reg = <0x0 0x4ab00000 0x0 0x00100000>;
+ reg = <0x0 0x4ab00000 0x0 0x100000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
memory@4ac00000 {
+ reg = <0x0 0x4ac00000 0x0 0x400000>;
no-map;
- reg = <0x0 0x4ac00000 0x0 0x00400000>;
};
};

49
target/linux/qualcommax/patches-6.1/0040-v6.5-arm64-dts-qcom-enable-the-download-mode-support.patch Normal file
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@ -0,0 +1,49 @@
From 9b2406aaba7841863ac041225316c1ec1c86ea36 Mon Sep 17 00:00:00 2001
From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Date: Fri, 26 May 2023 16:36:52 +0530
Subject: [PATCH] arm64: dts: qcom: enable the download mode support
Like any other Qualcomm SoCs, IPQ8074 and IPQ6018 also supports the
download mode to collect the RAM dumps if system crashes, to perform
the post mortem analysis. Add support for the same.
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526110653.27777-3-quic_viswanat@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++
2 files changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -90,6 +90,7 @@
firmware {
scm {
compatible = "qcom,scm-ipq6018", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x6100>;
};
};
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -112,6 +112,7 @@
firmware {
scm {
compatible = "qcom,scm-ipq8074", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x6100>;
};
};
@@ -386,6 +387,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1937000 {
+ compatible = "qcom,tcsr-ipq8074", "syscon";
+ reg = <0x01937000 0x21000>;
+ };
+
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,

29
target/linux/qualcommax/patches-6.1/0041-v6.5-arm64-dts-qcom-ipq6018-correct-qrng-unit-address.patch Normal file
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@ -0,0 +1,29 @@
From 085058786a7890dd44ec623fe5ac74db870f6b93 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Wed, 19 Apr 2023 23:18:39 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: correct qrng unit address
Match unit-address to reg entry to fix dtbs W=1 warnings:
Warning (simple_bus_reg): /soc/qrng@e1000: simple-bus unit address format error, expected "e3000"
Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230419211856.79332-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -312,7 +312,7 @@
status = "disabled";
};
- prng: qrng@e1000 {
+ prng: qrng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x0 0x000e3000 0x0 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;

28
target/linux/qualcommax/patches-6.1/0042-v6.5-arm64-dts-qcom-ipq6018-add-unit-address-to-soc-node.patch Normal file
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@ -0,0 +1,28 @@
From 393595d4ffbd0a1fafd5548f8de1b8487a037cf2 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Thu, 20 Apr 2023 08:36:04 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: add unit address to soc node
"soc" node is supposed to have unit address:
Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230420063610.11068-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -209,7 +209,7 @@
hwlocks = <&tcsr_mutex 3>;
};
- soc: soc {
+ soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x0 0xffffffff>;

34
target/linux/qualcommax/patches-6.1/0043-v6.5-arm64-dts-qcom-ipq6018-add-QFPROM-node.patch Normal file
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@ -0,0 +1,34 @@
From 546f0617a22a481f3ca1f7e058aea0c40517c64e Mon Sep 17 00:00:00 2001
From: Kathiravan T <quic_kathirav@quicinc.com>
Date: Fri, 26 May 2023 18:23:04 +0530
Subject: [PATCH] arm64: dts: qcom: ipq6018: add QFPROM node
IPQ6018 has efuse region to determine the various HW quirks. Lets
add the initial support and the individual fuses will be added as they
are required.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526125305.19626-4-quic_kathirav@quicinc.com
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -312,6 +312,13 @@
status = "disabled";
};
+ qfprom: efuse@a4000 {
+ compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
+ reg = <0x0 0x000a4000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
prng: qrng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x0 0x000e3000 0x0 0x1000>;

37
target/linux/qualcommax/patches-6.1/0044-v6.5-arm64-dts-qcom-ipq6018-drop-incorrect-SPI-bus.patch Normal file
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@ -0,0 +1,37 @@
From b8420d478aa3fc739fcdba6b4b945850b356cb3b Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Sun, 16 Apr 2023 14:37:25 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: drop incorrect SPI bus
spi-max-frequency
The spi-max-frequency property belongs to SPI devices, not SPI
controller:
ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-1-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 --
1 file changed, 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -458,7 +458,6 @@
#size-cells = <0>;
reg = <0x0 0x078b5000 0x0 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
@@ -473,7 +472,6 @@
#size-cells = <0>;
reg = <0x0 0x078b6000 0x0 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";

29
target/linux/qualcommax/patches-6.1/0045-v6.5-arm64-dts-qcom-ipq8074-drop-incorrect-SPI-bus.patch Normal file
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@ -0,0 +1,29 @@
From e6e0e706940b64e3a77e0a4840037692f109bd5f Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Sun, 16 Apr 2023 14:37:26 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: drop incorrect SPI bus
spi-max-frequency
The spi-max-frequency property belongs to SPI devices, not SPI
controller:
ipq8074-hk01.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416123730.300863-2-krzysztof.kozlowski@linaro.org
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 -
1 file changed, 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -487,7 +487,6 @@
#size-cells = <0>;
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";

27
target/linux/qualcommax/patches-6.1/0046-v6.6-clk-qcom-gcc-ipq6018-Use-floor-ops-for-sdcc-clocks.patch Normal file
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@ -0,0 +1,27 @@
From 56e5ae0116aef87273cf1812d608645b076e4f02 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 25 Apr 2023 12:11:49 +0300
Subject: [PATCH] clk: qcom: gcc-ipq6018: Use floor ops for sdcc clocks
SDCC clocks must be rounded down to avoid overclocking the controller.
Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1682413909-24927-1-git-send-email-mantas@8devices.com
---
drivers/clk/qcom/gcc-ipq6018.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -1702,7 +1702,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
.name = "usb0_mock_utmi_clk_src",
.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
.num_parents = 4,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};

27
target/linux/qualcommax/patches-6.1/0047-v6.6-clk-qcom-gcc-ipq6018-drop-redundant-F-define.patch Normal file
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@ -0,0 +1,27 @@
From 923f7d678b2ae3d522543058514d5605c185633b Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 17 Apr 2023 19:44:07 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: drop redundant F define
The same exact F frequency table entry is defined in clk-rcg.h
Drop the redundant define to cleanup code.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230417174408.23722-1-ansuelsmth@gmail.com
---
drivers/clk/qcom/gcc-ipq6018.c | 2 --
1 file changed, 2 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -26,8 +26,6 @@
#include "clk-regmap-mux.h"
#include "reset.h"
-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
enum {
P_XO,
P_BIAS_PLL,

39
target/linux/qualcommax/patches-6.1/0048-v6.6-clk-qcom-gcc-ipq6018-update-UBI32-PLL.patch Normal file
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@ -0,0 +1,39 @@
From f4f0c8acee0e41c5fbae7a7ad06087668ddce0d6 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 26 May 2023 21:08:54 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: update UBI32 PLL
Update the UBI32 alpha PLL config to the latest values from the downstream
QCA 5.4 kernel.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526190855.2941291-1-robimarko@gmail.com
---
drivers/clk/qcom/gcc-ipq6018.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -4143,15 +4143,20 @@ static struct clk_branch gcc_dcc_clk = {
static const struct alpha_pll_config ubi32_pll_config = {
.l = 0x3e,
- .alpha = 0x57,
+ .alpha = 0x6667,
.config_ctl_val = 0x240d6aa8,
.config_ctl_hi_val = 0x3c2,
+ .config_ctl_val = 0x240d4828,
+ .config_ctl_hi_val = 0x6,
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.pre_div_val = 0x0,
.pre_div_mask = BIT(12),
.post_div_val = 0x0,
.post_div_mask = GENMASK(9, 8),
+ .alpha_en_mask = BIT(24),
+ .test_ctl_val = 0x1C0000C0,
+ .test_ctl_hi_val = 0x4000,
};
static const struct alpha_pll_config nss_crypto_pll_config = {

38
target/linux/qualcommax/patches-6.1/0049-v6.6-clk-qcom-gcc-ipq6018-remove-duplicate-initializers.patch Normal file
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@ -0,0 +1,38 @@
From 5ae7899765607e97e5eb34486336898c8d9ec654 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Thu, 1 Jun 2023 23:34:12 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: remove duplicate initializers
A recent change added new initializers for .config_ctl_val and
.config_ctl_hi_val but left the old values in place:
drivers/clk/qcom/gcc-ipq6018.c:4155:27: error: initialized field overwritten [-Werror=override-init]
4155 | .config_ctl_val = 0x240d4828,
| ^~~~~~~~~~
drivers/clk/qcom/gcc-ipq6018.c:4156:30: error: initialized field overwritten [-Werror=override-init]
4156 | .config_ctl_hi_val = 0x6,
| ^~~
Remove the unused ones now to avoid confusion.
Fixes: f4f0c8acee0e4 ("clk: qcom: gcc-ipq6018: update UBI32 PLL")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230601213416.3373599-1-arnd@kernel.org
---
drivers/clk/qcom/gcc-ipq6018.c | 2 --
1 file changed, 2 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -4144,8 +4144,6 @@ static struct clk_branch gcc_dcc_clk = {
static const struct alpha_pll_config ubi32_pll_config = {
.l = 0x3e,
.alpha = 0x6667,
- .config_ctl_val = 0x240d6aa8,
- .config_ctl_hi_val = 0x3c2,
.config_ctl_val = 0x240d4828,
.config_ctl_hi_val = 0x6,
.main_output_mask = BIT(0),

132
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@ -0,0 +1,132 @@
From 8ddfa81d090c71fd6cb3cb8ca1d420c0da33a575 Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan@gerhold.net>
Date: Thu, 15 Jun 2023 18:50:42 +0200
Subject: [PATCH] soc: qcom: Add RPM processor/subsystem driver
Add a simple driver for the qcom,rpm-proc compatible that registers the
"smd-edge" and populates other children defined in the device tree.
Note that the DT schema belongs to the remoteproc subsystem while this
driver is added inside soc/qcom. I argue that the RPM *is* a remoteproc,
but as an implementation detail in Linux it can currently not benefit
from anything provided by the remoteproc subsystem. The RPM firmware is
usually already loaded and started by earlier components in the boot
chain and is not meant to be ever restarted.
To avoid breaking existing kernel configurations the driver is always
built when smd-rpm.c is also built. They belong closely together anyway.
To avoid build errors CONFIG_RPMSG_QCOM_SMD must be also built-in if
rpm-proc is.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-9-a07dcdefd918@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/soc/qcom/Kconfig | 1 +
drivers/soc/qcom/Makefile | 2 +-
drivers/soc/qcom/rpm-proc.c | 77 +++++++++++++++++++++++++++++++++++++
3 files changed, 79 insertions(+), 1 deletion(-)
create mode 100644 drivers/soc/qcom/rpm-proc.c
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -153,6 +153,7 @@ config QCOM_SMD_RPM
tristate "Qualcomm Resource Power Manager (RPM) over SMD"
depends on ARCH_QCOM || COMPILE_TEST
depends on RPMSG
+ depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
help
If you say yes to this option, support will be included for the
Resource Power Manager system found in the Qualcomm 8974 based
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_me
obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o
qcom_rpmh-y += rpmh-rsc.o
qcom_rpmh-y += rpmh.o
-obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o
+obj-$(CONFIG_QCOM_SMD_RPM) += rpm-proc.o smd-rpm.o
obj-$(CONFIG_QCOM_SMEM) += smem.o
obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o
obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
--- /dev/null
+++ b/drivers/soc/qcom/rpm-proc.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/rpmsg/qcom_smd.h>
+
+static int rpm_proc_probe(struct platform_device *pdev)
+{
+ struct qcom_smd_edge *edge = NULL;
+ struct device *dev = &pdev->dev;
+ struct device_node *edge_node;
+ int ret;
+
+ edge_node = of_get_child_by_name(dev->of_node, "smd-edge");
+ if (edge_node) {
+ edge = qcom_smd_register_edge(dev, edge_node);
+ of_node_put(edge_node);
+ if (IS_ERR(edge))
+ return dev_err_probe(dev, PTR_ERR(edge),
+ "Failed to register smd-edge\n");
+ }
+
+ ret = devm_of_platform_populate(dev);
+ if (ret) {
+ dev_err(dev, "Failed to populate child devices: %d\n", ret);
+ goto err;
+ }
+
+ platform_set_drvdata(pdev, edge);
+ return 0;
+err:
+ if (edge)
+ qcom_smd_unregister_edge(edge);
+ return ret;
+}
+
+static void rpm_proc_remove(struct platform_device *pdev)
+{
+ struct qcom_smd_edge *edge = platform_get_drvdata(pdev);
+
+ if (edge)
+ qcom_smd_unregister_edge(edge);
+}
+
+static const struct of_device_id rpm_proc_of_match[] = {
+ { .compatible = "qcom,rpm-proc", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rpm_proc_of_match);
+
+static struct platform_driver rpm_proc_driver = {
+ .probe = rpm_proc_probe,
+ .remove_new = rpm_proc_remove,
+ .driver = {
+ .name = "qcom-rpm-proc",
+ .of_match_table = rpm_proc_of_match,
+ },
+};
+
+static int __init rpm_proc_init(void)
+{
+ return platform_driver_register(&rpm_proc_driver);
+}
+arch_initcall(rpm_proc_init);
+
+static void __exit rpm_proc_exit(void)
+{
+ platform_driver_unregister(&rpm_proc_driver);
+}
+module_exit(rpm_proc_exit);
+
+MODULE_DESCRIPTION("Qualcomm RPM processor/subsystem driver");
+MODULE_AUTHOR("Stephan Gerhold <stephan@gerhold.net>");
+MODULE_LICENSE("GPL");

93
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From 7e1acc8b92a3b67db1e5255adae2851d58d74434 Mon Sep 17 00:00:00 2001
From: Stephan Gerhold <stephan@gerhold.net>
Date: Thu, 15 Jun 2023 18:50:44 +0200
Subject: [PATCH] arm64: dts: qcom: Add rpm-proc node for GLINK gplatforms
Rather than having the RPM GLINK channels as the only child of a dummy
top-level rpm-glink node, switch to representing the RPM as remoteproc
like all the other remoteprocs (modem DSP, ...).
This allows assigning additional subdevices to it like the MPM
interrupt-controller or rpm-master-stats.
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM6375
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-11-a07dcdefd918@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 ++++----
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 +++--
arch/arm64/boot/dts/qcom/msm8996.dtsi | 113 +++++++++----------
arch/arm64/boot/dts/qcom/msm8998.dtsi | 102 ++++++++---------
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 126 ++++++++++-----------
arch/arm64/boot/dts/qcom/qcs404.dtsi | 152 +++++++++++++-------------
arch/arm64/boot/dts/qcom/sdm630.dtsi | 132 +++++++++++-----------
arch/arm64/boot/dts/qcom/sm6115.dtsi | 128 +++++++++++-----------
arch/arm64/boot/dts/qcom/sm6125.dtsi | 140 ++++++++++++------------
arch/arm64/boot/dts/qcom/sm6375.dtsi | 126 ++++++++++-----------
10 files changed, 566 insertions(+), 529 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -145,6 +145,32 @@
method = "smc";
};
+ rpm: remoteproc {
+ compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
+
+ glink-edge {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-ipq6018";
+ qcom,glink-channels = "rpm_requests";
+
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq6018_s2: s2 {
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1062500>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -181,28 +207,6 @@
};
};
- rpm-glink {
- compatible = "qcom,glink-rpm";
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&apcs_glb 0>;
-
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-ipq6018";
- qcom,glink-channels = "rpm_requests";
-
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq6018_s2: s2 {
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1062500>;
- regulator-always-on;
- };
- };
- };
- };
-
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;

35
target/linux/qualcommax/patches-6.1/0052-v6.7-arm64-dts-qcom-ipq6018-include-the-GPLL0-as.patch Normal file
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@ -0,0 +1,35 @@
From 0133c7af3aa0420778d106cb90db708cfa45f2c6 Mon Sep 17 00:00:00 2001
From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Date: Thu, 14 Sep 2023 12:29:59 +0530
Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock
provider for mailbox
While the kernel is booting up, APSS clock / CPU clock will be running
at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
APSS PLL will be configured to the rate based on the opp table and the
source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
consume the GPLL0, with this inclusion, CPU Freq correctly reports that
CPU is running at 800MHz rather than 24MHz.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com
[bjorn: Updated commit message, as requested by Kathiravan]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -618,8 +618,8 @@
compatible = "qcom,ipq6018-apcs-apps-global";
reg = <0x0 0x0b111000 0x0 0x1000>;
#clock-cells = <1>;
- clocks = <&a53pll>, <&xo>;
- clock-names = "pll", "xo";
+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
#mbox-cells = <1>;
};

57
target/linux/qualcommax/patches-6.1/0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch Normal file
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@ -0,0 +1,57 @@
From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sat, 21 Oct 2023 13:55:18 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock
QUP6 I2C clock is listed in the dt bindings but it was never included in
the GCC driver.
So lets add support for it, it is marked as criticial as it is used by RPM
to communicate to the external PMIC over I2C so this clock must not be
disabled.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -2120,6 +2120,26 @@ static struct clk_branch gcc_blsp1_qup5_
},
};
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+ .halt_reg = 0x07010,
+ .clkr = {
+ .enable_reg = 0x07010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup6_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
+ .num_parents = 1,
+ /*
+ * RPM uses QUP6 I2C to communicate with the external
+ * PMIC so it must not be disabled.
+ */
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
.halt_reg = 0x0700c,
.clkr = {
@@ -4276,6 +4296,7 @@ static struct clk_regmap *gcc_ipq6018_cl
[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,

85
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@ -0,0 +1,85 @@
From 83afcf14edb9217e58837eb119da96d734a4b3b1 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sat, 21 Oct 2023 14:00:07 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM
IPQ6018 comes in multiple SKU-s and some of them dont support all of the
OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
supported OPP-s based on the SoC dynamically.
As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
goes up to 1.5GHz and is marked as such via an eFuse.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231021120048.231239-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -95,42 +95,49 @@
};
cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&cpu_speed_bin>;
opp-shared;
opp-864000000 {
opp-hz = /bits/ 64 <864000000>;
opp-microvolt = <725000>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <787500>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt = <862500>;
+ opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
opp-microvolt = <925000>;
+ opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <987500>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1062500>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
};
@@ -321,6 +328,11 @@
reg = <0x0 0x000a4000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ cpu_speed_bin: cpu-speed-bin@135 {
+ reg = <0x135 0x1>;
+ bits = <7 1>;
+ };
};
prng: qrng@e3000 {

81
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@ -0,0 +1,81 @@
From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Sun, 3 Dec 2023 23:39:14 +0800
Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node
Add node to support all the QUP UART node controller inside of IPQ6018.
Some routers use these bus to connect Bluetooth chips.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -458,6 +458,26 @@
qcom,ee = <0>;
};
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x78af000 0x0 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart2: serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x78b0000 0x0 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
blsp1_uart3: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0 0x078b1000 0x0 0x200>;
@@ -466,6 +486,36 @@
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
+ };
+
+ blsp1_uart4: serial@78b2000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x078b2000 0x0 0x200>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart5: serial@78b3000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x78b3000 0x0 0x200>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart6: serial@78b4000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x078b4000 0x0 0x200>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
};
blsp1_spi1: spi@78b5000 {

95
target/linux/qualcommax/patches-6.1/0056-v6.9-arm64-dts-qcom-Fix-hs_phy_irq-for-QUSB2-targets.patch Normal file
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@ -0,0 +1,95 @@
From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001
From: Krishna Kurapati <quic_kriskura@quicinc.com>
Date: Fri, 26 Jan 2024 00:29:18 +0530
Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
On several QUSB2 Targets, the hs_phy_irq mentioned is actually
qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
to qusb2_phy for such targets.
In actuality, the hs_phy_irq is also present in these targets, but
kept in for debug purposes in hw test environments. This is not
triggered by default and its functionality is mutually exclusive
to that of qusb2_phy interrupt.
Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
Add missing ss_phy_irq on some targets which allows for remote
wakeup to work on a Super Speed link.
Also modify order of interrupts in accordance to bindings update.
Since driver looks up for interrupts by name and not by index, it
is safe to modify order of these interrupts in the DT.
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++--
arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++++--
arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++--
arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 +++++++++++++----
arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++--
arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++--
8 files changed, 70 insertions(+), 14 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -430,6 +430,12 @@
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<24000000>;
+
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy";
+
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
@@ -628,6 +634,13 @@
<133330000>,
<24000000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -611,6 +611,13 @@
<133330000>,
<19200000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
power-domains = <&gcc USB0_GDSC>;
resets = <&gcc GCC_USB0_BCR>;
@@ -653,6 +660,13 @@
<133330000>,
<19200000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
power-domains = <&gcc USB1_GDSC>;
resets = <&gcc GCC_USB1_BCR>;

32
target/linux/qualcommax/patches-6.1/0057-v6.8-hwspinlock-qcom-Remove-IPQ6018-SOC-specific-.patch Normal file
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@ -0,0 +1,32 @@
From c3dc3d079d191c9149496b3c7fe1ece909386d93 Mon Sep 17 00:00:00 2001
From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Date: Tue, 5 Sep 2023 15:25:35 +0530
Subject: [PATCH] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible
IPQ6018 has 32 tcsr_mutex hwlock registers with stride 0x1000.
The compatible string qcom,ipq6018-tcsr-mutex is mapped to
of_msm8226_tcsr_mutex which has 32 locks configured with stride of 0x80
and doesn't match the HW present in IPQ6018.
Remove IPQ6018 specific compatible string so that it fallsback to
of_tcsr_mutex data which maps to the correct configuration for IPQ6018.
Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs")
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230905095535.1263113-3-quic_viswanat@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/hwspinlock/qcom_hwspinlock.c | 1 -
1 file changed, 1 deletion(-)
--- a/drivers/hwspinlock/qcom_hwspinlock.c
+++ b/drivers/hwspinlock/qcom_hwspinlock.c
@@ -115,7 +115,6 @@ static const struct of_device_id qcom_hw
{ .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex },
{ .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
{ .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
- { .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
{ .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
{ .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
{ .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },

34
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@ -0,0 +1,34 @@
From 0b17197055b528da22e9385200e61b847b499d48 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Thu, 25 Jan 2024 11:04:11 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: add tsens node
IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add
node for it.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Link: https://lore.kernel.org/r/1706173452-1017-3-git-send-email-mantas@8devices.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -342,6 +342,16 @@
clock-names = "core";
};
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens";
+ reg = <0x0 0x004a9000 0x0 0x1000>,
+ <0x0 0x004a8000 0x0 0x1000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "combined";
+ #qcom,sensors = <16>;
+ #thermal-sensor-cells = <1>;
+ };
+
cryptobam: dma-controller@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x00704000 0x0 0x20000>;

180
target/linux/qualcommax/patches-6.1/0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch Normal file
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@ -0,0 +1,180 @@
From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Thu, 25 Jan 2024 11:04:12 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones
Add thermal zones to make use of thermal sensors data. For CPU zone,
add cooling device that uses CPU frequency scaling.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
#address-cells = <2>;
@@ -43,6 +44,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
+ #cooling-cells = <2>;
};
CPU1: cpu@1 {
@@ -55,6 +57,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
+ #cooling-cells = <2>;
};
CPU2: cpu@2 {
@@ -67,6 +70,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
+ #cooling-cells = <2>;
};
CPU3: cpu@3 {
@@ -79,6 +83,7 @@
clock-names = "cpu";
operating-points-v2 = <&cpu_opp_table>;
cpu-supply = <&ipq6018_s2>;
+ #cooling-cells = <2>;
};
L2_0: l2-cache {
@@ -888,6 +893,122 @@
};
};
+ thermal-zones {
+ nss-top-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 4>;
+
+ trips {
+ nss-top-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nss-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 5>;
+
+ trips {
+ nss-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ wcss-phya0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 7>;
+
+ trips {
+ wcss-phya0-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ wcss-phya1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 8>;
+
+ trips {
+ wcss-phya1-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 13>;
+
+ trips {
+ cpu-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+
+ cpu_alert: cpu-passive {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ lpass-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 14>;
+
+ trips {
+ lpass-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddrss-top-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsens 15>;
+
+ trips {
+ ddrss-top-critical {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

50
target/linux/qualcommax/patches-6.1/0060-v6.9-clk-qcom-gcc-ipq6018-add-qdss_at-clock-needed-for-wi.patch Normal file
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@ -0,0 +1,50 @@
From fd712118aa1aa758da1fd1546b3f8a1b00e42cbc Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 23 Jan 2024 11:26:09 +0200
Subject: [PATCH] clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi
operation
Without it system hangs upon wifi firmware load. It should be enabled by
remoteproc/wifi driver. Bindings already exist for it, so add it based
on vendor code.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Link: https://lore.kernel.org/r/1706001970-26032-1-git-send-email-mantas@8devices.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
drivers/clk/qcom/gcc-ipq6018.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -3523,6 +3523,22 @@ static struct clk_branch gcc_prng_ahb_cl
},
};
+static struct clk_branch gcc_qdss_at_clk = {
+ .halt_reg = 0x29024,
+ .clkr = {
+ .enable_reg = 0x29024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qdss_at_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &qdss_at_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_qdss_dap_clk = {
.halt_reg = 0x29084,
.clkr = {
@@ -4362,6 +4378,7 @@ static struct clk_regmap *gcc_ipq6018_cl
[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,

102
target/linux/qualcommax/patches-6.1/0061-v6.8-phy-qcom-qmp-usb-fix-serdes-init-sequence-for-IPQ6018.patch Normal file
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@ -0,0 +1,102 @@
From 62a5df451ab911421da96655fcc4d1e269ff6e2f Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 23 Jan 2024 18:09:20 +0200
Subject: [PATCH] phy: qcom-qmp-usb: fix serdes init sequence for IPQ6018
Commit 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
noted that IPQ6018 init is identical to IPQ8074. Yet downstream uses
separate serdes init sequence for IPQ6018. Since already existing IPQ9574
serdes init sequence is identical, just reuse it and fix failing USB3 mode
in IPQ6018.
Fixes: 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1706026160-17520-3-git-send-email-mantas@8devices.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -233,6 +233,43 @@ static const struct qmp_phy_init_tbl ipq
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
};
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+ /* PLL and Loop filter settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+ /* SSC settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
@@ -1591,6 +1628,26 @@ static const char * const qmp_phy_vreg_l
"vdda-phy", "vdda-pll",
};
+static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
+ .lanes = 1,
+
+ .serdes_tbl = ipq9574_usb3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
+ .tx_tbl = msm8996_usb3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
+ .rx_tbl = ipq8074_usb3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
+ .clk_list = msm8996_phy_clk_l,
+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
+ .reset_list = msm8996_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = qmp_v3_usb3phy_regs_layout,
+};
+
static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
.lanes = 1,
@@ -2534,7 +2591,7 @@ static const struct of_device_id qmp_usb
.data = &msm8996_usb3phy_cfg,
}, {
.compatible = "qcom,ipq6018-qmp-usb3-phy",
- .data = &ipq8074_usb3phy_cfg,
+ .data = &ipq6018_usb3phy_cfg,
}, {
.compatible = "qcom,sc7180-qmp-usb3-phy",
.data = &sc7180_usb3phy_cfg,

38
target/linux/qualcommax/patches-6.1/0062-v6.8-arm64-dts-qcom-ipq8074-Add-QUP4-SPI-node.patch Normal file
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@ -0,0 +1,38 @@
From 6a25e70214fde6dcf900271c819c8d7fe7b9a4b0 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 23 Nov 2023 13:12:54 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP4 SPI node
Add node to support the QUP4 SPI controller inside of IPQ8074.
Some devices use this bus to communicate to a Bluetooth controller.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20231123121324.1046164-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -529,6 +529,20 @@
status = "disabled";
};
+ blsp1_spi4: spi@78b8000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b8000 0x600>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 18>, <&blsp_dma 19>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
blsp1_i2c5: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;

203
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@ -0,0 +1,203 @@
From 032be4f49dda786fea9e1501212f6cd09a7ded96 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 3 Nov 2022 14:49:43 +0100
Subject: [PATCH] clk: qcom: clk-rcg2: introduce support for multiple conf for
same freq
Some RCG frequency can be reached by multiple configuration.
We currently declare multiple configuration for the same frequency but
that is not supported and always the first configuration will be taken.
These multiple configuration are needed as based on the current parent
configuration, it may be needed to use a different configuration to
reach the same frequency.
To handle this introduce 2 new macro, FM and C.
- FM is used to declare an empty freq_tbl with just the frequency and an
array of confs to insert all the config for the provided frequency.
- C is used to declare a fre_conf where src, pre_div, m and n are
provided.
The driver is changed to handle this special freq_tbl and select the
correct config by calculating the final rate and deciding based on the
one that is less different than the requested one.
Tested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/qcom/clk-rcg.h | 14 ++++++-
drivers/clk/qcom/clk-rcg2.c | 84 +++++++++++++++++++++++++++++++++----
2 files changed, 88 insertions(+), 10 deletions(-)
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -7,7 +7,17 @@
#include <linux/clk-provider.h>
#include "clk-regmap.h"
-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n), 0, NULL }
+
+#define FM(_f, _confs) { .freq = (_f), .confs_num = ARRAY_SIZE(_confs), .confs = (_confs) }
+#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) }
+
+struct freq_conf {
+ u8 src;
+ u8 pre_div;
+ u16 m;
+ u16 n;
+};
struct freq_tbl {
unsigned long freq;
@@ -15,6 +25,8 @@ struct freq_tbl {
u8 pre_div;
u16 m;
u16 n;
+ int confs_num;
+ const struct freq_conf *confs;
};
/**
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -203,11 +203,60 @@ clk_rcg2_recalc_rate(struct clk_hw *hw,
return __clk_rcg2_recalc_rate(hw, parent_rate, cfg);
}
+static void
+clk_rcg2_select_conf(struct clk_hw *hw, struct freq_tbl *f_tbl,
+ const struct freq_tbl *f, unsigned long req_rate)
+{
+ unsigned long best_rate = 0, parent_rate, rate;
+ const struct freq_conf *conf, *best_conf;
+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+ struct clk_hw *p;
+ int index, i;
+
+ /* Search in each provided config the one that is near the wanted rate */
+ for (i = 0, conf = f->confs; i < f->confs_num; i++, conf++) {
+ index = qcom_find_src_index(hw, rcg->parent_map, conf->src);
+ if (index < 0)
+ continue;
+
+ p = clk_hw_get_parent_by_index(hw, index);
+ if (!p)
+ continue;
+
+ parent_rate = clk_hw_get_rate(p);
+ rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
+
+ if (rate == req_rate) {
+ best_conf = conf;
+ break;
+ }
+
+ if (abs(req_rate - rate) < abs(best_rate - rate)) {
+ best_rate = rate;
+ best_conf = conf;
+ }
+ }
+
+ /*
+ * Very unlikely.
+ * Force the first conf if we can't find a correct config.
+ */
+ if (unlikely(i == f->confs_num))
+ best_conf = f->confs;
+
+ /* Apply the config */
+ f_tbl->src = best_conf->src;
+ f_tbl->pre_div = best_conf->pre_div;
+ f_tbl->m = best_conf->m;
+ f_tbl->n = best_conf->n;
+}
+
static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
struct clk_rate_request *req,
enum freq_policy policy)
{
unsigned long clk_flags, rate = req->rate;
+ struct freq_tbl f_tbl;
struct clk_hw *p;
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
int index;
@@ -226,7 +275,15 @@ static int _freq_tbl_determine_rate(stru
if (!f)
return -EINVAL;
- index = qcom_find_src_index(hw, rcg->parent_map, f->src);
+ f_tbl = *f;
+ /*
+ * A single freq may be reached by multiple configuration.
+ * Try to find the bast one if we have this kind of freq_table.
+ */
+ if (f->confs)
+ clk_rcg2_select_conf(hw, &f_tbl, f, rate);
+
+ index = qcom_find_src_index(hw, rcg->parent_map, f_tbl.src);
if (index < 0)
return index;
@@ -236,18 +293,18 @@ static int _freq_tbl_determine_rate(stru
return -EINVAL;
if (clk_flags & CLK_SET_RATE_PARENT) {
- rate = f->freq;
- if (f->pre_div) {
+ rate = f_tbl.freq;
+ if (f_tbl.pre_div) {
if (!rate)
rate = req->rate;
rate /= 2;
- rate *= f->pre_div + 1;
+ rate *= f_tbl.pre_div + 1;
}
- if (f->n) {
+ if (f_tbl.n) {
u64 tmp = rate;
- tmp = tmp * f->n;
- do_div(tmp, f->m);
+ tmp = tmp * f_tbl.n;
+ do_div(tmp, f_tbl.m);
rate = tmp;
}
} else {
@@ -255,7 +312,7 @@ static int _freq_tbl_determine_rate(stru
}
req->best_parent_hw = p;
req->best_parent_rate = rate;
- req->rate = f->freq;
+ req->rate = f_tbl.freq;
return 0;
}
@@ -351,6 +408,7 @@ static int __clk_rcg2_set_rate(struct cl
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const struct freq_tbl *f;
+ struct freq_tbl f_tbl;
switch (policy) {
case FLOOR:
@@ -366,7 +424,15 @@ static int __clk_rcg2_set_rate(struct cl
if (!f)
return -EINVAL;
- return clk_rcg2_configure(rcg, f);
+ f_tbl = *f;
+ /*
+ * A single freq may be reached by multiple configuration.
+ * Try to find the best one if we have this kind of freq_table.
+ */
+ if (f->confs)
+ clk_rcg2_select_conf(hw, &f_tbl, f, rate);
+
+ return clk_rcg2_configure(rcg, &f_tbl);
}
static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,

129
target/linux/qualcommax/patches-6.1/0101-clk-qcom-gcc-ipq8074-rework-nss_port5-6-clock-to-mul.patch Normal file
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@ -0,0 +1,129 @@
From f778553f296792f4d1e8b3552603ad6116ea3eb3 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 3 Nov 2022 14:49:44 +0100
Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
conf
Rework nss_port5/6 to use the new multiple configuration implementation
and correctly fix the clocks for these port under some corner case.
This is particularly relevant for device that have 2.5G or 10G port
connected to port5 or port 6 on ipq8074. As the parent are shared
across multiple port it may be required to select the correct
configuration to accomplish the desired clock. Without this patch such
port doesn't work in some specific ethernet speed as the clock will be
set to the wrong frequency as we just select the first configuration for
the related frequency instead of selecting the best one.
Tested-by: Robert Marko <robimarko@gmail.com> # ipq8074 Qnap QHora-301W
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq8074.c | 64 +++++++++++++++++++++++++---------
1 file changed, 48 insertions(+), 16 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -1676,13 +1676,21 @@ static struct clk_regmap_div nss_port4_t
},
};
+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
+ C(P_UNIPHY1_RX, 12.5, 0, 0),
+ C(P_UNIPHY0_RX, 5, 0, 0),
+};
+
+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
+ C(P_UNIPHY1_RX, 2.5, 0, 0),
+ C(P_UNIPHY0_RX, 1, 0, 0),
+};
+
static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
- F(25000000, P_UNIPHY0_RX, 5, 0, 0),
+ FM(25000000, ftbl_nss_port5_rx_clk_src_25),
F(78125000, P_UNIPHY1_RX, 4, 0, 0),
- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
- F(125000000, P_UNIPHY0_RX, 1, 0, 0),
+ FM(125000000, ftbl_nss_port5_rx_clk_src_125),
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
{ }
@@ -1738,13 +1746,21 @@ static struct clk_regmap_div nss_port5_r
},
};
+static struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
+ C(P_UNIPHY1_TX, 12.5, 0, 0),
+ C(P_UNIPHY0_TX, 5, 0, 0),
+};
+
+static struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
+ C(P_UNIPHY1_TX, 2.5, 0, 0),
+ C(P_UNIPHY0_TX, 1, 0, 0),
+};
+
static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
- F(25000000, P_UNIPHY0_TX, 5, 0, 0),
+ FM(25000000, ftbl_nss_port5_tx_clk_src_25),
F(78125000, P_UNIPHY1_TX, 4, 0, 0),
- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
- F(125000000, P_UNIPHY0_TX, 1, 0, 0),
+ FM(125000000, ftbl_nss_port5_tx_clk_src_125),
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
{ }
@@ -1800,13 +1816,21 @@ static struct clk_regmap_div nss_port5_t
},
};
+static struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
+ C(P_UNIPHY2_RX, 5, 0, 0),
+ C(P_UNIPHY2_RX, 12.5, 0, 0),
+};
+
+static struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
+ C(P_UNIPHY2_RX, 1, 0, 0),
+ C(P_UNIPHY2_RX, 2.5, 0, 0),
+};
+
static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
- F(25000000, P_UNIPHY2_RX, 5, 0, 0),
- F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
+ FM(25000000, ftbl_nss_port6_rx_clk_src_25),
F(78125000, P_UNIPHY2_RX, 4, 0, 0),
- F(125000000, P_UNIPHY2_RX, 1, 0, 0),
- F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
+ FM(125000000, ftbl_nss_port6_rx_clk_src_125),
F(156250000, P_UNIPHY2_RX, 2, 0, 0),
F(312500000, P_UNIPHY2_RX, 1, 0, 0),
{ }
@@ -1857,13 +1881,21 @@ static struct clk_regmap_div nss_port6_r
},
};
+static struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
+ C(P_UNIPHY2_TX, 5, 0, 0),
+ C(P_UNIPHY2_TX, 12.5, 0, 0),
+};
+
+static struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
+ C(P_UNIPHY2_TX, 1, 0, 0),
+ C(P_UNIPHY2_TX, 2.5, 0, 0),
+};
+
static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
- F(25000000, P_UNIPHY2_TX, 5, 0, 0),
- F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
+ FM(25000000, ftbl_nss_port6_tx_clk_src_25),
F(78125000, P_UNIPHY2_TX, 4, 0, 0),
- F(125000000, P_UNIPHY2_TX, 1, 0, 0),
- F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
+ FM(125000000, ftbl_nss_port6_tx_clk_src_125),
F(156250000, P_UNIPHY2_TX, 2, 0, 0),
F(312500000, P_UNIPHY2_TX, 1, 0, 0),
{ }

60
target/linux/qualcommax/patches-6.1/0102-arm64-dts-ipq8074-add-reserved-memory-nodes.patch Normal file
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@ -0,0 +1,60 @@
From ad2d07f71739351eeea1d8a120c0918e2c4b265f Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 22 Dec 2021 12:23:34 +0100
Subject: [PATCH] arm64: dts: ipq8074: add reserved memory nodes
IPQ8074 has multiple reserved memory ranges, if they are not defined
then weird things tend to happen, board hangs and resets when PCI or
WLAN is used etc.
So, to avoid all of that add the reserved memory nodes from the downstream
5.4 kernel from QCA.
This is their default layout meant for devices with 1GB of RAM, but
devices with lower ammounts can override the Q6 node.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 35 +++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -85,6 +85,16 @@
#size-cells = <2>;
ranges;
+ nss@40000000 {
+ no-map;
+ reg = <0x0 0x40000000 0x0 0x01000000>;
+ };
+
+ tzapp_region: tzapp@4a400000 {
+ no-map;
+ reg = <0x0 0x4a400000 0x0 0x00200000>;
+ };
+
bootloader@4a600000 {
reg = <0x0 0x4a600000 0x0 0x400000>;
no-map;
@@ -107,6 +117,21 @@
reg = <0x0 0x4ac00000 0x0 0x400000>;
no-map;
};
+
+ q6_region: wcnss@4b000000 {
+ no-map;
+ reg = <0x0 0x4b000000 0x0 0x05f00000>;
+ };
+
+ q6_etr_region: q6_etr_dump@50f00000 {
+ no-map;
+ reg = <0x0 0x50f00000 0x0 0x00100000>;
+ };
+
+ m3_dump_region: m3_dump@51000000 {
+ no-map;
+ reg = <0x0 0x51000000 0x0 0x100000>;
+ };
};
firmware {

30
target/linux/qualcommax/patches-6.1/0110-arm64-dts-qcom-ipq8074-pass-QMP-PCI-PHY-PIPE-clocks-.patch Normal file
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@ -0,0 +1,30 @@
From 8a576b5bc9f0555d1d970cacabcaa24a3b74fa57 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 16 Nov 2022 22:15:01 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to
GCC
Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to
find them by matching globaly by name.
If not passed directly, driver maintains backwards compatibility by then
falling back to global lookup.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -399,8 +399,8 @@
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
- clocks = <&xo>, <&sleep_clk>;
- clock-names = "xo", "sleep_clk";
+ clocks = <&xo>, <&sleep_clk>, <&pcie_phy0>, <&pcie_phy1>;
+ clock-names = "xo", "sleep_clk", "pcie0_pipe", "pcie1_pipe";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;

43
target/linux/qualcommax/patches-6.1/0111-arm64-dts-qcom-ipq8074-use-msi-parent-for-PCIe.patch Normal file
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@ -0,0 +1,43 @@
From fb1f6850be00d8dd8a54017be4c1336e224069ac Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 16 Nov 2022 22:26:25 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: use msi-parent for PCIe
Instead of hardcoding the IRQ, simply use msi-parent instead.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -734,7 +734,7 @@
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
ranges = <0 0xb00a000 0xffd>;
- v2m@0 {
+ gic_v2m0: v2m@0 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xffd>;
@@ -847,8 +847,7 @@
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ msi-parent = <&gic_v2m0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 142
@@ -909,8 +908,7 @@
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ msi-parent = <&gic_v2m0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 75

155
target/linux/qualcommax/patches-6.1/0112-remoteproc-qcom-Add-PRNG-proxy-clock.patch Normal file
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@ -0,0 +1,155 @@
From 125681433c8e526356947acf572fe8ca8ad32291 Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:05 +0530
Subject: [PATCH] remoteproc: qcom: Add PRNG proxy clock
PRNG clock is needed by the secure PIL, support for the same
is added in subsequent patches.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
1 file changed, 47 insertions(+), 18 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -91,19 +91,6 @@ enum {
WCSS_QCS404,
};
-struct wcss_data {
- const char *firmware_name;
- unsigned int crash_reason_smem;
- u32 version;
- bool aon_reset_required;
- bool wcss_q6_reset_required;
- const char *ssr_name;
- const char *sysmon_name;
- int ssctl_id;
- const struct rproc_ops *ops;
- bool requires_force_stop;
-};
-
struct q6v5_wcss {
struct device *dev;
@@ -128,6 +115,7 @@ struct q6v5_wcss {
struct clk *qdsp6ss_xo_cbcr;
struct clk *qdsp6ss_core_gfmux;
struct clk *lcc_bcr_sleep;
+ struct clk *prng_clk;
struct regulator *cx_supply;
struct qcom_sysmon *sysmon;
@@ -151,6 +139,21 @@ struct q6v5_wcss {
struct qcom_rproc_ssr ssr_subdev;
};
+struct wcss_data {
+ int (*init_clock)(struct q6v5_wcss *wcss);
+ int (*init_regulator)(struct q6v5_wcss *wcss);
+ const char *firmware_name;
+ unsigned int crash_reason_smem;
+ u32 version;
+ bool aon_reset_required;
+ bool wcss_q6_reset_required;
+ const char *ssr_name;
+ const char *sysmon_name;
+ int ssctl_id;
+ const struct rproc_ops *ops;
+ bool requires_force_stop;
+};
+
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
{
int ret;
@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc
struct q6v5_wcss *wcss = rproc->priv;
int ret;
+ ret = clk_prepare_enable(wcss->prng_clk);
+ if (ret) {
+ dev_err(wcss->dev, "prng clock enable failed\n");
+ return ret;
+ }
+
qcom_q6v5_prepare(&wcss->q6v5);
/* Release Q6 and WCSS reset */
@@ -733,6 +742,7 @@ static int q6v5_wcss_stop(struct rproc *
return ret;
}
+ clk_disable_unprepare(wcss->prng_clk);
qcom_q6v5_unprepare(&wcss->q6v5);
return 0;
@@ -900,7 +910,21 @@ static int q6v5_alloc_memory_region(stru
return 0;
}
-static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
+static int ipq8074_init_clock(struct q6v5_wcss *wcss)
+{
+ int ret;
+
+ wcss->prng_clk = devm_clk_get(wcss->dev, "prng");
+ if (IS_ERR(wcss->prng_clk)) {
+ ret = PTR_ERR(wcss->prng_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "Failed to get prng clock\n");
+ return ret;
+ }
+ return 0;
+}
+
+static int qcs404_init_clock(struct q6v5_wcss *wcss)
{
int ret;
@@ -990,7 +1014,7 @@ static int q6v5_wcss_init_clock(struct q
return 0;
}
-static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
+static int qcs404_init_regulator(struct q6v5_wcss *wcss)
{
wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
if (IS_ERR(wcss->cx_supply))
@@ -1034,12 +1058,14 @@ static int q6v5_wcss_probe(struct platfo
if (ret)
goto free_rproc;
- if (wcss->version == WCSS_QCS404) {
- ret = q6v5_wcss_init_clock(wcss);
+ if (desc->init_clock) {
+ ret = desc->init_clock(wcss);
if (ret)
goto free_rproc;
+ }
- ret = q6v5_wcss_init_regulator(wcss);
+ if (desc->init_regulator) {
+ ret = desc->init_regulator(wcss);
if (ret)
goto free_rproc;
}
@@ -1087,6 +1113,7 @@ static int q6v5_wcss_remove(struct platf
}
static const struct wcss_data wcss_ipq8074_res_init = {
+ .init_clock = ipq8074_init_clock,
.firmware_name = "IPQ8074/q6_fw.mdt",
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
@@ -1096,6 +1123,8 @@ static const struct wcss_data wcss_ipq80
};
static const struct wcss_data wcss_qcs404_res_init = {
+ .init_clock = qcs404_init_clock,
+ .init_regulator = qcs404_init_regulator,
.crash_reason_smem = WCSS_CRASH_REASON,
.firmware_name = "wcnss.mdt",
.version = WCSS_QCS404,

143
target/linux/qualcommax/patches-6.1/0113-remoteproc-qcom-Add-secure-PIL-support.patch Normal file
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@ -0,0 +1,143 @@
From 7358d42dfbdfdb5d4f1d0d4c2e5c2bb4143a29b0 Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:06 +0530
Subject: [PATCH] remoteproc: qcom: Add secure PIL support
IPQ8074 uses secure PIL. Hence, adding the support for the same.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++--
1 file changed, 40 insertions(+), 3 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -18,6 +18,7 @@
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/soc/qcom/mdt_loader.h>
+#include <linux/qcom_scm.h>
#include "qcom_common.h"
#include "qcom_pil_info.h"
#include "qcom_q6v5.h"
@@ -86,6 +87,9 @@
#define TCSR_WCSS_CLK_ENABLE 0x14
#define MAX_HALT_REG 3
+
+#define WCNSS_PAS_ID 6
+
enum {
WCSS_IPQ8074,
WCSS_QCS404,
@@ -134,6 +138,7 @@ struct q6v5_wcss {
unsigned int crash_reason_smem;
u32 version;
bool requires_force_stop;
+ bool need_mem_protection;
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_ssr ssr_subdev;
@@ -152,6 +157,7 @@ struct wcss_data {
int ssctl_id;
const struct rproc_ops *ops;
bool requires_force_stop;
+ bool need_mem_protection;
};
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc
qcom_q6v5_prepare(&wcss->q6v5);
+ if (wcss->need_mem_protection) {
+ ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
+ if (ret) {
+ dev_err(wcss->dev, "wcss_reset failed\n");
+ return ret;
+ }
+ goto wait_for_reset;
+ }
+
/* Release Q6 and WCSS reset */
ret = reset_control_deassert(wcss->wcss_reset);
if (ret) {
@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc
if (ret)
goto wcss_q6_reset;
+wait_for_reset:
ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
if (ret == -ETIMEDOUT)
dev_err(wcss->dev, "start timed out\n");
@@ -718,6 +734,15 @@ static int q6v5_wcss_stop(struct rproc *
struct q6v5_wcss *wcss = rproc->priv;
int ret;
+ if (wcss->need_mem_protection) {
+ ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
+ if (ret) {
+ dev_err(wcss->dev, "not able to shutdown\n");
+ return ret;
+ }
+ goto pas_done;
+ }
+
/* WCSS powerdown */
if (wcss->requires_force_stop) {
ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
@@ -742,6 +767,7 @@ static int q6v5_wcss_stop(struct rproc *
return ret;
}
+pas_done:
clk_disable_unprepare(wcss->prng_clk);
qcom_q6v5_unprepare(&wcss->q6v5);
@@ -765,9 +791,15 @@ static int q6v5_wcss_load(struct rproc *
struct q6v5_wcss *wcss = rproc->priv;
int ret;
- ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
- 0, wcss->mem_region, wcss->mem_phys,
- wcss->mem_size, &wcss->mem_reloc);
+ if (wcss->need_mem_protection)
+ ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
+ WCNSS_PAS_ID, wcss->mem_region,
+ wcss->mem_phys, wcss->mem_size,
+ &wcss->mem_reloc);
+ else
+ ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
+ 0, wcss->mem_region, wcss->mem_phys,
+ wcss->mem_size, &wcss->mem_reloc);
if (ret)
return ret;
@@ -1036,6 +1068,9 @@ static int q6v5_wcss_probe(struct platfo
if (!desc)
return -EINVAL;
+ if (desc->need_mem_protection && !qcom_scm_is_available())
+ return -EPROBE_DEFER;
+
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
desc->firmware_name, sizeof(*wcss));
if (!rproc) {
@@ -1049,6 +1084,7 @@ static int q6v5_wcss_probe(struct platfo
wcss->version = desc->version;
wcss->requires_force_stop = desc->requires_force_stop;
+ wcss->need_mem_protection = desc->need_mem_protection;
ret = q6v5_wcss_init_mmio(wcss, pdev);
if (ret)
@@ -1120,6 +1156,7 @@ static const struct wcss_data wcss_ipq80
.wcss_q6_reset_required = true,
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
+ .need_mem_protection = true,
};
static const struct wcss_data wcss_qcs404_res_init = {

103
target/linux/qualcommax/patches-6.1/0114-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch Normal file
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@ -0,0 +1,103 @@
From b422c9d4f048b086ce83f44a7cfcddcce162897f Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:07 +0530
Subject: [PATCH] remoteproc: qcom: Add support for split q6 + m3 wlan firmware
IPQ8074 supports split firmware for q6 and m3 as well.
So add support for loading the m3 firmware before q6.
Now the drivers works fine for both split and unified
firmwares.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++----
1 file changed, 29 insertions(+), 4 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -139,6 +139,7 @@ struct q6v5_wcss {
u32 version;
bool requires_force_stop;
bool need_mem_protection;
+ const char *m3_firmware_name;
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_ssr ssr_subdev;
@@ -147,7 +148,8 @@ struct q6v5_wcss {
struct wcss_data {
int (*init_clock)(struct q6v5_wcss *wcss);
int (*init_regulator)(struct q6v5_wcss *wcss);
- const char *firmware_name;
+ const char *q6_firmware_name;
+ const char *m3_firmware_name;
unsigned int crash_reason_smem;
u32 version;
bool aon_reset_required;
@@ -789,8 +791,29 @@ static void *q6v5_wcss_da_to_va(struct r
static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
{
struct q6v5_wcss *wcss = rproc->priv;
+ const struct firmware *m3_fw;
int ret;
+ if (wcss->m3_firmware_name) {
+ ret = request_firmware(&m3_fw, wcss->m3_firmware_name,
+ wcss->dev);
+ if (ret)
+ goto skip_m3;
+
+ ret = qcom_mdt_load_no_init(wcss->dev, m3_fw,
+ wcss->m3_firmware_name, 0,
+ wcss->mem_region, wcss->mem_phys,
+ wcss->mem_size, &wcss->mem_reloc);
+
+ release_firmware(m3_fw);
+
+ if (ret) {
+ dev_err(wcss->dev, "can't load m3_fw.bXX\n");
+ return ret;
+ }
+ }
+
+skip_m3:
if (wcss->need_mem_protection)
ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
WCNSS_PAS_ID, wcss->mem_region,
@@ -1072,7 +1095,7 @@ static int q6v5_wcss_probe(struct platfo
return -EPROBE_DEFER;
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
- desc->firmware_name, sizeof(*wcss));
+ desc->q6_firmware_name, sizeof(*wcss));
if (!rproc) {
dev_err(&pdev->dev, "failed to allocate rproc\n");
return -ENOMEM;
@@ -1085,6 +1108,7 @@ static int q6v5_wcss_probe(struct platfo
wcss->version = desc->version;
wcss->requires_force_stop = desc->requires_force_stop;
wcss->need_mem_protection = desc->need_mem_protection;
+ wcss->m3_firmware_name = desc->m3_firmware_name;
ret = q6v5_wcss_init_mmio(wcss, pdev);
if (ret)
@@ -1150,7 +1174,8 @@ static int q6v5_wcss_remove(struct platf
static const struct wcss_data wcss_ipq8074_res_init = {
.init_clock = ipq8074_init_clock,
- .firmware_name = "IPQ8074/q6_fw.mdt",
+ .q6_firmware_name = "IPQ8074/q6_fw.mdt",
+ .m3_firmware_name = "IPQ8074/m3_fw.mdt",
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
.wcss_q6_reset_required = true,
@@ -1163,7 +1188,7 @@ static const struct wcss_data wcss_qcs40
.init_clock = qcs404_init_clock,
.init_regulator = qcs404_init_regulator,
.crash_reason_smem = WCSS_CRASH_REASON,
- .firmware_name = "wcnss.mdt",
+ .q6_firmware_name = "wcnss.mdt",
.version = WCSS_QCS404,
.aon_reset_required = false,
.wcss_q6_reset_required = false,

24
target/linux/qualcommax/patches-6.1/0115-remoteproc-qcom-Add-ssr-subdevice-identifier.patch Normal file
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@ -0,0 +1,24 @@
From 3a8f67b4770c817b04794c9a02e3f88f85d86280 Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:08 +0530
Subject: [PATCH] remoteproc: qcom: Add ssr subdevice identifier
Add name for ssr subdevice on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -1179,6 +1179,7 @@ static const struct wcss_data wcss_ipq80
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
.wcss_q6_reset_required = true,
+ .ssr_name = "q6wcss",
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
.need_mem_protection = true,

79
target/linux/qualcommax/patches-6.1/0116-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch Normal file
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@ -0,0 +1,79 @@
From 8c73af6e8d78c66cfef0f551b00d375ec0b67ff3 Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:09 +0530
Subject: [PATCH] remoteproc: qcom: Update regmap offsets for halt register
Fixed issue in reading halt-regs parameter from device-tree.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -86,7 +86,7 @@
#define TCSR_WCSS_CLK_MASK 0x1F
#define TCSR_WCSS_CLK_ENABLE 0x14
-#define MAX_HALT_REG 3
+#define MAX_HALT_REG 4
#define WCNSS_PAS_ID 6
@@ -154,6 +154,7 @@ struct wcss_data {
u32 version;
bool aon_reset_required;
bool wcss_q6_reset_required;
+ bool bcr_reset_required;
const char *ssr_name;
const char *sysmon_name;
int ssctl_id;
@@ -875,10 +876,13 @@ static int q6v5_wcss_init_reset(struct q
}
}
- wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset");
- if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
- dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
- return PTR_ERR(wcss->wcss_q6_bcr_reset);
+ if (desc->bcr_reset_required) {
+ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev,
+ "wcss_q6_bcr_reset");
+ if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
+ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
+ return PTR_ERR(wcss->wcss_q6_bcr_reset);
+ }
}
return 0;
@@ -929,9 +933,9 @@ static int q6v5_wcss_init_mmio(struct q6
return -EINVAL;
}
- wcss->halt_q6 = halt_reg[0];
- wcss->halt_wcss = halt_reg[1];
- wcss->halt_nc = halt_reg[2];
+ wcss->halt_q6 = halt_reg[1];
+ wcss->halt_wcss = halt_reg[2];
+ wcss->halt_nc = halt_reg[3];
return 0;
}
@@ -1179,6 +1183,7 @@ static const struct wcss_data wcss_ipq80
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
.wcss_q6_reset_required = true,
+ .bcr_reset_required = false,
.ssr_name = "q6wcss",
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
@@ -1193,6 +1198,7 @@ static const struct wcss_data wcss_qcs40
.version = WCSS_QCS404,
.aon_reset_required = false,
.wcss_q6_reset_required = false,
+ .bcr_reset_required = true,
.ssr_name = "mpss",
.sysmon_name = "wcnss",
.ssctl_id = 0x12,

26
target/linux/qualcommax/patches-6.1/0117-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch Normal file
View File

@ -0,0 +1,26 @@
From ff7c6533ed8c4de58ed6c8aab03ea59c03eb4f31 Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:10 +0530
Subject: [PATCH] dt-bindings: clock: qcom: Add reset for WCSSAON
Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
1 file changed, 1 insertion(+)
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -381,6 +381,7 @@
#define GCC_NSSPORT4_RESET 143
#define GCC_NSSPORT5_RESET 144
#define GCC_NSSPORT6_RESET 145
+#define GCC_WCSSAON_RESET 146
#define USB0_GDSC 0
#define USB1_GDSC 1

25
target/linux/qualcommax/patches-6.1/0118-clk-qcom-Add-WCSSAON-reset.patch Normal file
View File

@ -0,0 +1,25 @@
From 43d9788f546d24df22d8ba3fcc2497d7ccc198f3 Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:11 +0530
Subject: [PATCH] clk: qcom: Add WCSSAON reset
Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/qcom/gcc-ipq8074.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4711,6 +4711,7 @@ static const struct qcom_reset_map gcc_i
[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
[GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
+ [GCC_WCSSAON_RESET] = { 0x59010, 0 },
};
static struct gdsc *gcc_ipq8074_gdscs[] = {

48
target/linux/qualcommax/patches-6.1/0119-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch Normal file
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@ -0,0 +1,48 @@
From 406a332fd1bcc4e18d73cce390f56272fe9111d7 Mon Sep 17 00:00:00 2001
From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Date: Fri, 17 Apr 2020 16:37:10 +0530
Subject: [PATCH] remoteproc: wcss: disable auto boot for IPQ8074
There is no need for remoteproc to boot automatically, ath11k will trigger
booting when its probing.
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -161,6 +161,7 @@ struct wcss_data {
const struct rproc_ops *ops;
bool requires_force_stop;
bool need_mem_protection;
+ bool need_auto_boot;
};
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
@@ -1150,6 +1151,7 @@ static int q6v5_wcss_probe(struct platfo
desc->sysmon_name,
desc->ssctl_id);
+ rproc->auto_boot = desc->need_auto_boot;
ret = rproc_add(rproc);
if (ret)
goto free_rproc;
@@ -1188,6 +1190,7 @@ static const struct wcss_data wcss_ipq80
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
.need_mem_protection = true,
+ .need_auto_boot = false,
};
static const struct wcss_data wcss_qcs404_res_init = {
@@ -1204,6 +1207,7 @@ static const struct wcss_data wcss_qcs40
.ssctl_id = 0x12,
.ops = &q6v5_wcss_qcs404_ops,
.requires_force_stop = false,
+ .need_auto_boot = true,
};
static const struct of_device_id q6v5_wcss_of_match[] = {

120
target/linux/qualcommax/patches-6.1/0120-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch Normal file
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@ -0,0 +1,120 @@
From 7388400b8bd42f71d040dbf2fdbdcb834fcc0ede Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:13 +0530
Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
Enable remoteproc WCSS PIL driver with glink and ssr subdevices.
Also enables smp2p and mailboxes required for IPC.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -141,6 +141,32 @@
};
};
+ wcss: smp2p-wcss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <0 322 1>;
+
+ mboxes = <&apcs_glb 9>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ wcss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ qcom,smp2p-feature-ssr-ack;
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
@@ -417,6 +443,11 @@
reg = <0x01937000 0x21000>;
};
+ tcsr_q6: syscon@1945000 {
+ compatible = "syscon";
+ reg = <0x01945000 0xe000>;
+ };
+
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,
@@ -949,6 +980,56 @@
"axi_s_sticky";
status = "disabled";
};
+
+ q6v5_wcss: q6v5_wcss@cd00000 {
+ compatible = "qcom,ipq8074-wcss-pil";
+ reg = <0x0cd00000 0x4040>,
+ <0x004ab000 0x20>;
+ reg-names = "qdsp6",
+ "rmb";
+ qca,auto-restart;
+ qca,extended-intc;
+ interrupts-extended = <&intc 0 325 1>,
+ <&wcss_smp2p_in 0 0>,
+ <&wcss_smp2p_in 1 0>,
+ <&wcss_smp2p_in 2 0>,
+ <&wcss_smp2p_in 3 0>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ resets = <&gcc GCC_WCSSAON_RESET>,
+ <&gcc GCC_WCSS_BCR>,
+ <&gcc GCC_WCSS_Q6_BCR>;
+
+ reset-names = "wcss_aon_reset",
+ "wcss_reset",
+ "wcss_q6_reset";
+
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "prng";
+
+ qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
+
+ qcom,smem-states = <&wcss_smp2p_out 0>,
+ <&wcss_smp2p_out 1>;
+ qcom,smem-state-names = "shutdown",
+ "stop";
+
+ memory-region = <&q6_region>;
+
+ glink-edge {
+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 8>;
+
+ rpm_requests {
+ qcom,glink-channels = "IPCRTR";
+ };
+ };
+ };
};
timer {

135
target/linux/qualcommax/patches-6.1/0121-arm64-dts-ipq8074-Add-WLAN-node.patch Normal file
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@ -0,0 +1,135 @@
From a67d1901741c162645eda0dbdc3a2c0c2aff5cf4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 21 Dec 2021 14:49:36 +0100
Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node
IPQ8074 has a AHB based Q6v5 802.11ax radios that are supported
by the ath11k.
Add the required DT node to enable the built-in radios.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -1030,6 +1030,117 @@
};
};
};
+
+ wifi: wifi@c0000000 {
+ compatible = "qcom,ipq8074-wifi";
+ reg = <0xc000000 0x2000000>;
+
+ interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "misc-pulse1",
+ "misc-latch",
+ "sw-exception",
+ "ce0",
+ "ce1",
+ "ce2",
+ "ce3",
+ "ce4",
+ "ce5",
+ "ce6",
+ "ce7",
+ "ce8",
+ "ce9",
+ "ce10",
+ "ce11",
+ "host2wbm-desc-feed",
+ "host2reo-re-injection",
+ "host2reo-command",
+ "host2rxdma-monitor-ring3",
+ "host2rxdma-monitor-ring2",
+ "host2rxdma-monitor-ring1",
+ "reo2ost-exception",
+ "wbm2host-rx-release",
+ "reo2host-status",
+ "reo2host-destination-ring4",
+ "reo2host-destination-ring3",
+ "reo2host-destination-ring2",
+ "reo2host-destination-ring1",
+ "rxdma2host-monitor-destination-mac3",
+ "rxdma2host-monitor-destination-mac2",
+ "rxdma2host-monitor-destination-mac1",
+ "ppdu-end-interrupts-mac3",
+ "ppdu-end-interrupts-mac2",
+ "ppdu-end-interrupts-mac1",
+ "rxdma2host-monitor-status-ring-mac3",
+ "rxdma2host-monitor-status-ring-mac2",
+ "rxdma2host-monitor-status-ring-mac1",
+ "host2rxdma-host-buf-ring-mac3",
+ "host2rxdma-host-buf-ring-mac2",
+ "host2rxdma-host-buf-ring-mac1",
+ "rxdma2host-destination-ring-mac3",
+ "rxdma2host-destination-ring-mac2",
+ "rxdma2host-destination-ring-mac1",
+ "host2tcl-input-ring4",
+ "host2tcl-input-ring3",
+ "host2tcl-input-ring2",
+ "host2tcl-input-ring1",
+ "wbm2host-tx-completions-ring3",
+ "wbm2host-tx-completions-ring2",
+ "wbm2host-tx-completions-ring1",
+ "tcl2host-status-ring";
+ qcom,rproc = <&q6v5_wcss>;
+ status = "disabled";
+ };
};
timer {

59
target/linux/qualcommax/patches-6.1/0122-arm64-dts-ipq8074-add-CPU-clock.patch Normal file
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@ -0,0 +1,59 @@
From cb3ef99c1553565e1dc0301ccd5c1c0fa2d15c15 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 31 Dec 2021 17:56:14 +0100
Subject: [PATCH] arm64: dts: ipq8074: add CPU clock
Now that CPU clock is exposed and can be controlled, add the necessary
properties to the CPU nodes.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+#include <dt-bindings/clock/qcom,apss-ipq.h>
/ {
#address-cells = <2>;
@@ -38,6 +39,8 @@
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
CPU1: cpu@1 {
@@ -46,6 +49,8 @@
enable-method = "psci";
reg = <0x1>;
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
CPU2: cpu@2 {
@@ -54,6 +59,8 @@
enable-method = "psci";
reg = <0x2>;
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
CPU3: cpu@3 {
@@ -62,6 +69,8 @@
enable-method = "psci";
reg = <0x3>;
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
};
L2_0: l2-cache {

48
target/linux/qualcommax/patches-6.1/0123-arm64-dts-ipq8074-add-cooling-cells-to-CPU-nodes.patch Normal file
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@ -0,0 +1,48 @@
From 347ca56e86c99021fad059b9a8ef101245b8507e Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 31 Dec 2021 20:38:06 +0100
Subject: [PATCH] arm64: dts: ipq8074: add cooling cells to CPU nodes
Since there is CPU Freq support as well as thermal sensor support
now for the IPQ8074, add cooling cells to CPU nodes so that they can
be used as cooling devices using CPU Freq.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -41,6 +41,7 @@
enable-method = "psci";
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
CPU1: cpu@1 {
@@ -51,6 +52,7 @@
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
CPU2: cpu@2 {
@@ -61,6 +63,7 @@
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
CPU3: cpu@3 {
@@ -71,6 +74,7 @@
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
+ #cooling-cells = <2>;
};
L2_0: l2-cache {

128
target/linux/qualcommax/patches-6.1/0129-arm64-dts-qcom-ipq8074-add-QFPROM-fuses.patch Normal file
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@ -0,0 +1,128 @@
From 04d2fc6a551bbd972a6428059b45ce79cb9de9d7 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 6 May 2022 22:38:24 +0200
Subject: [PATCH] arm64: dts: qcom: ipq8074: add QFPROM fuses
Add the QFPROM node and CPR fuses.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 107 ++++++++++++++++++++++++++
1 file changed, 107 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -343,6 +343,113 @@
status = "disabled";
};
+ qfprom: efuse@a4000 {
+ compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
+ reg = <0x000a4000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpr_efuse_speedbin: speedbin@125 {
+ reg = <0x125 0x1>;
+ bits = <0 3>;
+ };
+
+ cpr_efuse_boost_cfg: boost_cfg@125 {
+ reg = <0x125 0x1>;
+ bits = <3 3>;
+ };
+
+ cpr_efuse_misc_volt_adj: misc_volt_adj@125 {
+ reg = <0x125 0x1>;
+ bits = <3 3>;
+ };
+
+ cpr_efuse_boost_volt: boost_volt@126 {
+ reg = <0x126 0x1>;
+ bits = <6 1>;
+ };
+
+ cpr_efuse_revision: revision@23e {
+ reg = <0x23e 0x1>;
+ bits = <5 3>;
+ };
+
+ cpr_efuse_ro_sel0: rosel0@249 {
+ reg = <0x249 0x1>;
+ bits = <0 4>;
+ };
+
+ cpr_efuse_ro_sel1: rosel1@248 {
+ reg = <0x248 0x1>;
+ bits = <4 4>;
+ };
+
+ cpr_efuse_ro_sel2: rosel2@248 {
+ reg = <0x248 0x2>;
+ bits = <0 4>;
+ };
+
+ cpr_efuse_ro_sel3: rosel3@249 {
+ reg = <0x249 0x1>;
+ bits = <4 4>;
+ };
+
+ cpr_efuse_init_voltage0: ivoltage0@23a {
+ reg = <0x23a 0x1>;
+ bits = <2 6>;
+ };
+
+ cpr_efuse_init_voltage1: ivoltage1@239 {
+ reg = <0x239 0x2>;
+ bits = <4 6>;
+ };
+
+ cpr_efuse_init_voltage2: ivoltage2@238 {
+ reg = <0x238 0x2>;
+ bits = <6 6>;
+ };
+
+ cpr_efuse_init_voltage3: ivoltage3@238 {
+ reg = <0x238 0x1>;
+ bits = <0 6>;
+ };
+
+ cpr_efuse_quot0: quot0@244 {
+ reg = <0x244 0x2>;
+ bits = <0 12>;
+ };
+
+ cpr_efuse_quot1: quot1@242 {
+ reg = <0x242 0x2>;
+ bits = <4 12>;
+ };
+
+ cpr_efuse_quot2: quot2@241 {
+ reg = <0x241 0x2>;
+ bits = <0 12>;
+ };
+
+ cpr_efuse_quot3: quot3@245 {
+ reg = <0x245 0x2>;
+ bits = <4 12>;
+ };
+
+ cpr_efuse_quot0_offset: quot0_offset@23d {
+ reg = <0x23d 0x2>;
+ bits = <6 7>;
+ };
+
+ cpr_efuse_quot1_offset: quot1_offset@23c {
+ reg = <0x23c 0x2>;
+ bits = <7 7>;
+ };
+
+ cpr_efuse_quot2_offset: quot2_offset@23c {
+ reg = <0x23c 0x1>;
+ bits = <0 7>;
+ };
+ };
+
prng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;

102
target/linux/qualcommax/patches-6.1/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch Normal file
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@ -0,0 +1,102 @@
From a20c4e8738a00087aa5d53fe5148ed484e23d229 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sat, 31 Dec 2022 13:56:26 +0100
Subject: [PATCH] arm64: dts: qcom: ipq8074: add CPU OPP table
Now that there is NVMEM CPUFreq support for IPQ8074, we can add the OPP
table for SoC.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 52 +++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -42,6 +42,7 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
};
CPU1: cpu@1 {
@@ -53,6 +54,7 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
};
CPU2: cpu@2 {
@@ -64,6 +66,7 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
};
CPU3: cpu@3 {
@@ -75,6 +78,7 @@
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
clock-names = "cpu";
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
};
L2_0: l2-cache {
@@ -83,6 +87,54 @@
};
};
+ cpu_opp_table: opp-table {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&cpr_efuse_speedbin>;
+ opp-shared;
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-microvolt = <1>;
+ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1382400000 {
+ opp-hz = /bits/ 64 <1382400000>;
+ opp-microvolt = <2>;
+ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-microvolt = <3>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ opp-microvolt = <4>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-microvolt = <5>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <6>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

61
target/linux/qualcommax/patches-6.1/0136-remoteproc-qcom-wcss-populate-driver-data-for-IPQ601.patch Normal file
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@ -0,0 +1,61 @@
From 9dd19a9ae36bc60d58287d0c52e53024d484e64d Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Fri, 29 Jan 2021 22:41:59 +0530
Subject: [PATCH 2/3] remoteproc: qcom: wcss: populate driver data for IPQ6018
Populate hardcoded param using driver data for IPQ6018 SoCs.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -970,7 +970,7 @@ static int q6v5_alloc_memory_region(stru
return 0;
}
-static int ipq8074_init_clock(struct q6v5_wcss *wcss)
+static int ipq_init_clock(struct q6v5_wcss *wcss)
{
int ret;
@@ -1179,7 +1179,7 @@ static int q6v5_wcss_remove(struct platf
}
static const struct wcss_data wcss_ipq8074_res_init = {
- .init_clock = ipq8074_init_clock,
+ .init_clock = ipq_init_clock,
.q6_firmware_name = "IPQ8074/q6_fw.mdt",
.m3_firmware_name = "IPQ8074/m3_fw.mdt",
.crash_reason_smem = WCSS_CRASH_REASON,
@@ -1193,6 +1193,20 @@ static const struct wcss_data wcss_ipq80
.need_auto_boot = false,
};
+static const struct wcss_data wcss_ipq6018_res_init = {
+ .init_clock = ipq_init_clock,
+ .q6_firmware_name = "IPQ6018/q6_fw.mdt",
+ .m3_firmware_name = "IPQ6018/m3_fw.mdt",
+ .crash_reason_smem = WCSS_CRASH_REASON,
+ .aon_reset_required = true,
+ .wcss_q6_reset_required = true,
+ .bcr_reset_required = false,
+ .ssr_name = "q6wcss",
+ .ops = &q6v5_wcss_ipq8074_ops,
+ .requires_force_stop = true,
+ .need_mem_protection = true,
+};
+
static const struct wcss_data wcss_qcs404_res_init = {
.init_clock = qcs404_init_clock,
.init_regulator = qcs404_init_regulator,
@@ -1212,6 +1226,7 @@ static const struct wcss_data wcss_qcs40
static const struct of_device_id q6v5_wcss_of_match[] = {
{ .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
+ { .compatible = "qcom,ipq6018-wcss-pil", .data = &wcss_ipq6018_res_init },
{ .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init },
{ },
};

45
target/linux/qualcommax/patches-6.1/0137-arm64-dts-qcom-ipq6018-add-SDHCI-node.patch Normal file
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@ -0,0 +1,45 @@
From e4d7544ce092807e8c5aeb618cec30e2eb9b40c2 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Mon, 24 Apr 2023 15:13:32 +0300
Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
IPQ6018 has one SD/eMMC controller, add node for it.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
Tested-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -469,6 +469,29 @@
};
};
+ sdhc_1: mmc@7804000 {
+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x07804000 0x0 0x1000>,
+ <0x0 0x07805000 0x0 0x1000>,
+ <0x0 0x07808000 0x0 0x2000>;
+ reg-names = "hc", "cqhci", "ice";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface", "core", "xo", "ice";
+
+ resets = <&gcc GCC_SDCC1_BCR>;
+ supports-cqe;
+ bus-width = <8>;
+ status = "disabled";
+ };
+
blsp_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0 0x07884000 0x0 0x2b000>;

27
target/linux/qualcommax/patches-6.1/0139-arm64-dts-qcom-ipq6018-add-LDOA2-regulator.patch Normal file
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@ -0,0 +1,27 @@
From d24bc08bfc66f47d6e0a294a080d62893a7696b5 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Thu, 18 Jan 2024 21:30:21 +0800
Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator
Add LDOA2 regulator of MP5496 to support SDCC voltage scaling.
Suggested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -178,6 +178,11 @@
regulator-max-microvolt = <1062500>;
regulator-always-on;
};
+
+ ipq6018_l2: l2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
};
};

42
target/linux/qualcommax/patches-6.1/0400-mtd-rawnand-add-support-for-TH58NYG3S0HBAI4.patch Normal file
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@ -0,0 +1,42 @@
From 8d8b37d3af2bdccf0a37d2017d876bfc6ce42552 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Fri, 20 Oct 2023 23:18:21 +0800
Subject: [PATCH 1/1] mtd: rawnand: add support for TH58NYG3S0HBAI4 NAND flash
The Toshiba TH58NYG3S0HBAI4 is detected with 128 byte OOB while the flash
has 256 bytes OOB. Since it is not an ONFI compliant NAND, the model name
cannot be read from anywhere, add a static NAND ID entry to correct this.
However, the NAND ID of this flash is inconsistent with the datasheet.
The actual NAND ID is only 4 ID bytes, the last ID byte is missing.
Datasheet available at (the ID table is on page 50):
https://europe.kioxia.com/content/dam/kioxia/newidr/productinfo/datasheet/201910/DST_TH58NYG3S0HBAI4-TDE_EN_31565.pdf
Datasheet NAND ID: {0x98, 0xa3, 0x91, 0x26, 0x76}
Actual NAND ID: {0x98, 0xa3, 0x91, 0x26}
It seems that this flash may be counterfeit, but another Toshiba flash
also has the same problem. Maybe the driver has a bug, or some Toshiba
nand flash is like this. Anyway, add a static NAND ID entry with only
4 ID bytes as a hack to make sure it works.
Tested on Arcadyan AW1000 flashed with OpenWrt.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
drivers/mtd/nand/raw/nand_ids.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -55,6 +55,9 @@ struct nand_flash_dev nand_flash_ids[] =
{ .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} },
SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664,
NAND_ECC_INFO(40, SZ_1K) },
+ {"TH58NYG3S0HBAI4 8G 1.8V 8-bit", /* Last ID bytes missing */
+ { .id = {0x98, 0xa3, 0x91, 0x26} },
+ SZ_4K, SZ_1K, SZ_256K, 0, 4, 256, NAND_ECC_INFO(8, SZ_512) },
{"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
{ .id = {0x98, 0xdc, 0x91, 0x15, 0x76} },
SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) },

1047
target/linux/qualcommax/patches-6.1/0900-power-Add-Qualcomm-APM.patch Normal file
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File diff suppressed because it is too large Load Diff

12144
target/linux/qualcommax/patches-6.1/0901-regulator-add-Qualcomm-CPR-regulators.patch Normal file
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File diff suppressed because it is too large Load Diff

24
target/linux/qualcommax/patches-6.1/0902-arm64-dts-ipq8074-add-label-to-clocks.patch Normal file
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@ -0,0 +1,24 @@
From 6baf7e4abcea6f7ac21eccf072a20078b39d064c Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 9 Feb 2022 23:13:26 +0100
Subject: [PATCH] arm64: dts: ipq8074: add label to clocks
Add label to clocks node as that makes it easy to add the NSS fixed
clocks that are required in their DTSI.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -15,7 +15,7 @@
compatible = "qcom,ipq8074";
interrupt-parent = <&intc>;
- clocks {
+ clocks: clocks {
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32768>;

40
target/linux/qualcommax/patches-6.1/0903-psci-dont-advertise-OSI-support-for-IPQ6018.patch Normal file
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@ -0,0 +1,40 @@
From 563db68137475d011b355bfe674d1b7a24778091 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sat, 8 Oct 2022 22:26:31 +0200
Subject: [PATCH] psci: dont advertise OSI support for IPQ6018
Some older IPQ60xx SoC series boards ship with TrustZone/QSEE firmware
older than TZ.WNS.5.1-00084 which will advertise OSI[1] but are broken
and trying to use OSI will cause the board to hang until WDT kicks in.
So workaround it by checking for SoC compatible and returning false so
OSI is not used.
[1] https://www.spinics.net/lists/linux-arm-msm/msg79916.html
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/firmware/psci/psci.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/drivers/firmware/psci/psci.c
+++ b/drivers/firmware/psci/psci.c
@@ -87,6 +87,18 @@ static inline bool psci_has_ext_power_st
bool psci_has_osi_support(void)
{
+ /*
+ * Some older IPQ60xx SoC series boards ship with
+ * TrustZone/QSEE firmware older than TZ.WNS.5.1-00084
+ * which will advertise OSI but is broken and trying
+ * to use OSI will cause the board to hang until WDT
+ * kicks in.
+ * So workaround it by checking for SoC compatible
+ * and returning false so OSI is not used.
+ */
+ if (of_machine_is_compatible("qcom,ipq6018"))
+ return false;
+
return psci_cpu_suspend_feature & PSCI_1_0_OS_INITIATED;
}

109
target/linux/qualcommax/patches-6.1/0904-clk-qcom-ipq6018-workaround-networking-clock-parenti.patch Normal file
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@ -0,0 +1,109 @@
From 0c5b5243ad55ae744e790ba90c5ad37a93bd1377 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 11 Oct 2022 23:38:45 +0200
Subject: [PATCH] clk: qcom: ipq6018: workaround networking clock parenting
Currently, networking clocks are only looked up by fw_name however,
these are registered and setup by SSDK and are not available to the
GCC driver at all, so work around that by providing a global name
fallback.
While we are here, provide global fallback for bias_pll_cc_clk and
bias_pll_nss_noc_clk as well as these are fixed clocks also not available
to the driver.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/clk/qcom/gcc-ipq6018.c | 39 +++++++++++++++++-----------------
1 file changed, 19 insertions(+), 20 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -361,7 +361,7 @@ static const struct freq_tbl ftbl_nss_pp
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
{ .fw_name = "xo" },
- { .fw_name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &nss_crypto_pll.clkr.hw },
@@ -527,12 +527,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data
gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo" },
- { .fw_name = "uniphy0_gcc_rx_clk" },
- { .fw_name = "uniphy0_gcc_tx_clk" },
- { .fw_name = "uniphy1_gcc_rx_clk" },
- { .fw_name = "uniphy1_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -574,12 +574,12 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data
gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo" },
- { .fw_name = "uniphy0_gcc_tx_clk" },
- { .fw_name = "uniphy0_gcc_rx_clk" },
- { .fw_name = "uniphy1_gcc_tx_clk" },
- { .fw_name = "uniphy1_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -715,10 +715,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
{ .fw_name = "xo" },
- { .fw_name = "uniphy0_gcc_rx_clk" },
- { .fw_name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
@@ -751,10 +751,10 @@ static const struct freq_tbl ftbl_nss_po
static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
{ .fw_name = "xo" },
- { .fw_name = "uniphy0_gcc_tx_clk" },
- { .fw_name = "uniphy0_gcc_rx_clk" },
+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
@@ -1898,12 +1898,11 @@ static const struct freq_tbl ftbl_ubi32_
{ }
};
-static const struct clk_parent_data
- gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
+static const struct clk_parent_data gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
{ .fw_name = "xo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
- { .fw_name = "bias_pll_nss_noc_clk" },
+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
};
static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {

40
target/linux/qualcommax/patches-6.1/0905-remoteproc-q6v5_wcss-change-ssr-name-for-ipq6018-wif.patch Normal file
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@ -0,0 +1,40 @@
From 505f9c8653fc218ca47a153ec58ebc16bef5502f Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 16 Jan 2024 10:42:40 +0200
Subject: [PATCH 16/19] remoteproc: q6v5_wcss: change ssr name for ipq6018 wifi
subsystem
On IPQ6018 this string ends up being sent to RPM when remoteproc stops
(on crash or rmmod ath11k). "q6wcss" is not a valid name (not found by
`strings` in rpm.mbn), so this causes RPM do 'something' (presumably crash)
causing a system reboot followed by hang in XBL, with no WDT running.
Let's change ssr_name to a more sensible 'wcnss', that does not cause such
issues.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -1143,8 +1143,8 @@ static int q6v5_wcss_probe(struct platfo
if (ret)
goto free_rproc;
- qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss");
- qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss");
+ qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ssr_name);
+ qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ssr_name);
if (desc->ssctl_id)
wcss->sysmon = qcom_add_sysmon_subdev(rproc,
@@ -1201,7 +1201,7 @@ static const struct wcss_data wcss_ipq60
.aon_reset_required = true,
.wcss_q6_reset_required = true,
.bcr_reset_required = false,
- .ssr_name = "q6wcss",
+ .ssr_name = "wcnss",
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
.need_mem_protection = true,

120
target/linux/qualcommax/patches-6.1/0906-arm64-dts-qcom-ipq6018-add-wifi-node.patch Normal file
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@ -0,0 +1,120 @@
From 153c74fc80b9f33ed1a50d7790bf6979fdceb370 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 16 Jan 2024 11:41:06 +0200
Subject: [PATCH 19/19] arm64: dts: qcom: ipq6018: add wifi node
IPQ6018 has a AHB based Q6v5 802.11ax radios that are supported
by the ath11k.
Add the required DT node to enable the built-in radios.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 96 +++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -807,6 +807,102 @@
};
};
+ wifi: wifi@c000000 {
+ compatible = "qcom,ipq6018-wifi";
+ reg = <0x0 0xc000000 0x0 0x1000000>;
+ qcom,rproc = <&q6v5_wcss>;
+ interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "misc-pulse1", "misc-latch", "sw-exception",
+ "watchdog", "ce0", "ce1", "ce2", "ce3", "ce4",
+ "ce5", "ce6", "ce7", "ce8", "ce9", "ce10",
+ "ce11", "host2wbm-desc-feed",
+ "host2reo-re-injection", "host2reo-command",
+ "host2rxdma-monitor-ring3",
+ "host2rxdma-monitor-ring2",
+ "host2rxdma-monitor-ring1",
+ "reo2ost-exception", "wbm2host-rx-release",
+ "reo2host-status",
+ "reo2host-destination-ring4",
+ "reo2host-destination-ring3",
+ "reo2host-destination-ring2",
+ "reo2host-destination-ring1",
+ "rxdma2host-monitor-destination-mac3",
+ "rxdma2host-monitor-destination-mac2",
+ "rxdma2host-monitor-destination-mac1",
+ "ppdu-end-interrupts-mac3",
+ "ppdu-end-interrupts-mac2",
+ "ppdu-end-interrupts-mac1",
+ "rxdma2host-monitor-status-ring-mac3",
+ "rxdma2host-monitor-status-ring-mac2",
+ "rxdma2host-monitor-status-ring-mac1",
+ "host2rxdma-host-buf-ring-mac3",
+ "host2rxdma-host-buf-ring-mac2",
+ "host2rxdma-host-buf-ring-mac1",
+ "rxdma2host-destination-ring-mac3",
+ "rxdma2host-destination-ring-mac2",
+ "rxdma2host-destination-ring-mac1",
+ "host2tcl-input-ring4",
+ "host2tcl-input-ring3",
+ "host2tcl-input-ring2",
+ "host2tcl-input-ring1",
+ "wbm2host-tx-completions-ring3",
+ "wbm2host-tx-completions-ring2",
+ "wbm2host-tx-completions-ring1",
+ "tcl2host-status-ring";
+ status = "disabled";
+ };
+
q6v5_wcss: remoteproc@cd00000 {
compatible = "qcom,ipq6018-wcss-pil";
reg = <0x0 0x0cd00000 0x0 0x4040>,

53
target/linux/qualcommax/patches-6.1/0907-soc-qcom-fix-smp2p-ack-on-ipq6018.patch Normal file
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@ -0,0 +1,53 @@
From d93936f175bd914067df8f63f5fbe6e3b77bb4d2 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 23 May 2023 14:46:28 +0300
Subject: [PATCH 11/19] soc: qcom: fix smp2p ack on ipq6018
IPQ6018 seem to need different ack mechanism for smp2p messaging. This
fixes q6v5_wcss remoteproc firmware reloading. Without this first load
is OK, but subsequent loads would hang and fail to complete.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
drivers/soc/qcom/smp2p.c | 6 +++++-
2 files changed, 6 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -1155,6 +1155,7 @@
wcss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
+ qcom,smp2p-feature-ssr-ack;
#qcom,smem-state-cells = <1>;
};
--- a/drivers/soc/qcom/smp2p.c
+++ b/drivers/soc/qcom/smp2p.c
@@ -158,6 +158,8 @@ struct qcom_smp2p {
struct list_head inbound;
struct list_head outbound;
+
+ bool need_ssr_ack;
};
static void qcom_smp2p_kick(struct qcom_smp2p *smp2p)
@@ -306,7 +308,7 @@ static irqreturn_t qcom_smp2p_intr(int i
ack_restart = qcom_smp2p_check_ssr(smp2p);
qcom_smp2p_notify_in(smp2p);
- if (ack_restart)
+ if (ack_restart || smp2p->need_ssr_ack)
qcom_smp2p_do_ssr_ack(smp2p);
}
@@ -427,6 +429,7 @@ static int qcom_smp2p_outbound_entry(str
/* Make the logical entry reference the physical value */
entry->value = &out->entries[out->valid_entries].value;
+ smp2p->need_ssr_ack = of_property_read_bool(node, "qcom,smp2p-feature-ssr-ack");
out->valid_entries++;

55
target/linux/qualcommax/patches-6.1/0908-remoteproc-qcom_q6v5_wcss-add-optional-qdss_at-clock.patch Normal file
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@ -0,0 +1,55 @@
From 87dbcc69a7e3fe6ccddf4fe9bdbf51330f5e4a77 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 23 Jan 2024 11:04:04 +0200
Subject: [PATCH] remoteproc: qcom_q6v5_wcss: add optional qdss_at clock
IPQ6018 needs QDSS_AT clock enabled when loading wifi. Optionally enable it
when provided by DT.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -120,6 +120,7 @@ struct q6v5_wcss {
struct clk *qdsp6ss_core_gfmux;
struct clk *lcc_bcr_sleep;
struct clk *prng_clk;
+ struct clk *qdss_clk;
struct regulator *cx_supply;
struct qcom_sysmon *sysmon;
@@ -259,6 +260,9 @@ static int q6v5_wcss_start(struct rproc
return ret;
}
+ if (wcss->qdss_clk)
+ clk_prepare_enable(wcss->qdss_clk);
+
qcom_q6v5_prepare(&wcss->q6v5);
if (wcss->need_mem_protection) {
@@ -772,6 +776,8 @@ static int q6v5_wcss_stop(struct rproc *
}
pas_done:
+ if (wcss->qdss_clk)
+ clk_disable_unprepare(wcss->qdss_clk);
clk_disable_unprepare(wcss->prng_clk);
qcom_q6v5_unprepare(&wcss->q6v5);
@@ -981,6 +987,12 @@ static int ipq_init_clock(struct q6v5_wc
dev_err(wcss->dev, "Failed to get prng clock\n");
return ret;
}
+
+ wcss->qdss_clk = devm_clk_get(wcss->dev, "qdss");
+ if (IS_ERR(wcss->qdss_clk)) {
+ wcss->qdss_clk = NULL;
+ }
+
return 0;
}

26
target/linux/qualcommax/patches-6.1/0909-arm64-dts-qcom-ipq6018-assign-QDSS_AT-clock-to-wifi-.patch Normal file
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@ -0,0 +1,26 @@
From 71f30e25d21ae4981ecef6653a4ba7dfeb80db7b Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 23 Jan 2024 11:04:57 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: assign QDSS_AT clock to wifi remoteproc
IPQ6018 needs to enable QDSS_AT clock when loading wifi firmware,
add it to wifi remoteproc clock list.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 ++++++++-------
1 file changed, 9 insertions(+), 8 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -928,8 +928,8 @@
"wcss_reset",
"wcss_q6_reset";
- clocks = <&gcc GCC_PRNG_AHB_CLK>;
- clock-names = "prng";
+ clocks = <&gcc GCC_PRNG_AHB_CLK>, <&gcc GCC_QDSS_AT_CLK>;
+ clock-names = "prng", "qdss" ;
qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;

65
target/linux/qualcommax/patches-6.1/0910-arm64-dts-qcom-ipq6018-change-voltage-to-perf-levels.patch Normal file
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@ -0,0 +1,65 @@
From c67a1814bb1d0df290cf1e3f9c966f04aa41b9b9 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Tue, 30 Jan 2024 12:43:56 +0200
Subject: [PATCH] arm64: dts: qcom: ipq6018: change voltage to perf levels for
CPR4 driver
Current CPR4 driver requires opp-microvolt to be an abstract
performance level instead of actual voltage level.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -106,42 +106,42 @@
opp-864000000 {
opp-hz = /bits/ 64 <864000000>;
- opp-microvolt = <725000>;
+ opp-microvolt = <1>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
- opp-microvolt = <787500>;
+ opp-microvolt = <2>;
opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
- opp-microvolt = <862500>;
+ opp-microvolt = <3>;
opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
- opp-microvolt = <925000>;
+ opp-microvolt = <4>;
opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <987500>;
+ opp-microvolt = <5>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1062500>;
+ opp-microvolt = <6>;
opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};