mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 16:31:13 +00:00
31 lines
1.2 KiB
Diff
31 lines
1.2 KiB
Diff
|
From 5fdc065751ee25688f99da501123f7e7d4020751 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Vladimir Oltean <vladimir.oltean@nxp.com>
|
||
|
|
Date: Fri, 22 Nov 2019 13:46:46 +0200
|
||
|
|
Subject: [PATCH] net: phylink: make QSGMII a valid PHY mode for in-band AN
|
||
|
|
|
||
|
|
QSGMII is a SerDes protocol clocked at 5 Gbaud (4 times higher than
|
||
|
|
SGMII which is clocked at 1.25 Gbaud), with the same 8b/10b encoding and
|
||
|
|
some extra symbols for synchronization. Logically it offers 4 SGMII
|
||
|
|
interfaces multiplexed onto the same physical lanes. Each MAC PCS has
|
||
|
|
its own in-band AN process with the system side of the QSGMII PHY, which
|
||
|
|
is identical to the regular SGMII AN process.
|
||
|
|
|
||
|
|
So allow QSGMII as a valid in-band AN mode, since it is no different
|
||
|
|
from software perspective from regular SGMII.
|
||
|
|
|
||
|
|
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
|
||
|
|
---
|
||
|
|
drivers/net/phy/phylink.c | 1 +
|
||
|
|
1 file changed, 1 insertion(+)
|
||
|
|
|
||
|
|
--- a/drivers/net/phy/phylink.c
|
||
|
|
+++ b/drivers/net/phy/phylink.c
|
||
|
|
@@ -283,6 +283,7 @@ static int phylink_parse_mode(struct phy
|
||
|
|
|
||
|
|
switch (pl->link_config.interface) {
|
||
|
|
case PHY_INTERFACE_MODE_SGMII:
|
||
|
|
+ case PHY_INTERFACE_MODE_QSGMII:
|
||
|
|
phylink_set(pl->supported, 10baseT_Half);
|
||
|
|
phylink_set(pl->supported, 10baseT_Full);
|
||
|
|
phylink_set(pl->supported, 100baseT_Half);
|