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57 lines
2.2 KiB
Diff
57 lines
2.2 KiB
Diff
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From d62184f6b06627b4fe922b08132e38c181d389a0 Mon Sep 17 00:00:00 2001
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From: Jagan Teki <jagan@amarulasolutions.com>
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Date: Tue, 28 Mar 2023 22:37:52 +0530
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Subject: [PATCH 1270/1350] drm/bridge: Document bridge init order with
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pre_enable_prev_first
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Upstream commit 113cc3ad8566e06d6c8ef4fc0075a938dedefab5
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In order to satisfy the MIPI DSI initialization sequence the bridge
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init order has been altered with the help of pre_enable_prev_first
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in pre_enable and post_disable bridge operations.
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Document the affected bridge init order with an example on the
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bridge operations helpers.
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Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Signed-off-by: Robert Foss <rfoss@kernel.org>
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Link: https://patchwork.freedesktop.org/patch/msgid/20230328170752.1102347-2-jagan@amarulasolutions.com
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---
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drivers/gpu/drm/drm_bridge.c | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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--- a/drivers/gpu/drm/drm_bridge.c
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+++ b/drivers/gpu/drm/drm_bridge.c
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@@ -657,6 +657,13 @@ static void drm_atomic_bridge_call_post_
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* bridge will be called before the previous one to reverse the @pre_enable
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* calling direction.
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*
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+ * Example:
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+ * Bridge A ---> Bridge B ---> Bridge C ---> Bridge D ---> Bridge E
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+ *
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+ * With pre_enable_prev_first flag enable in Bridge B, D, E then the resulting
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+ * @post_disable order would be,
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+ * Bridge B, Bridge A, Bridge E, Bridge D, Bridge C.
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+ *
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* Note: the bridge passed should be the one closest to the encoder
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*/
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void drm_atomic_bridge_chain_post_disable(struct drm_bridge *bridge,
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@@ -753,6 +760,13 @@ static void drm_atomic_bridge_call_pre_e
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* If a bridge sets @pre_enable_prev_first, then the pre_enable for the
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* prev bridge will be called before pre_enable of this bridge.
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*
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+ * Example:
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+ * Bridge A ---> Bridge B ---> Bridge C ---> Bridge D ---> Bridge E
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+ *
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+ * With pre_enable_prev_first flag enable in Bridge B, D, E then the resulting
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+ * @pre_enable order would be,
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+ * Bridge C, Bridge D, Bridge E, Bridge A, Bridge B.
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+ *
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* Note: the bridge passed should be the one closest to the encoder
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*/
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void drm_atomic_bridge_chain_pre_enable(struct drm_bridge *bridge,
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