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56 lines
1.8 KiB
Diff
56 lines
1.8 KiB
Diff
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From e13c24ef2f068e651b9996922a08843d53513cab Mon Sep 17 00:00:00 2001
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From: Wen He <wen.he_1@nxp.com>
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Date: Fri, 20 Sep 2019 16:34:18 +0800
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Subject: [PATCH] arm64: dts: ls1028a: Update the clock providers for the Mali
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DP500
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In order to maximise performance of the LCD Controller's 64-bit AXI
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bus, for any give speed bin of the device, the AXI master interface
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clock(ACLK) clock can be up to CPU_frequency/2, which is already
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capable of optimal performance. In general, ACLK is always expected
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to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and
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Main processing clock(PCLK) both are tied to the same clock as ACLK.
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This change followed the LS1028A Architecture Specification Manual.
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Signed-off-by: Wen He <wen.he_1@nxp.com>
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Acked-by: Li Yang <leoyang.li@nxp.com>
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Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 17 ++---------------
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1 file changed, 2 insertions(+), 15 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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@@ -90,20 +90,6 @@
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clocks = <&osc_27m>;
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};
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- aclk: clock-axi {
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- compatible = "fixed-clock";
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- #clock-cells = <0>;
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- clock-frequency = <650000000>;
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- clock-output-names= "aclk";
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- };
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-
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- pclk: clock-apb {
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- compatible = "fixed-clock";
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- #clock-cells = <0>;
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- clock-frequency = <650000000>;
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- clock-output-names= "pclk";
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- };
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-
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reboot {
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compatible ="syscon-reboot";
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regmap = <&rst>;
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@@ -862,7 +848,8 @@
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interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
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<0 223 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "DE", "SE";
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- clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>;
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+ clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>,
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+ <&clockgen 2 2>;
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clock-names = "pxlclk", "mclk", "aclk", "pclk";
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arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
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arm,malidp-arqos-value = <0xd000d000>;
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