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115 lines
3.6 KiB
Diff
115 lines
3.6 KiB
Diff
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From 92aff696c8708ff5293eb000e98456e23afe1cb3 Mon Sep 17 00:00:00 2001
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From: Pankaj Bansal <pankaj.bansal@nxp.com>
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Date: Mon, 22 Apr 2019 16:43:13 +0530
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Subject: [PATCH] arm64: dts: fsl: layerscape: fix warnings when compiling dts
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files
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when compiling dts file using DTC_FLAG='-@', the device tree compiler
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reports these warnings:
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Warning (alias_paths): /aliases: aliases property name must include
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only lowercase and '-'
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Fixed the node aliases to silence these warnings.
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Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 34 +++++++++++------------
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arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 28 +++++++++----------
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2 files changed, 31 insertions(+), 31 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
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@@ -3,7 +3,7 @@
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* Device Tree Include file for Freescale Layerscape-1043A family SoC.
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*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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- * Copyright 2018 NXP
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+ * Copyright 2018-2019 NXP
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*
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* Mingkai Hu <Mingkai.hu@freescale.com>
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*/
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@@ -24,22 +24,22 @@
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serial1 = &duart1;
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serial2 = &duart2;
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serial3 = &duart3;
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- sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
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- sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
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- sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
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- sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
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- qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
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- qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
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- qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
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- qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
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- qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
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- qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
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- qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
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- qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
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- emi1_slot1 = &ls1043mdio_s1;
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- emi1_slot2 = &ls1043mdio_s2;
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- emi1_slot3 = &ls1043mdio_s3;
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- emi1_slot4 = &ls1043mdio_s4;
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+ sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
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+ sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
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+ sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
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+ sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
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+ qsgmii-s1-p1 = &qsgmii_phy_s1_p1;
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+ qsgmii-s1-p2 = &qsgmii_phy_s1_p2;
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+ qsgmii-s1-p3 = &qsgmii_phy_s1_p3;
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+ qsgmii-s1-p4 = &qsgmii_phy_s1_p4;
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+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
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+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
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+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
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+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
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+ emi1-slot1 = &ls1043mdio_s1;
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+ emi1-slot2 = &ls1043mdio_s2;
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+ emi1-slot3 = &ls1043mdio_s3;
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+ emi1-slot4 = &ls1043mdio_s4;
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};
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chosen {
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
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@@ -3,7 +3,7 @@
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* Device Tree Include file for Freescale Layerscape-1046A family SoC.
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*
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* Copyright 2016 Freescale Semiconductor, Inc.
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- * Copyright 2018 NXP
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+ * Copyright 2018-2019 NXP
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*
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* Shaohui Xie <Shaohui.Xie@nxp.com>
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*/
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@@ -26,19 +26,19 @@
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serial2 = &duart2;
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serial3 = &duart3;
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- emi1_slot1 = &ls1046mdio_s1;
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- emi1_slot2 = &ls1046mdio_s2;
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- emi1_slot4 = &ls1046mdio_s4;
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-
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- sgmii_s1_p1 = &sgmii_phy_s1_p1;
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- sgmii_s1_p2 = &sgmii_phy_s1_p2;
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- sgmii_s1_p3 = &sgmii_phy_s1_p3;
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- sgmii_s1_p4 = &sgmii_phy_s1_p4;
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- sgmii_s4_p1 = &sgmii_phy_s4_p1;
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- qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
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- qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
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- qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
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- qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
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+ emi1-slot1 = &ls1046mdio_s1;
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+ emi1-slot2 = &ls1046mdio_s2;
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+ emi1-slot4 = &ls1046mdio_s4;
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+
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+ sgmii-s1-p1 = &sgmii_phy_s1_p1;
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+ sgmii-s1-p2 = &sgmii_phy_s1_p2;
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+ sgmii-s1-p3 = &sgmii_phy_s1_p3;
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+ sgmii-s1-p4 = &sgmii_phy_s1_p4;
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+ sgmii-s4-p1 = &sgmii_phy_s4_p1;
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+ qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
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+ qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
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+ qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
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+ qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
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};
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chosen {
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