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52 lines
1.9 KiB
Diff
52 lines
1.9 KiB
Diff
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From 7cc1ca9e3a87027dbe6598a0c50cb466fc5861e4 Mon Sep 17 00:00:00 2001
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From: Xiaowei Bao <xiaowei.bao@nxp.com>
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Date: Tue, 22 Jan 2019 19:19:30 +0800
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Subject: [PATCH] PCI: mobiveil: Add workaround for unsupported request error
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Errata: unsupported request error on inbound posted write
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transaction, PCIe controller reports advisory error instead
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of uncorrectable error message to RC.
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Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
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Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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---
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drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c | 13 +++++++++++++
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drivers/pci/controller/mobiveil/pcie-mobiveil.h | 4 ++++
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2 files changed, 17 insertions(+)
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--- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
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+++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
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@@ -49,6 +49,19 @@ static void ls_pcie_g4_ep_init(struct mo
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struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
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int win_idx;
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u8 bar;
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+ u32 val;
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+
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+ /*
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+ * Errata: unsupported request error on inbound posted write
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+ * transaction, PCIe controller reports advisory error instead
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+ * of uncorrectable error message to RC.
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+ * workaround: set the bit20(unsupported_request_Error_severity) with
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+ * value 1 in uncorrectable_Error_Severity_Register, make the
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+ * unsupported request error generate the fatal error.
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+ */
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+ val = csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY);
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+ val |= 1 << UNSUPPORTED_REQUEST_ERROR_SHIFT;
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+ csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY);
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ep->bar_num = PCIE_LX2_BAR_NUM;
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--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
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+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
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@@ -123,6 +123,10 @@
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#define GPEX_BAR_SIZE_UDW 0x4DC
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#define GPEX_BAR_SELECT 0x4E0
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+#define CFG_UNCORRECTABLE_ERROR_SEVERITY 0x10c
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+#define UNSUPPORTED_REQUEST_ERROR_SHIFT 20
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+#define CFG_UNCORRECTABLE_ERROR_MASK 0x108
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+
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/* starting offset of INTX bits in status register */
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#define PAB_INTX_START 5
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