2020-04-10 02:47:05 +00:00
|
|
|
From 53c3bd0d5a873c23841bb95e7b95c1c3630c50bd Mon Sep 17 00:00:00 2001
|
|
|
|
|
From: Vladimir Oltean <vladimir.oltean@nxp.com>
|
|
|
|
|
Date: Thu, 12 Jul 2018 13:03:13 +0300
|
|
|
|
|
Subject: [PATCH] at803x: Address packet drops at low traffic rate due to
|
|
|
|
|
SmartEEE feature
|
|
|
|
|
|
|
|
|
|
* According to the AR8035 datasheet, smartEEE mode (active by default)
|
|
|
|
|
makes the PHY enters sleep after a configurable idle time. It does
|
|
|
|
|
this autonomously, without LPI (Low Power Idle) signals coming from MAC.
|
|
|
|
|
* Tested with ping (default of 1 second interval) over back-to-back
|
|
|
|
|
RGMII between 2 boards having AR8035 at both ends:
|
|
|
|
|
- Without patch:
|
|
|
|
|
225 packets transmitted, 145 received, 35% packet loss, time 229334ms
|
|
|
|
|
- With patch:
|
|
|
|
|
144 packets transmitted, 144 received, 0% packet loss, time 146378ms
|
|
|
|
|
|
|
|
|
|
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
|
|
|
|
|
---
|
|
|
|
|
drivers/net/phy/Kconfig | 10 ++++++++++
|
|
|
|
|
drivers/net/phy/at803x.c | 22 ++++++++++++++++++++++
|
|
|
|
|
2 files changed, 32 insertions(+)
|
|
|
|
|
|
|
|
|
|
--- a/drivers/net/phy/Kconfig
|
|
|
|
|
+++ b/drivers/net/phy/Kconfig
|
2020-11-19 15:30:16 +00:00
|
|
|
@@ -367,6 +367,16 @@ config AT803X_PHY
|
2020-04-10 02:47:05 +00:00
|
|
|
---help---
|
|
|
|
|
Currently supports the AT8030 and AT8035 model
|
|
|
|
|
|
|
|
|
|
+config AT803X_PHY_SMART_EEE
|
|
|
|
|
+ depends on AT803X_PHY
|
|
|
|
|
+ default n
|
|
|
|
|
+ tristate "SmartEEE feature for AT803X PHYs"
|
|
|
|
|
+ ---help---
|
|
|
|
|
+ Enables the Atheros SmartEEE feature (not IEEE 802.3az). When 2 PHYs
|
|
|
|
|
+ which support this feature are connected back-to-back, they may
|
|
|
|
|
+ negotiate a low-power sleep mode autonomously, without the Ethernet
|
|
|
|
|
+ controller's knowledge. May cause packet loss.
|
|
|
|
|
+
|
|
|
|
|
config BCM63XX_PHY
|
|
|
|
|
tristate "Broadcom 63xx SOCs internal PHY"
|
|
|
|
|
depends on BCM63XX || COMPILE_TEST
|
|
|
|
|
--- a/drivers/net/phy/at803x.c
|
|
|
|
|
+++ b/drivers/net/phy/at803x.c
|
|
|
|
|
@@ -63,6 +63,8 @@
|
|
|
|
|
#define AT803X_DEBUG_REG_5 0x05
|
|
|
|
|
#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
|
|
|
|
|
|
|
|
|
|
+#define AT803X_LPI_EN BIT(8)
|
|
|
|
|
+
|
|
|
|
|
#define ATH8030_PHY_ID 0x004dd076
|
|
|
|
|
#define ATH8031_PHY_ID 0x004dd074
|
|
|
|
|
#define ATH8032_PHY_ID 0x004dd023
|
|
|
|
|
@@ -257,6 +259,19 @@ static int at803x_probe(struct phy_devic
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
+static void at803x_enable_smart_eee(struct phy_device *phydev, int on)
|
|
|
|
|
+{
|
|
|
|
|
+ int value;
|
|
|
|
|
+
|
|
|
|
|
+ /* 5.1.11 Smart_eee control3 */
|
|
|
|
|
+ value = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x805D);
|
|
|
|
|
+ if (on)
|
|
|
|
|
+ value |= AT803X_LPI_EN;
|
|
|
|
|
+ else
|
|
|
|
|
+ value &= ~AT803X_LPI_EN;
|
|
|
|
|
+ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x805D, value);
|
|
|
|
|
+}
|
|
|
|
|
+
|
|
|
|
|
static int at803x_config_init(struct phy_device *phydev)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
@@ -282,6 +297,13 @@ static int at803x_config_init(struct phy
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
+
|
|
|
|
|
+#ifdef CONFIG_AT803X_PHY_SMART_EEE
|
|
|
|
|
+ at803x_enable_smart_eee(phydev, 1);
|
|
|
|
|
+#else
|
|
|
|
|
+ at803x_enable_smart_eee(phydev, 0);
|
|
|
|
|
+#endif
|
|
|
|
|
+
|
|
|
|
|
/* The RX and TX delay default is:
|
|
|
|
|
* after HW reset: RX delay enabled and TX delay disabled
|
|
|
|
|
* after SW reset: RX delay enabled, while TX delay retains the
|
