2020-04-10 02:47:05 +00:00
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From 27aa9f97887f599267c345075e61979de785c770 Mon Sep 17 00:00:00 2001
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From: Peng Ma <peng.ma@nxp.com>
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Date: Thu, 11 Oct 2018 16:49:41 +0800
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Subject: [PATCH] dma: caam: add dma memcpy driver
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This module introduces a memcpy DMA driver based on the DMA capabilities
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of the CAAM hardware block. CAAM DMA is a platform driver that is only
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probed if the device is defined in the device tree. The driver creates
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a DMA channel for each JR of the CAAM. This introduces a dependency on
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the JR driver. Therefore a defering mechanism was used to ensure that
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the CAAM DMA driver is probed only after the JR driver.
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Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
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Signed-off-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com>
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Signed-off-by: Rajiv Vishwakarma <rajiv.vishwakarma@nxp.com>
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Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
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[rebase]
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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drivers/dma/Kconfig | 19 +-
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drivers/dma/Makefile | 1 +
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drivers/dma/caam_dma.c | 462 +++++++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 481 insertions(+), 1 deletion(-)
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create mode 100644 drivers/dma/caam_dma.c
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--- a/drivers/dma/Kconfig
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+++ b/drivers/dma/Kconfig
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2021-06-26 19:08:19 +00:00
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@@ -132,6 +132,24 @@ config COH901318
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2020-04-10 02:47:05 +00:00
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help
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Enable support for ST-Ericsson COH 901 318 DMA.
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+config CRYPTO_DEV_FSL_CAAM_DMA
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+ tristate "CAAM DMA engine support"
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+ depends on CRYPTO_DEV_FSL_CAAM_JR
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+ default n
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+ select DMA_ENGINE
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+ select ASYNC_CORE
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+ select ASYNC_TX_ENABLE_CHANNEL_SWITCH
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+ help
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+ Selecting this will offload the DMA operations for users of
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+ the scatter gather memcopy API to the CAAM via job rings. The
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+ CAAM is a hardware module that provides hardware acceleration to
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+ cryptographic operations. It has a built-in DMA controller that can
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+ be programmed to read/write cryptographic data. This module defines
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+ a DMA driver that uses the DMA capabilities of the CAAM.
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+
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+ To compile this as a module, choose M here: the module
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+ will be called caam_dma.
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+
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config DMA_BCM2835
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tristate "BCM2835 DMA engine support"
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depends on ARCH_BCM2835
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2021-06-26 19:08:19 +00:00
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@@ -663,7 +681,6 @@ config ZX_DMA
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2020-04-10 02:47:05 +00:00
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help
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Support the DMA engine for ZTE ZX family platform devices.
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-
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# driver files
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source "drivers/dma/bestcomm/Kconfig"
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--- a/drivers/dma/Makefile
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+++ b/drivers/dma/Makefile
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@@ -77,6 +77,7 @@ obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
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obj-$(CONFIG_ZX_DMA) += zx_dma.o
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obj-$(CONFIG_ST_FDMA) += st_fdma.o
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obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/
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+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_DMA) += caam_dma.o
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obj-y += mediatek/
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obj-y += qcom/
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--- /dev/null
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+++ b/drivers/dma/caam_dma.c
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@@ -0,0 +1,462 @@
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+/*
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+ * caam support for SG DMA
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+ *
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+ * Copyright 2016 Freescale Semiconductor, Inc
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+ * Copyright 2017 NXP
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in the
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+ * documentation and/or other materials provided with the distribution.
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+ * * Neither the names of the above-listed copyright holders nor the
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+ * names of any contributors may be used to endorse or promote products
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+ * derived from this software without specific prior written permission.
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+ *
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+ *
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+ * ALTERNATIVELY, this software may be distributed under the terms of the
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+ * GNU General Public License ("GPL") as published by the Free Software
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+ * Foundation, either version 2 of that License or (at your option) any
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+ * later version.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
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+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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+ * POSSIBILITY OF SUCH DAMAGE.
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+ */
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+
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+#include <linux/dma-mapping.h>
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+#include <linux/dmaengine.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+
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+#include "dmaengine.h"
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+
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+#include "../crypto/caam/regs.h"
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+#include "../crypto/caam/jr.h"
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+#include "../crypto/caam/error.h"
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+#include "../crypto/caam/desc_constr.h"
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+
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+#define DESC_DMA_MEMCPY_LEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / \
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+ CAAM_CMD_SZ)
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+
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+/*
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+ * This is max chunk size of a DMA transfer. If a buffer is larger than this
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+ * value it is internally broken into chunks of max CAAM_DMA_CHUNK_SIZE bytes
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+ * and for each chunk a DMA transfer request is issued.
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+ * This value is the largest number on 16 bits that is a multiple of 256 bytes
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+ * (the largest configurable CAAM DMA burst size).
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+ */
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+#define CAAM_DMA_CHUNK_SIZE 65280
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+
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+struct caam_dma_sh_desc {
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+ u32 desc[DESC_DMA_MEMCPY_LEN] ____cacheline_aligned;
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+ dma_addr_t desc_dma;
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+};
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+
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+/* caam dma extended descriptor */
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+struct caam_dma_edesc {
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+ struct dma_async_tx_descriptor async_tx;
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+ struct list_head node;
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+ struct caam_dma_ctx *ctx;
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+ dma_addr_t src_dma;
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+ dma_addr_t dst_dma;
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+ unsigned int src_len;
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+ unsigned int dst_len;
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+ u32 jd[] ____cacheline_aligned;
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+};
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+
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+/*
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+ * caam_dma_ctx - per jr/channel context
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+ * @chan: dma channel used by async_tx API
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+ * @node: list_head used to attach to the global dma_ctx_list
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+ * @jrdev: Job Ring device
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+ * @pending_q: queue of pending (submitted, but not enqueued) jobs
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+ * @done_not_acked: jobs that have been completed by jr, but maybe not acked
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+ * @edesc_lock: protects extended descriptor
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+ */
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+struct caam_dma_ctx {
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+ struct dma_chan chan;
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+ struct list_head node;
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+ struct device *jrdev;
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+ struct list_head pending_q;
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+ struct list_head done_not_acked;
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+ spinlock_t edesc_lock;
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+};
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+
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+static struct dma_device *dma_dev;
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+static struct caam_dma_sh_desc *dma_sh_desc;
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+static LIST_HEAD(dma_ctx_list);
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+
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+static dma_cookie_t caam_dma_tx_submit(struct dma_async_tx_descriptor *tx)
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+{
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+ struct caam_dma_edesc *edesc = NULL;
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+ struct caam_dma_ctx *ctx = NULL;
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+ dma_cookie_t cookie;
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+
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+ edesc = container_of(tx, struct caam_dma_edesc, async_tx);
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+ ctx = container_of(tx->chan, struct caam_dma_ctx, chan);
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+
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+ spin_lock_bh(&ctx->edesc_lock);
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+
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+ cookie = dma_cookie_assign(tx);
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+ list_add_tail(&edesc->node, &ctx->pending_q);
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+
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+ spin_unlock_bh(&ctx->edesc_lock);
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+
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+ return cookie;
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+}
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+
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+static void caam_jr_chan_free_edesc(struct caam_dma_edesc *edesc)
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+{
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+ struct caam_dma_ctx *ctx = edesc->ctx;
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+ struct caam_dma_edesc *_edesc = NULL;
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+
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+ spin_lock_bh(&ctx->edesc_lock);
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+
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+ list_add_tail(&edesc->node, &ctx->done_not_acked);
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+ list_for_each_entry_safe(edesc, _edesc, &ctx->done_not_acked, node) {
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+ if (async_tx_test_ack(&edesc->async_tx)) {
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+ list_del(&edesc->node);
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+ kfree(edesc);
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+ }
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+ }
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+
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+ spin_unlock_bh(&ctx->edesc_lock);
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+}
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+
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+static void caam_dma_done(struct device *dev, u32 *hwdesc, u32 err,
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+ void *context)
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+{
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+ struct caam_dma_edesc *edesc = context;
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+ struct caam_dma_ctx *ctx = edesc->ctx;
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+ dma_async_tx_callback callback;
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+ void *callback_param;
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+
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+ if (err)
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+ caam_jr_strstatus(ctx->jrdev, err);
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+
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+ dma_run_dependencies(&edesc->async_tx);
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+
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+ spin_lock_bh(&ctx->edesc_lock);
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+ dma_cookie_complete(&edesc->async_tx);
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+ spin_unlock_bh(&ctx->edesc_lock);
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+
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+ callback = edesc->async_tx.callback;
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+ callback_param = edesc->async_tx.callback_param;
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+
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+ dma_descriptor_unmap(&edesc->async_tx);
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+
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+ caam_jr_chan_free_edesc(edesc);
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+
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+ if (callback)
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+ callback(callback_param);
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+}
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+
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+static void caam_dma_memcpy_init_job_desc(struct caam_dma_edesc *edesc)
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+{
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+ u32 *jd = edesc->jd;
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+ u32 *sh_desc = dma_sh_desc->desc;
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+ dma_addr_t desc_dma = dma_sh_desc->desc_dma;
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+
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+ /* init the job descriptor */
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+ init_job_desc_shared(jd, desc_dma, desc_len(sh_desc), HDR_REVERSE);
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+
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+ /* set SEQIN PTR */
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+ append_seq_in_ptr(jd, edesc->src_dma, edesc->src_len, 0);
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+
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+ /* set SEQOUT PTR */
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+ append_seq_out_ptr(jd, edesc->dst_dma, edesc->dst_len, 0);
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+
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+ print_hex_dump_debug("caam dma desc@" __stringify(__LINE__) ": ",
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+ DUMP_PREFIX_ADDRESS, 16, 4, jd, desc_bytes(jd), 1);
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+}
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+
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+static struct dma_async_tx_descriptor *
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+caam_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
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+ size_t len, unsigned long flags)
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+{
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+ struct caam_dma_edesc *edesc;
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+ struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx,
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+ chan);
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+
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+ edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN, GFP_DMA | GFP_NOWAIT);
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+ if (!edesc)
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+ return ERR_PTR(-ENOMEM);
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+
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+ dma_async_tx_descriptor_init(&edesc->async_tx, chan);
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+ edesc->async_tx.tx_submit = caam_dma_tx_submit;
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+ edesc->async_tx.flags = flags;
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+ edesc->async_tx.cookie = -EBUSY;
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+
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+ edesc->src_dma = src;
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+ edesc->src_len = len;
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+ edesc->dst_dma = dst;
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+ edesc->dst_len = len;
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+ edesc->ctx = ctx;
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+
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+ caam_dma_memcpy_init_job_desc(edesc);
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+
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+ return &edesc->async_tx;
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+}
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+
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+/* This function can be called in an interrupt context */
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+static void caam_dma_issue_pending(struct dma_chan *chan)
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+{
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+ struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx,
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+ chan);
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+ struct caam_dma_edesc *edesc, *_edesc;
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+
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+ spin_lock_bh(&ctx->edesc_lock);
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+ list_for_each_entry_safe(edesc, _edesc, &ctx->pending_q, node) {
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+ if (caam_jr_enqueue(ctx->jrdev, edesc->jd,
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+ caam_dma_done, edesc) < 0)
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+ break;
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+ list_del(&edesc->node);
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+ }
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+ spin_unlock_bh(&ctx->edesc_lock);
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+}
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+
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+static void caam_dma_free_chan_resources(struct dma_chan *chan)
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+{
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+ struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx,
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+ chan);
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+ struct caam_dma_edesc *edesc, *_edesc;
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+
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+ spin_lock_bh(&ctx->edesc_lock);
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+ list_for_each_entry_safe(edesc, _edesc, &ctx->pending_q, node) {
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+ list_del(&edesc->node);
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+ kfree(edesc);
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+ }
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+ list_for_each_entry_safe(edesc, _edesc, &ctx->done_not_acked, node) {
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+ list_del(&edesc->node);
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+ kfree(edesc);
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+ }
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+ spin_unlock_bh(&ctx->edesc_lock);
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+}
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+
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+static int caam_dma_jr_chan_bind(void)
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+{
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+ struct device *jrdev;
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+ struct caam_dma_ctx *ctx;
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+ int bonds = 0;
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+ int i;
|
|
|
|
+
|
|
|
|
+ for (i = 0; i < caam_jr_driver_probed(); i++) {
|
|
|
|
+ jrdev = caam_jridx_alloc(i);
|
|
|
|
+ if (IS_ERR(jrdev)) {
|
|
|
|
+ pr_err("job ring device %d allocation failed\n", i);
|
|
|
|
+ continue;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
|
|
|
|
+ if (!ctx) {
|
|
|
|
+ caam_jr_free(jrdev);
|
|
|
|
+ continue;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ ctx->chan.device = dma_dev;
|
|
|
|
+ ctx->chan.private = ctx;
|
|
|
|
+
|
|
|
|
+ ctx->jrdev = jrdev;
|
|
|
|
+
|
|
|
|
+ INIT_LIST_HEAD(&ctx->pending_q);
|
|
|
|
+ INIT_LIST_HEAD(&ctx->done_not_acked);
|
|
|
|
+ INIT_LIST_HEAD(&ctx->node);
|
|
|
|
+ spin_lock_init(&ctx->edesc_lock);
|
|
|
|
+
|
|
|
|
+ dma_cookie_init(&ctx->chan);
|
|
|
|
+
|
|
|
|
+ /* add the context of this channel to the context list */
|
|
|
|
+ list_add_tail(&ctx->node, &dma_ctx_list);
|
|
|
|
+
|
|
|
|
+ /* add this channel to the device chan list */
|
|
|
|
+ list_add_tail(&ctx->chan.device_node, &dma_dev->channels);
|
|
|
|
+
|
|
|
|
+ bonds++;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ return bonds;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static inline void caam_jr_dma_free(struct dma_chan *chan)
|
|
|
|
+{
|
|
|
|
+ struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx,
|
|
|
|
+ chan);
|
|
|
|
+
|
|
|
|
+ list_del(&ctx->node);
|
|
|
|
+ list_del(&chan->device_node);
|
|
|
|
+ caam_jr_free(ctx->jrdev);
|
|
|
|
+ kfree(ctx);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void set_caam_dma_desc(u32 *desc)
|
|
|
|
+{
|
|
|
|
+ u32 *jmp_cmd;
|
|
|
|
+
|
|
|
|
+ /* dma shared descriptor */
|
|
|
|
+ init_sh_desc(desc, HDR_SHARE_NEVER | (1 << HDR_START_IDX_SHIFT));
|
|
|
|
+
|
|
|
|
+ /* REG1 = CAAM_DMA_CHUNK_SIZE */
|
|
|
|
+ append_math_add_imm_u32(desc, REG1, ZERO, IMM, CAAM_DMA_CHUNK_SIZE);
|
|
|
|
+
|
|
|
|
+ /* REG0 = SEQINLEN - CAAM_DMA_CHUNK_SIZE */
|
|
|
|
+ append_math_sub_imm_u32(desc, REG0, SEQINLEN, IMM, CAAM_DMA_CHUNK_SIZE);
|
|
|
|
+
|
|
|
|
+ /*
|
|
|
|
+ * if (REG0 > 0)
|
|
|
|
+ * jmp to LABEL1
|
|
|
|
+ */
|
|
|
|
+ jmp_cmd = append_jump(desc, JUMP_TEST_INVALL | JUMP_COND_MATH_N |
|
|
|
|
+ JUMP_COND_MATH_Z);
|
|
|
|
+
|
|
|
|
+ /* REG1 = SEQINLEN */
|
|
|
|
+ append_math_sub(desc, REG1, SEQINLEN, ZERO, CAAM_CMD_SZ);
|
|
|
|
+
|
|
|
|
+ /* LABEL1 */
|
|
|
|
+ set_jump_tgt_here(desc, jmp_cmd);
|
|
|
|
+
|
|
|
|
+ /* VARSEQINLEN = REG1 */
|
|
|
|
+ append_math_add(desc, VARSEQINLEN, REG1, ZERO, CAAM_CMD_SZ);
|
|
|
|
+
|
|
|
|
+ /* VARSEQOUTLEN = REG1 */
|
|
|
|
+ append_math_add(desc, VARSEQOUTLEN, REG1, ZERO, CAAM_CMD_SZ);
|
|
|
|
+
|
|
|
|
+ /* do FIFO STORE */
|
|
|
|
+ append_seq_fifo_store(desc, 0, FIFOST_TYPE_METADATA | LDST_VLF);
|
|
|
|
+
|
|
|
|
+ /* do FIFO LOAD */
|
|
|
|
+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 |
|
|
|
|
+ FIFOLD_TYPE_IFIFO | LDST_VLF);
|
|
|
|
+
|
|
|
|
+ /*
|
|
|
|
+ * if (REG0 > 0)
|
|
|
|
+ * jmp 0xF8 (after shared desc header)
|
|
|
|
+ */
|
|
|
|
+ append_jump(desc, JUMP_TEST_INVALL | JUMP_COND_MATH_N |
|
|
|
|
+ JUMP_COND_MATH_Z | 0xF8);
|
|
|
|
+
|
|
|
|
+ print_hex_dump_debug("caam dma shdesc@" __stringify(__LINE__) ": ",
|
|
|
|
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
|
|
|
|
+ 1);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int caam_dma_probe(struct platform_device *pdev)
|
|
|
|
+{
|
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
|
+ struct device *ctrldev = dev->parent;
|
|
|
|
+ struct dma_chan *chan, *_chan;
|
|
|
|
+ u32 *sh_desc;
|
|
|
|
+ int err = -ENOMEM;
|
|
|
|
+ int bonds;
|
|
|
|
+
|
|
|
|
+ if (!caam_jr_driver_probed()) {
|
|
|
|
+ dev_info(dev, "Defer probing after JR driver probing\n");
|
|
|
|
+ return -EPROBE_DEFER;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ dma_dev = kzalloc(sizeof(*dma_dev), GFP_KERNEL);
|
|
|
|
+ if (!dma_dev)
|
|
|
|
+ return -ENOMEM;
|
|
|
|
+
|
|
|
|
+ dma_sh_desc = kzalloc(sizeof(*dma_sh_desc), GFP_KERNEL | GFP_DMA);
|
|
|
|
+ if (!dma_sh_desc)
|
|
|
|
+ goto desc_err;
|
|
|
|
+
|
|
|
|
+ sh_desc = dma_sh_desc->desc;
|
|
|
|
+ set_caam_dma_desc(sh_desc);
|
|
|
|
+ dma_sh_desc->desc_dma = dma_map_single(ctrldev, sh_desc,
|
|
|
|
+ desc_bytes(sh_desc),
|
|
|
|
+ DMA_TO_DEVICE);
|
|
|
|
+ if (dma_mapping_error(ctrldev, dma_sh_desc->desc_dma)) {
|
|
|
|
+ dev_err(dev, "unable to map dma descriptor\n");
|
|
|
|
+ goto map_err;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ INIT_LIST_HEAD(&dma_dev->channels);
|
|
|
|
+
|
|
|
|
+ bonds = caam_dma_jr_chan_bind();
|
|
|
|
+ if (!bonds) {
|
|
|
|
+ err = -ENODEV;
|
|
|
|
+ goto jr_bind_err;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ dma_dev->dev = dev;
|
|
|
|
+ dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
|
|
|
|
+ dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
|
|
|
|
+ dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
|
|
|
|
+ dma_dev->device_tx_status = dma_cookie_status;
|
|
|
|
+ dma_dev->device_issue_pending = caam_dma_issue_pending;
|
|
|
|
+ dma_dev->device_prep_dma_memcpy = caam_dma_prep_memcpy;
|
|
|
|
+ dma_dev->device_free_chan_resources = caam_dma_free_chan_resources;
|
|
|
|
+
|
|
|
|
+ err = dma_async_device_register(dma_dev);
|
|
|
|
+ if (err) {
|
|
|
|
+ dev_err(dev, "Failed to register CAAM DMA engine\n");
|
|
|
|
+ goto jr_bind_err;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ dev_info(dev, "caam dma support with %d job rings\n", bonds);
|
|
|
|
+
|
|
|
|
+ return err;
|
|
|
|
+
|
|
|
|
+jr_bind_err:
|
|
|
|
+ list_for_each_entry_safe(chan, _chan, &dma_dev->channels, device_node)
|
|
|
|
+ caam_jr_dma_free(chan);
|
|
|
|
+
|
|
|
|
+ dma_unmap_single(ctrldev, dma_sh_desc->desc_dma, desc_bytes(sh_desc),
|
|
|
|
+ DMA_TO_DEVICE);
|
|
|
|
+map_err:
|
|
|
|
+ kfree(dma_sh_desc);
|
|
|
|
+desc_err:
|
|
|
|
+ kfree(dma_dev);
|
|
|
|
+ return err;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int caam_dma_remove(struct platform_device *pdev)
|
|
|
|
+{
|
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
|
+ struct device *ctrldev = dev->parent;
|
|
|
|
+ struct caam_dma_ctx *ctx, *_ctx;
|
|
|
|
+
|
|
|
|
+ dma_async_device_unregister(dma_dev);
|
|
|
|
+
|
|
|
|
+ list_for_each_entry_safe(ctx, _ctx, &dma_ctx_list, node) {
|
|
|
|
+ list_del(&ctx->node);
|
|
|
|
+ caam_jr_free(ctx->jrdev);
|
|
|
|
+ kfree(ctx);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ dma_unmap_single(ctrldev, dma_sh_desc->desc_dma,
|
|
|
|
+ desc_bytes(dma_sh_desc->desc), DMA_TO_DEVICE);
|
|
|
|
+
|
|
|
|
+ kfree(dma_sh_desc);
|
|
|
|
+ kfree(dma_dev);
|
|
|
|
+
|
|
|
|
+ dev_info(dev, "caam dma support disabled\n");
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static struct platform_driver caam_dma_driver = {
|
|
|
|
+ .driver = {
|
|
|
|
+ .name = "caam-dma",
|
|
|
|
+ },
|
|
|
|
+ .probe = caam_dma_probe,
|
|
|
|
+ .remove = caam_dma_remove,
|
|
|
|
+};
|
|
|
|
+module_platform_driver(caam_dma_driver);
|
|
|
|
+
|
|
|
|
+MODULE_LICENSE("Dual BSD/GPL");
|
|
|
|
+MODULE_DESCRIPTION("NXP CAAM support for DMA engine");
|
|
|
|
+MODULE_AUTHOR("NXP Semiconductors");
|
|
|
|
+MODULE_ALIAS("platform:caam-dma");
|