openwrt/target/linux/layerscape/patches-5.4/302-dts-0075-arm64-dts-fsl-ls1028a-Enable-switch-PHYs-on-RDB.patch

From aafb63a926b790b64a5ed83377f07b90ec7ba7c0 Mon Sep 17 00:00:00 2001
From: Claudiu Manoil <claudiu.manoil@nxp.com>
Date: Thu, 20 Jun 2019 19:53:55 +0300
Subject: [PATCH] arm64: dts: fsl: ls1028a: Enable switch PHYs on RDB

Just link the switch PHY nodes to the central MDIO
controller PCIe endpoint node on ls1028 (implemented
as PF3) so that PHYs are configurable via MDIO.

Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 39 +++++++++++++++++++++++
 1 file changed, 39 insertions(+)

--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -208,6 +208,45 @@
 	status = "disabled";
 };
 
+&enetc_mdio_pf3 {
+	qsgmii_phy1: ethernet-phy@4 {
+		reg = <0x10>;
+	};
+
+	qsgmii_phy2: ethernet-phy@5 {
+		reg = <0x11>;
+	};
+
+	qsgmii_phy3: ethernet-phy@6 {
+		reg = <0x12>;
+	};
+
+	qsgmii_phy4: ethernet-phy@7 {
+		reg = <0x13>;
+	};
+};
+
+/* l2switch ports */
+&switch_port0 {
+	phy-handle = <&qsgmii_phy1>;
+	phy-connection-type = "qsgmii";
+};
+
+&switch_port1 {
+	phy-handle = <&qsgmii_phy2>;
+	phy-connection-type = "qsgmii";
+};
+
+&switch_port2 {
+	phy-handle = <&qsgmii_phy3>;
+	phy-connection-type = "qsgmii";
+};
+
+&switch_port3 {
+	phy-handle = <&qsgmii_phy4>;
+	phy-connection-type = "qsgmii";
+};
+
 &sai4 {
 	status = "okay";
 };