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73 lines
2.9 KiB
Diff
73 lines
2.9 KiB
Diff
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From 494c1f9c5c86396d2974c6072f728e2325b72703 Mon Sep 17 00:00:00 2001
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From: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
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Date: Wed, 7 Mar 2018 11:35:07 +0200
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Subject: [PATCH] Sound: Soc: fsl: Set SAI Channel Mode to Output Mode
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Transmit data pins will output zero when slots are masked or channels
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are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when
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slots are masked or channels are disabled. When data pins are tri-stated,
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there is noise on some channels when FS clock value is high and data is
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read while fsclk is transitioning from high to low.
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Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
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Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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---
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sound/soc/fsl/fsl_sai.c | 14 +++++++++++---
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sound/soc/fsl/fsl_sai.h | 2 ++
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2 files changed, 13 insertions(+), 3 deletions(-)
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--- a/sound/soc/fsl/fsl_sai.c
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+++ b/sound/soc/fsl/fsl_sai.c
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@@ -589,6 +589,11 @@ static int fsl_sai_hw_params(struct snd_
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val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
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+ /* Output Mode - data pins transmit 0 when slots are masked
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+ * or channels are disabled
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+ */
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+ val_cr4 |= FSL_SAI_CR4_CHMOD;
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+
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/*
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* For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
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* generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
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@@ -599,14 +604,16 @@ static int fsl_sai_hw_params(struct snd_
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if (!sai->slave_mode[tx]) {
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if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
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regmap_update_bits(sai->regmap, FSL_SAI_TCR4(offset),
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- FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
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+ FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
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+ FSL_SAI_CR4_CHMOD_MASK,
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val_cr4);
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regmap_update_bits(sai->regmap, FSL_SAI_TCR5(offset),
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FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
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FSL_SAI_CR5_FBT_MASK, val_cr5);
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} else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
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regmap_update_bits(sai->regmap, FSL_SAI_RCR4(offset),
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- FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
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+ FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
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+ FSL_SAI_CR4_CHMOD_MASK,
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val_cr4);
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regmap_update_bits(sai->regmap, FSL_SAI_RCR5(offset),
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FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
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@@ -682,7 +689,8 @@ static int fsl_sai_hw_params(struct snd_
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}
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regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, offset),
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- FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
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+ FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
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+ FSL_SAI_CR4_CHMOD_MASK,
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val_cr4);
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regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, offset),
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FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
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--- a/sound/soc/fsl/fsl_sai.h
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+++ b/sound/soc/fsl/fsl_sai.h
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@@ -129,6 +129,8 @@
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#define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
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#define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
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#define FSL_SAI_CR4_SYWD_MASK (0x1f << 8)
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+#define FSL_SAI_CR4_CHMOD (1 << 5)
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+#define FSL_SAI_CR4_CHMOD_MASK (1 << 5)
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#define FSL_SAI_CR4_MF BIT(4)
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#define FSL_SAI_CR4_FSE BIT(3)
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#define FSL_SAI_CR4_FSP BIT(1)
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