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42 lines
1.6 KiB
Diff
42 lines
1.6 KiB
Diff
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From 82b892c3df4893b123681b2ba725c0861e0112a4 Mon Sep 17 00:00:00 2001
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From: Robin Gong <yibin.gong@nxp.com>
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Date: Tue, 13 Mar 2018 02:03:09 +0800
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Subject: [PATCH] MLK-17782 dma: fsl-edma-v3: fix issue reported by Coverity
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Fix below issue reported by Coverity, actually, don't need this
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condition check here, remove it.
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CID undefined (#1 of 1): Wrong operator used (CONSTANT_EXPRESSION_RESULT)operator_confusion:
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(16UL /* 1UL << 4 */) | (__u16)(__le16)tcd->csr is always 1/true regardless of the values of its operand.
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This occurs as the logical first operand of "&&".
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Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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(cherry picked from commit ab942110975cadcde57ab1110df03f526bd3fec5)
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---
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drivers/dma/fsl-edma-v3.c | 6 ++----
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1 file changed, 2 insertions(+), 4 deletions(-)
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--- a/drivers/dma/fsl-edma-v3.c
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+++ b/drivers/dma/fsl-edma-v3.c
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@@ -1,7 +1,7 @@
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/*
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* drivers/dma/fsl-edma3-v3.c
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*
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- * Copyright 2017 NXP .
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+ * Copyright 2017-2018 NXP .
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*
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* Driver for the Freescale eDMA engine v3. This driver based on fsl-edma3.c
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* but changed to meet the IP change on i.MX8QM: every dma channel is specific
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@@ -451,9 +451,7 @@ static void fsl_edma3_set_tcd_regs(struc
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writel(le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA);
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/* Must clear CHa_CSR[DONE] bit before enable TCDa_CSR[ESG] */
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- if ((EDMA_TCD_CSR_E_SG | le16_to_cpu(tcd->csr)) &&
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- EDMA_CH_CSR_DONE | readl(addr + EDMA_CH_CSR))
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- writel(EDMA_CH_CSR_DONE, addr + EDMA_CH_CSR);
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+ writel(readl(addr + EDMA_CH_CSR), addr + EDMA_CH_CSR);
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writew(le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR);
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}
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