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60 lines
2.3 KiB
Diff
60 lines
2.3 KiB
Diff
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From 060265cd3cec354804c0c944e42de83cec9f2f2a Mon Sep 17 00:00:00 2001
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From: Mihai Serban <mihai.serban@nxp.com>
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Date: Fri, 21 Apr 2017 15:57:58 +0300
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Subject: [PATCH] MLK-14847: Revert "ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI
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master mode"
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This reverts commit c768ed336bba ("ASoC: fsl-sai: set xCR4/xCR5/xMR for
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SAI master mode")
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This change was already introduced by commit 51659ca069ce ("ASoC: fsl-sai:
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set xCR4/xCR5/xMR for SAI master mode") from upstream.
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Manually adjust the code to match the changes introduced by subsequent
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commit b2936555bb38 ("MLK-13609: ASoC: fsl_sai: fix for synchronize mode")
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by removing updates to FSL_SAI_TMR/FSL_SAI_RMR registers.
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Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
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---
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sound/soc/fsl/fsl_sai.c | 29 -----------------------------
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1 file changed, 29 deletions(-)
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--- a/sound/soc/fsl/fsl_sai.c
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+++ b/sound/soc/fsl/fsl_sai.c
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@@ -507,35 +507,6 @@ static int fsl_sai_hw_params(struct snd_
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regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
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FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
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FSL_SAI_CR5_FBT_MASK, val_cr5);
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- regmap_write(sai->regmap, FSL_SAI_TMR,
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- ~0UL - ((1 << channels) - 1));
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- } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
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- regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
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- FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
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- val_cr4);
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- regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
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- FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
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- FSL_SAI_CR5_FBT_MASK, val_cr5);
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- regmap_write(sai->regmap, FSL_SAI_RMR,
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- ~0UL - ((1 << channels) - 1));
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- }
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- }
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-
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- /*
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- * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
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- * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
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- * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
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- * error.
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- */
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-
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- if (!sai->slave_mode[tx]) {
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- if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
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- regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
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- FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
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- val_cr4);
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- regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
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- FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
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- FSL_SAI_CR5_FBT_MASK, val_cr5);
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} else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
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regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
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FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
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