openwrt/target/linux/mvebu/cortexa9/target.mk

#
# Copyright (C) 2017 Hauke Mehrtens
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#

include $(TOPDIR)/rules.mk

ARCH:=arm
BOARDNAME:=Marvell Armada 37x/38x/XP
CPU_TYPE:=cortex-a9
CPU_SUBTYPE:=vfpv3-d16
KERNELNAME:=zImage dtbs
mvebu: Add subtarget for Cortex A9 build This is in preparation for adding a subtarget for the Cortex A53 later. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> 2018-03-07 22:10:01 +01:00			`#`
			`# Copyright (C) 2017 Hauke Mehrtens`
			`#`
			`# This is free software, licensed under the GNU General Public License v2.`
			`# See /LICENSE for more information.`
			`#`

			`include $(TOPDIR)/rules.mk`

			`ARCH:=arm`
			`BOARDNAME:=Marvell Armada 37x/38x/XP`
			`CPU_TYPE:=cortex-a9`
mvebu: cortexa9: correct cpu subtype Armada 370 processors have only 16 double-precision registers. The change introduced by 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") switched accidentally the toolchain for mvebu cortexa9 subtarget to cpu type with 32 double-precision registers. This stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That change resulted in unusable image, in which kernel will kill userspace as soon as it causing "Illegal instruction". Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272 Fixes: 8dcc1087602e ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl> 2020-03-18 19:04:12 +01:00			`CPU_SUBTYPE:=vfpv3-d16`
mvebu: Add subtarget for Cortex A9 build This is in preparation for adding a subtarget for the Cortex A53 later. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> 2018-03-07 22:10:01 +01:00			`KERNELNAME:=zImage dtbs`