Xianjun Jiao f71252c537 iq capture feature		2020-10-19 10:13:51 +02:00
..
ad9361	prepare upgrade	2020-04-27 09:37:04 +02:00
openofdm_rx	update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing	2020-06-12 10:50:34 +02:00
openofdm_tx	update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing	2020-06-12 10:50:34 +02:00
rx_intf	update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing	2020-06-12 10:50:34 +02:00
side_ch	iq capture feature	2020-10-19 10:13:51 +02:00
tx_intf	the side channel (timestamp, frequency offset, CSI, equalizer) feature	2020-10-08 15:07:57 +02:00
xilinx_dma	sync master (#21)	2020-06-11 15:50:12 +02:00
xpu	update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing	2020-06-12 10:50:34 +02:00
hw_def.h	update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing	2020-06-12 10:50:34 +02:00
make_all.sh	add recent update:	2020-09-04 10:57:04 +02:00
Makefile	prepare upgrade	2020-04-27 09:37:04 +02:00
sdr.c	the side channel (timestamp, frequency offset, CSI, equalizer) feature	2020-10-08 15:07:57 +02:00
sdr.h	the side channel (timestamp, frequency offset, CSI, equalizer) feature	2020-10-08 15:07:57 +02:00