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Author	SHA1	Message	Date
Xianjun Jiao	c491759016	Re-calibrate the ACK timing after merging LLR	2025-04-17 16:17:22 +02:00
Xianjun Jiao	478ee06a4e	Add scripts and update README to ease: ... transfer kernel/devicetree/fpga/driver on board	2025-04-17 16:17:22 +02:00
Xianjun Jiao	fc0eb1fd2a	Necessary changes for ADI Linux kernel 2022_R2	2025-04-17 16:17:22 +02:00
thavinga	70cb2fa99f	Update device trees for optimized AGC settings	2025-04-17 16:17:22 +02:00
thavinga	e4ed4a34a8	Update ADI kernel patches for missing AGC setting	2025-04-17 16:17:22 +02:00
thavinga	3f266966d6	Add note about enabling statistics before rx_gain_show.sh	2025-04-17 16:17:22 +02:00
thavinga	ef5722e6ac	Add driver info to git info	2025-04-17 16:17:22 +02:00
thavinga	08c886eae1	Add option to give file postfix for drv_and_fpga_package_gen.sh	2025-04-17 16:17:22 +02:00
Xianjun Jiao	30b492d3aa	Make ack timing work with tx_control_state 5: ... RECV_ACK_WAIT_SIG_VALID	2025-04-17 16:17:22 +02:00
thavinga	30db65945b	Unwrap each CSI vector in the matrix separately	2025-04-17 16:17:22 +02:00
thavinga	c7ce4b2bfc	Side info display: unwrap phase, set DC to 0	2025-04-17 16:17:22 +02:00
Xianjun Jiao	d16217b7aa	Swap positon of phy_hdr_config and tx_config: ... to align better with 80211ax driver	2025-04-17 16:17:22 +02:00
Xianjun Jiao	fb4cc3e54d	improve (force)use_cts_protect code efficiency	2025-04-17 16:17:22 +02:00
Xianjun Jiao	380eec74e8	improve the LARGE/SMALL_FPGA detection in driver	2025-04-17 16:17:22 +02:00
Xianjun Jiao	77769f9dcb	change some u16 to u8	2025-04-17 16:17:22 +02:00
Xianjun Jiao	bb3e53ba4d	add short gi config into driver test_mode argument	2025-04-17 16:17:22 +02:00
Xianjun Jiao	3b510cfa8a	Update side_ch scripts for this discussion: ... https://github.com/open-sdr/openwifi/discussions/344	2025-04-17 16:17:22 +02:00
Xianjun Jiao	8f959713dc	Improve the ACK gap calculation parameter	2025-04-17 16:17:22 +02:00
Xianjun Jiao	a424d7bb3b	Add timestamp as return argument of .m	2025-04-17 16:17:22 +02:00
Xianjun Jiao	b01c227660	Change the ACK tx timing in xpu driver: ... according to the ACK timing analysis results of HT	2025-04-17 16:17:22 +02:00
Xianjun Jiao	cfc73a3359	Add Matlab script for ACK timing analysis	2025-04-17 16:17:22 +02:00
Xianjun Jiao	bd3f48f407	Change the default data type to uint16	2025-04-17 16:17:22 +02:00
thavinga	4cfdc1c47c	Update prepare_kernel to ignore warning in mac80211	2025-04-17 16:17:22 +02:00
Wei Liu	b102ce3460	write Fc to lower 16 bit of XPU_REG_BAND_CHANNEL register	2025-04-17 16:17:22 +02:00
Jiao Xianjun	2433d43ded	Add CSI fuzzer counter attack paper.	2025-03-21 20:47:50 +01:00
Jiao Xianjun	653e3eed2b	Add TWT survey paper	2025-03-19 08:37:31 +01:00
Jiao Xianjun	b3bfd95b39	Jesus A. Armenta-Garcia sensing survey paper	2025-03-12 11:08:51 +01:00
Jiao Xianjun	19e2e96f87	Add Tianyu testbed survey paper	2025-03-12 11:05:38 +01:00
Jiao Xianjun	e46ef8cb3c	Add Hao Zhou LLM for telecomm paper.	2025-03-12 09:42:40 +01:00
Jiao Xianjun	8aadf2e653	Add Renato secure Wi-Fi sensing paper	2025-03-12 09:39:58 +01:00
Jiao Xianjun	70c0f75117	Add Yongchao openwifi RIC TSN paper	2025-03-12 09:32:31 +01:00
Jiao Xianjun	93c2fbb0d5	Add Louis openwifi UWB high res sync paper	2025-03-12 09:26:02 +01:00
Jiao Xianjun	c373780c69	Add Thijs Wi-Fi6 OFDMA paper	2025-03-12 09:20:55 +01:00
Jiao Xianjun	0be9a3dcbf	Add JC&S 2025 WiFi sensing paper	2025-03-12 09:13:34 +01:00
Xianjun Jiao	030b3f45eb	Fix the csi fuzzer CIR: ... Due to FPGA implementation, there CIR actually is [1, 0, c1, c2], not [1, c1, c2]	2025-01-14 09:55:37 +01:00
Xianjun Jiao	2b9eb82fa9	Fix the csi fuzzer CIR: ... Due to FPGA implementation, there CIR actually is [1, 0, c1, c2], not [1, c1, c2]	2025-01-08 10:36:12 +01:00
Jiao Xianjun	9fd3eee8b3	Add new CSI fuzzer paper into publications.	2025-01-06 09:05:00 +01:00
Jiao Xianjun	40bf1ed929	Add new CSI fuzzer work into app note.	2025-01-06 09:02:22 +01:00
Jiao Xianjun	a80935dc8b	Link block diagram of Andreas EPFL paper	2024-12-15 11:07:59 +01:00
Jiao Xianjun	ebc1ea77cb	Add block diagram for Andreas EPFL paper	2024-12-15 11:06:25 +01:00
Jiao Xianjun	66f1f8fdfe	Add Andreas AnSIC sensing paper	2024-12-14 10:13:01 +01:00
Jiao Xianjun	239ba79d1b	Add Aalto University master thesis	2024-11-24 13:42:41 +01:00
Jiao Xianjun	9c8cd6a384	Add Analog Devices, AN-2597: ... UAV video streaming.	2024-11-24 13:37:11 +01:00
Jiao Xianjun	0e92239b77	Update publications.md arxiv -> PIMRC	2024-11-04 13:45:34 +01:00
Jiao Xianjun	00a0adebb8	Add BW estimation ICCC23 paper	2024-09-20 16:53:48 +02:00
Jiao Xianjun	56d315f74d	Add Breathing Rate Sensing paper	2024-09-19 13:32:43 +02:00
Jiao Xianjun	6c1beb29ad	Add Jetmir paper	2024-09-04 10:37:48 +02:00
Jiao Xianjun	4c6df84e62	Add Jetmir paper	2024-09-04 10:36:13 +02:00
Jiao Xianjun	0be84898dd	Add Gilson paper	2024-09-04 10:31:28 +02:00
Jiao Xianjun	179be870f9	Add Jetmir paper	2024-09-04 10:28:15 +02:00