5 Commits

Author	SHA1	Message	Date
Xianjun Jiao	22dd0cc486	the side channel (timestamp, frequency offset, CSI, equalizer) feature	2020-10-08 15:07:57 +02:00
Xianjun Jiao	838a9007cf	update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing	2020-06-12 10:50:34 +02:00
Xianjun Jiao	febc5adf73	prepare upgrade	2020-04-27 09:37:04 +02:00
Xianjun Jiao	b73660ad79	prepare for release	2020-03-04 19:39:12 +01:00
Xianjun Jiao	2ee6717882	initial commit	2019-12-10 14:03:47 +01:00