6 Commits

Author	SHA1	Message	Date
Xianjun Jiao	f71252c537	iq capture feature	2020-10-19 10:13:51 +02:00
Xianjun Jiao	22dd0cc486	the side channel (timestamp, frequency offset, CSI, equalizer) feature	2020-10-08 15:07:57 +02:00
Xianjun Jiao	0a92505df2	add recent update: ... 1. add git revision software register 7 to DRV_XPU module (not FPGA XPU module) 2. fix the print of hdr->seq_ctrl in sdr.c 3. add ht_flag display to sdr.c 4. remove the sysid from devicetree because new we have our own git revision read back solution in FPGA (XPU register 63) and driver (the sotware register 7 of drv_xpu) 5. add sudo to update_sdcard.sh to make the image generation without SD card in the test-bed easier	2020-09-04 10:57:04 +02:00
Xianjun Jiao	8a6507ded8	add dtb. because they will not be changed frequently	2020-07-01 09:40:33 +02:00
Xianjun Jiao	febc5adf73	prepare upgrade	2020-04-27 09:37:04 +02:00
Xianjun Jiao	b73660ad79	prepare for release	2020-03-04 19:39:12 +01:00