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3 Commits

Author SHA1 Message Date
Xianjun Jiao
aaceb807fd Add sysfs to support xpu reg 6 bit27 26: 
bit27 to disable eifs triggered by last rx fail
bit26 to disable eifs triggered by last tx fail
 2023-02-27 19:56:32 +01:00
Xianjun Jiao
6bb9ef71e9 Example of how to add debug channel via sysfs and access it via script --> driver 2022-03-29 15:18:55 +02:00
Xianjun Jiao
61a639784b Add sysfs file based driver/FPGA access interface 2022-03-28 12:46:49 +02:00