Refactor according to ...

Some xpu registers are removed
This commit is contained in:
Xianjun Jiao 2023-01-17 13:22:17 +01:00
parent d4c3d8108e
commit 6c6cf95190

View File

@ -324,26 +324,11 @@ const char *xpu_compatible_str = "sdr,xpu";
#define XPU_REG_MAC_ADDR_LOW_ADDR (30*4) #define XPU_REG_MAC_ADDR_LOW_ADDR (30*4)
#define XPU_REG_MAC_ADDR_HIGH_ADDR (31*4) #define XPU_REG_MAC_ADDR_HIGH_ADDR (31*4)
#define XPU_REG_FC_DI_ADDR (34*4)
#define XPU_REG_ADDR1_LOW_ADDR (35*4)
#define XPU_REG_ADDR1_HIGH_ADDR (36*4)
#define XPU_REG_ADDR2_LOW_ADDR (37*4)
#define XPU_REG_ADDR2_HIGH_ADDR (38*4)
#define XPU_REG_ADDR3_LOW_ADDR (39*4)
#define XPU_REG_ADDR3_HIGH_ADDR (40*4)
#define XPU_REG_SC_LOW_ADDR (41*4)
#define XPU_REG_ADDR4_HIGH_ADDR (42*4)
#define XPU_REG_ADDR4_LOW_ADDR (43*4)
#define XPU_REG_TRX_STATUS_ADDR (50*4)
#define XPU_REG_TX_RESULT_ADDR (51*4)
#define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR (58*4) #define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR (58*4)
#define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4) #define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4)
#define XPU_REG_RSSI_HALF_DB_ADDR (60*4) #define XPU_REG_MAC_ADDR_READ_BACK_ADDR (62*4)
#define XPU_REG_IQ_RSSI_HALF_DB_ADDR (61*4) #define XPU_REG_FPGA_GIT_REV_ADDR (63*4)
enum xpu_mode { enum xpu_mode {
XPU_TEST = 0, XPU_TEST = 0,