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GNU AFFERO GENERAL PUBLIC LICENSE
Version 3, 19 November 2007
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
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Preamble
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The license terms used for the scard class (in pcsc_usim) derived from wpa_supplicant
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3. Neither the name(s) of the above-listed copyright holder(s) nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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# openwifi # openwifi
Free open source Wi-Fi project <img src="./openwifi-arch.jpg" width="900">
**openwifi:** Linux mac80211 compatiable full-stack Wi-Fi design based on SDR (Software Defined Radio).
This repository includes Linux driver and software. [openwifi-hw](https://github.ugent.be/xjiao/openwifi-hw) repository has the FPGA design. [[Detailed architecture](https://github.ugent.be/xjiao/openwifi/tree/master/doc)]
[Demo [video](https://drive.google.com/file/d/1Qk-MEHkK_9yL_KPv--4MCJhLoGzE2N5W/view?usp=sharing)]. [openwifi [maillist](https://lists.ugent.be/wws/subscribe/openwifi)]
Openwifi code has dual licenses. AGPLv3 is the opensource license. For non-opensource license, please contact Filip.Louagie@UGent.be. Openwifi project also leverages some 3rd party modules. It is your duty to check and follow licenses of those modules according to your purpose. You can find [an example explanation from Analog Devices](https://github.com/analogdevicesinc/hdl/blob/master/LICENSE) for this compound license conditions.
Openwifi was born in [ORCA project](https://www.orca-project.eu/) (EU's Horizon2020 programme under agreement number 732174).
**Features:**
* 802.11a/g; 802.11n MCS 0~7; 20MHz
* Mode tested: Ad-hoc; Station; AP
* DCF (CSMA/CA) low MAC layer in FPGA
* Configurable channel access priority parameters:
* duration of RTS/CTS, CTS-to-self
* SIFS/DIFS/xIFS/slot-time/CW/etc
* Time slicing based on MAC address
* Easy to change bandwidth and frequency:
* 2MHz for 802.11ah in sub-GHz
* 10MHz for 802.11p/vehicle in 5.9GHz
* On roadmap: **802.11ax**
**Performance (AP: openwifi at channel 44, client: TL-WDN4200 N900 Wireless Dual Band USB Adapter. iperf test):**
* AP --> client: 30.6Mbps(TCP), 38.8Mbps(UDP)
* client --> AP: 17.0Mbps(TCP), 21.5Mbps(UDP)
**Supported SDR platforms:**
* zc706 (Xilinx) + fmcomms2 (Analog Devices)
* On roadmap: ADRV9361-Z7035/ADRV9364-Z7020 + ADRV1CRR-BOB (Analog Devices)
* On roadmap: zcu102 (Xilinx) + fmcomms2/ADRV9371 (Analog Devices)
* Don't have any boards? Or you like JTAG boot instead of SD card? Check our test bed [w-iLab.t](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html) tutorial.
**Quick start:** (Example instructions are verified on Ubuntu 16/18)
* Download pre-built [openwifi Linux img file](https://users.ugent.be/~xjiao/). Burn the img file to a 16G SD card:
```
sudo dd bs=4M if=openwifi-zc706-v000.img of=/dev/mmcblk0
(mmcblk0 is the dev name of sdcard in Linux. Make sure you use the correct one in your situation!)
(Above command takes a while)
```
* Connect RX/TX antenna to RX1A/TX2A ports of your zc706+fmcomms2 platform, and make two antennas orthogonal to each other for good isolation. Config zc706 to SD card boot mode by switches (Read zc706 board spec on internet). Insert the SD card to zc706.
* Connect the board to PC. (PC IP address should be 192.168.10.1). Power on the board. Then from PC:
```
ssh root@192.168.10.122
(password: openwifi)
cd openwifi
service network-manager stop
./wgd.sh
ifconfig sdr0 up
iwlist sdr0 scan
(you should see the Wi-Fi scan result)
```
* Setup openwifi hotspot over topology: client -- (sdr0)|zc706|(eth0) -- (***ethX***)|PC|(***ethY***) -- internet
* Enable IPv4 IP forwarding on both zc706 and PC
* Then, on board:
ifconfig sdr0 192.168.13.1
route add default gw 192.168.10.1
service isc-dhcp-server restart
hostapd hostapd-openwifi.conf
* Then, on PC:
sudo iptables -t nat -A POSTROUTING -o ethY -j MASQUERADE
sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX
* Now you can connect openwifi by your devices (phone, laptop, etc)
* Connect openwifi to another hotspot. Terminate hostapd, edit wpa-connect.conf properly, then:
./wgd.sh
route del default gw 192.168.10.1
wpa_supplicant -i sdr0 -c wpa-connect.conf
(Wait for connection done, then open another ssh terminal)
dhclient sdr0
(Wait for its donw, then you should have connection)
* ***Note***: If openwifi stops working after ~2 hours, it means the evaluation license of Xilinx Viterbi decoder has expired. You need to power cycle the board. Run this command several times on board to confirm:
root@analog:~/openwifi# ./sdrctl dev sdr0 get reg rx 20
SENDaddr: 00040050
reg val: 34be0123
(If the last number of reg val is always 3, that means the Viterbi decoder stops working)
* Real-time control/config via sdrctl (time slice config, etc), please find the [doc](https://github.ugent.be/xjiao/openwifi/tree/master/doc).
**Build openwifi Linux img based on openwifi FPGA and driver:**
* Install Vivado/SDK 2017.4.1.
* Get necessary FPGA files from openwifi-hw repository.
```
git submodule init openwifi-hw
git submodule update openwifi-hw
cd openwifi-hw
git pull
```
* Build Linux kernel and modules:
```
export XILINX_DIR=your_Xilinx_directory
cd openwifi
git submodule init adi-linux
git submodule update adi-linux
(Will take a while)
cd adi-linux
git reset --hard 4220d5d24c6c7589fc702db4f941f0632b5ad767
cp ../kernel_boot/kernel_config ./.config
source $XILINX_DIR/SDK/2017.4/settings64.sh
export ARCH=arm
export CROSS_COMPILE=arm-linux-gnueabihf-
make -j12 UIMAGE_LOADADDR=0x8000 uImage
(Answer "y" to Xilinx DMA Engines (XILINX_DMA_ENGINES) [N/y/?] (NEW))
make modules
```
* Build openwifi Linux driver modules:
```
export OPENWIFI_DIR=your_openwifi_directory
cd $OPENWIFI_DIR/driver
./make_all.sh $XILINX_DIR/SDK/2017.4/ $OPENWIFI_DIR/adi-linux/
```
* Build openwifi Linux devicetree:
```
cd $OPENWIFI_DIR/kernel_boot
dtc -I dts -O dtb -o devicetree.dtb devicetree.dts
```
* Build openwifi BOOT.BIN based on FPGA files generated in openwifi-hw:
```
cd $OPENWIFI_DIR/kernel_boot
source $XILINX_DIR/Vivado/2017.4/settings64.sh
./build_boot_bin.sh ../openwifi-hw/zc706_fmcs2/sdk/system_top_hw_platform_0/system.hdf u-boot-zc70x.elf
(u-boot-zc70x.elf is included in the original Analog Devices Linux img)
```
* Download [2017_R1-2018_01_29.img.xz](http://swdownloads.analog.com/cse/2017_R1-2018_01_29.img.xz) from [Analog Devices Wiki](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images). Burn it into a SD card via your PC.
* Mount SD card BOOT/rootfs partitions to SDCARD_DIR directory of your PC (If it is mounted automatically, find the directory). Then copy built files to SD card via your PC. (You can also update files over ftp/ssh after your full system runs. Please check user_space/sdcard_boot_update.sh and set your ftp root directory to openwifi repository in your PC):
```
export SDCARD_DIR=sdcard_mount_point
cp $OPENWIFI_DIR/kernel_boot/devicetree.dtb $SDCARD_DIR/BOOT
cp $OPENWIFI_DIR/kernel_boot/output_boot_bin/BOOT.BIN $SDCARD_DIR/BOOT
cp $OPENWIFI_DIR/adi-linux/arch/arm/boot/uImage $SDCARD_DIR/BOOT
cd $SDCARD_DIR/BOOT
sync
sudo mkdir $SDCARD_DIR/rootfs/root/openwifi
sudo find $OPENWIFI_DIR/driver -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/root/openwifi/ \;
sudo cp $OPENWIFI_DIR/user_space/* $SDCARD_DIR/rootfs/root/openwifi/
sudo mkdir $SDCARD_DIR/rootfs/lib/modules
sudo mkdir $SDCARD_DIR/rootfs/lib/modules/4.14.0-g4220d5d24c6c
sudo find $OPENWIFI_DIR/adi-linux -name \*.ko -exec cp {} $SDCARD_DIR/rootfs/lib/modules/4.14.0-g4220d5d24c6c/ \;
sudo rm $SDCARD_DIR/rootfs/lib/modules/4.14.0-g4220d5d24c6c/{axidmatest.ko,xilinx_dma.ko,adi_axi_hdmi.ko,ad9361_drv.ko} -f
sudo rm $SDCARD_DIR/rootfs/etc/udev/rules.d/70-persistent-net.rules
sudo cp $OPENWIFI_DIR/kernel_boot/70-persistent-net.rules $SDCARD_DIR/rootfs/etc/udev/rules.d/
(Above rule will auto-rename wlan0 to sdr0 which is the openwifi NIC name)
cd $SDCARD_DIR/rootfs
sync
```
**Run Linux and do some post-config:**
* Insert the SD card to the board, power on and run serial console (such as minicom) from a PC via USB-UART cable to the board. After booting completes, in the PC serial console:
```
ln -s /lib/modules/4.14.0-g4220d5d24c6c /lib/modules/4.14.0-g4220d5d
(in case some Linux use short hash)
depmod
(Ignore the error messages)
modprobe mac80211
cd openwifi
./wgd.sh
(Wait for the completion)
ifconfig
(You should see sdr0 interface)
iwlist sdr0 scan
(You should see the Wi-Fi scan results)
```
* Config ssh server and ethernet IP address of the board. In the PC serial console:
```
passwd
(ssh server needs a password, such as "openwifi")
Add "UseDNS no" to /etc/ssh/sshd_config, otherwise ssh login takes too long time
Set static IP to board (If you have DHCP server on PC, you can skip this step)
Add following content to /etc/network/interfaces
auto lo eth0
iface lo inet loopback
iface eth0 inet static
address 192.168.10.122
netmask 255.255.255.0
Add following content to /etc/resolv.conf
nameserver 8.8.8.8
nameserver 4.4.4.4
Disable update (long time hang) on boot or ssh session:
sudo chmod -x /etc/update-motd.d/90-updates-available
sudo chmod -x /etc/update-motd.d/91-release-upgrade
reboot the board, and set proper IP of the connected PC, then from the PC:
ssh roo@192.168.10.122
(password: openwifi)
Access the board disk from PC: Ubuntu "File manager --> Connect to Server...", input: sftp://root@192.168.10.122/root
./wgd.sh remote
(Above command updates files from your PC and brings up sdr0. Make sure set ftp root directory to openwifi repository in your PC)
```
**Compile user_space/sdrctl_src on the board** ("On the board" means that you login to the board via ssh)
```
sudo apt-get install libnl-3-dev
sudo apt-get install libnl-genl-3-dev
(or find out .deb files by above commands and copy .deb to the board, if you do not have internet)
copy user_space/sdrctl_src to the board, then on the board:
cd sdrctl_src
chmod +x version.sh
make
```
**Internet config**
* Topology: client -- (sdr0)|zc706|(eth0) -- (***ethX***)|PC|(***ethY***) -- internet
* Enable IPv4 IP forwarding on both zc706 and PC
* On PC. After this your board should have internet via NAT through your PC.
```
sudo iptables -t nat -A POSTROUTING -o ethY -j MASQUERADE
```
* On board: Install dhcp server preparing for serving your openwifi clients via hostapd.
```
sudo apt-get install isc-dhcp-server
sudo apt-get install Haveged
```
* Put user_space/dhcpd.conf into (overwrite) /etc/dhcp/dhcpd.conf on board.
* On board:
```
cd openwifi
service network-manager stop
./wgd.sh
ifconfig sdr0 up
ifconfig sdr0 192.168.13.1
route add default gw 192.168.10.1
service isc-dhcp-server restart
hostapd hostapd-openwifi.conf
```
* On PC:
```
sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX
```
* Now you can connect openwifi hotspot from your phone/laptop and access internet.

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# openwifi domument
<img src="./openwifi-detail.jpg" width="1100">
Above figure shows software and hardware/FPGA modules that compose the openwifi design. The module name is equal/similar to the source code file name. Driver modules source code are in openwifi/driver/. FPGA modules source code are in openwifi-hw repository. The user space tool sdrctl source code are in openwifi/user_space/sdrctl_src/.
**sdrctl command**
Besides the Linux native Wi-Fi control programs, such as ifconfig/iw/iwconfig/iwlist/wpa_supplicant/hostapd/etc, openwifi offers a user space tool sdrctl to access openwifi specific functionalities. sdrctl is implemented as nl80211 testmode command and communicates with openwifi driver (function openwifi_testmode_cmd in sdr.c) via Linux nl80211--cfg80211--mac80211 path
* **get and set a parameter**
```
sdrctl dev sdr0 get para_name
sdrctl dev sdr0 set para_name value
```
para_name|meaning|example
---------|-------|----
addr0|target MAC addres of tx slice 0|32bit. for address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
slice_total0|tx slice 0 cycle length in us|for length 50ms, you set 49999
slice_start0|tx slice 0 cycle start time in us|for start at 10ms, you set 10000
slice_end0| tx slice 0 cycle end time in us|for end at 40ms, you set 39999
addr1|target MAC addres of tx slice 1|32bit. for address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
slice_total1|tx slice 1 cycle length in us|for length 50ms, you set 49999
slice_start1|tx slice 1 cycle start time in us|for start at 10ms, you set 10000
slice_end1| tx slice 1 cycle end time in us|for end at 40ms, you set 39999
* **get and set a register of a module**
```
sdrctl dev sdr0 get reg module_name reg_idx
sdrctl dev sdr0 set reg module_name reg_idx reg_value
```
module_name drv_rx/drv_tx/drv_xpu refer to driver modules. Related registers are defined in sdr.h (drv_rx_reg_val/drv_tx_reg_val/drv_xpu_reg_val)
module_name rf/rx_intf/tx_intf/rx/tx/xpu refer to RF (ad9xxx front-end) and FPGA (rx_intf/tx_intf/openofdm_rx/openofdm_tx/xpu) modules. Related register addresses are defined in hw_def.h.
module_name: drv_rx
reg_idx|meaning|example
-------|-------|----
1|rx antenna selection|0:rx1, 1:rx2. After this command, you should down and up sdr0 by ifconfig, but not reload sdr0 driver via ./wgd.sh
module_name: drv_tx
reg_idx|meaning|example
-------|-------|----
0|override Linux rate control of tx unicast data packet|4:6M, 5:9M, 6:12M, 7:18M, 8:24M, 9:36M, 10:48M, 11:54M
1|tx antenna selection|0:tx1, 1:tx2. After this command, you should down and up sdr0 by ifconfig, but not reload sdr0 driver via ./wgd.sh
module_name: drv_xpu
reg_idx|meaning|example
-------|-------|----
x|x|x
module_name: rf
reg_idx|meaning|example
-------|-------|----
x|x|x
module_name: rx_intf
reg_idx|meaning|example
-------|-------|----
2|enable/disable rx interrupt|256(0x100):disable, 0:enable
module_name: tx_intf
reg_idx|meaning|example
-------|-------|----
13|tx I/Q digital gain before DUC|current optimal value: 237
14|enable/disable tx interrupt|196672(0x30040):disable, 64(0x40):enable
module_name: rx
reg_idx|meaning|example
-------|-------|----
20|history of PHY rx state|read only. If the last digit readback is always 3, it means the Viterbi decoder stops working
module_name: tx
reg_idx|meaning|example
-------|-------|----
1|pilot scrambler initial state|lowest 7 bits are used. 0x7E by default in openofdm_tx.c
2|data scrambler initial state|lowest 7 bits are used. 0x7F by default in openofdm_tx.c
module_name: xpu
reg_idx|meaning|example
-------|-------|----
2|TSF timer low 32bit write|only write this register won't trigger the TSF timer reload. should use together with register for high 32bit
3|TSF timer high 32bit write|falling edge of MSB will trigger the TSF timer reload, which means write '1' then '0' to MSB
4|band and channel number setting|see enum openwifi_band in hw_def.h. it will be set automatically by Linux. normally you shouldn't set it
11|max number of retransmission in FPGA|normally number of retransmission controled by Linux in real-time. If you write non-zeros value to this register, it will override Linux real-time setting
19|CSMA enable/disable|3758096384(0xe0000000): disable, 3:enable
20|tx slice 0 cycle length in us|for length 50ms, you set 49999
21|tx slice 0 cycle start time in us|for start at 10ms, you set 10000
22|tx slice 0 cycle end time in us|for end at 40ms, you set 39999
23|tx slice 1 cycle length in us|for length 50ms, you set 49999
24|tx slice 1 cycle start time in us|for start at 10ms, you set 10000
25|tx slice 1 cycle end time in us|for end at 40ms, you set 39999
27|FPGA packet filter config|check openwifi_configure_filter in sdr.c. also: https://www.kernel.org/doc/html/v4.9/80211/mac80211.html#frame-filtering
28|BSSID address low 32bit for BSSID filtering|normally it is set by Linux in real-time automatically
29|BSSID address high 32bit for BSSID filtering|normally it is set by Linux in real-time automatically
30|openwifi MAC address low 32bit|
31|openwifi MAC address high 32bit|check XPU_REG_MAC_ADDR_write in sdr.c to see how we set MAC address to FPGA when NIC start
58|TSF runtime value low 32bit|read only
59|TSF runtime value high 32bit|read only

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# Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += sdr.o
all:
make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order

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# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
ad9361_drv-y := ad9361.o ad9361_conv.o
obj-m += ad9361_drv.o
all:
make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order

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/*
* AD9361
*
* Copyright 2013-2018 Analog Devices Inc.
*
* Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
* Licensed under the GPL-2.
*/
#ifndef IIO_FREQUENCY_AD9361_H_
#define IIO_FREQUENCY_AD9361_H_
//#define IIO_AD9361_USE_PRIVATE_H_
#include "ad9361_regs.h"
//#include "ad9361_private.h"
enum ad9361_clocks {
BB_REFCLK,
RX_REFCLK,
TX_REFCLK,
BBPLL_CLK,
ADC_CLK,
R2_CLK,
R1_CLK,
CLKRF_CLK,
RX_SAMPL_CLK,
DAC_CLK,
T2_CLK,
T1_CLK,
CLKTF_CLK,
TX_SAMPL_CLK,
RX_RFPLL_INT,
TX_RFPLL_INT,
RX_RFPLL_DUMMY,
TX_RFPLL_DUMMY,
RX_RFPLL,
TX_RFPLL,
NUM_AD9361_CLKS,
};
enum debugfs_cmd {
DBGFS_NONE,
DBGFS_INIT,
DBGFS_LOOPBACK,
DBGFS_BIST_PRBS,
DBGFS_BIST_TONE,
DBGFS_BIST_DT_ANALYSIS,
DBGFS_RXGAIN_1,
DBGFS_RXGAIN_2,
DBGFS_MCS,
DBGFS_CAL_SW_CTRL,
DBGFS_DIGITAL_TUNE,
};
enum dig_tune_flags {
BE_VERBOSE = 1,
BE_MOREVERBOSE = 2,
DO_IDELAY = 4,
DO_ODELAY = 8,
SKIP_STORE_RESULT = 16,
RESTORE_DEFAULT = 32,
};
enum ad9361_bist_mode {
BIST_DISABLE,
BIST_INJ_TX,
BIST_INJ_RX,
};
enum {
ID_AD9361,
ID_AD9364,
ID_AD9361_2,
ID_AD9363A,
};
enum rx_port_sel {
RX_A_BALANCED, /* 0 = (RX1A_N & RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */
RX_B_BALANCED, /* 1 = (RX1B_N & RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced */
RX_C_BALANCED, /* 2 = (RX1C_N & RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced */
RX_A_N, /* 3 = RX1A_N and RX2A_N enabled; unbalanced */
RX_A_P, /* 4 = RX1A_P and RX2A_P enabled; unbalanced */
RX_B_N, /* 5 = RX1B_N and RX2B_N enabled; unbalanced */
RX_B_P, /* 6 = RX1B_P and RX2B_P enabled; unbalanced */
RX_C_N, /* 7 = RX1C_N and RX2C_N enabled; unbalanced */
RX_C_P, /* 8 = RX1C_P and RX2C_P enabled; unbalanced */
TX_MON1, /* 9 = TX_MON1 enabled */
TX_MON2, /* 10 = TX_MON2 enabled */
TX_MON1_2, /* 11 = TX_MON1 & TX_MON2 enabled */
};
enum tx_port_sel {
TX_A,
TX_B,
};
enum digital_tune_skip_mode {
TUNE_RX_TX,
SKIP_TX,
SKIP_ALL,
};
enum rssi_restart_mode {
AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
EN_AGC_PIN_IS_PULLED_HIGH,
ENTERS_RX_MODE,
GAIN_CHANGE_OCCURS,
SPI_WRITE_TO_REGISTER,
GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
};
struct ctrl_outs_control {
u8 index;
u8 en_mask;
};
struct rssi_control {
enum rssi_restart_mode restart_mode;
bool rssi_unit_is_rx_samples; /* default unit is time */
u32 rssi_delay;
u32 rssi_wait;
u32 rssi_duration;
};
struct rf_rssi {
u32 ant; /* Antenna number for which RSSI is reported */
u32 symbol; /* Runtime RSSI */
u32 preamble; /* Initial RSSI */
s32 multiplier; /* Multiplier to convert reported RSSI */
u8 duration; /* Duration to be considered for measuring */
};
struct ad9361_rf_phy;
struct ad9361_debugfs_entry {
struct ad9361_rf_phy *phy;
const char *propname;
void *out_value;
u32 val;
u8 size;
u8 cmd;
};
struct ad9361_dig_tune_data {
u32 bist_loopback_mode;
u32 bist_config;
u32 ensm_state;
u8 skip_mode;
};
struct refclk_scale {
struct clk_hw hw;
struct spi_device *spi;
struct ad9361_rf_phy *phy;
unsigned long rate;
u32 mult;
u32 div;
enum ad9361_clocks source;
};
struct ad9361_rf_phy_state;
struct ad9361_ext_band_ctl;
struct ad9361_rf_phy {
struct spi_device *spi;
struct clk *clk_refin;
struct clk *clk_ext_lo_rx;
struct clk *clk_ext_lo_tx;
struct clk *clks[NUM_AD9361_CLKS];
struct notifier_block clk_nb_tx;
struct notifier_block clk_nb_rx;
struct refclk_scale clk_priv[NUM_AD9361_CLKS];
struct clk_onecell_data clk_data;
struct ad9361_phy_platform_data *pdata;
struct ad9361_debugfs_entry debugfs_entry[181];
struct bin_attribute bin;
struct bin_attribute bin_gt;
struct iio_dev *indio_dev;
struct work_struct work;
struct completion complete;
struct gain_table_info *gt_info;
char *bin_attr_buf;
u32 ad9361_debugfs_entry_index;
struct ad9361_ext_band_ctl *ext_band_ctl;
struct ad9361_rf_phy_state *state;
};
int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy, struct ctrl_outs_control *ctrl);
int ad9361_clk_set_rate(struct clk *clk, unsigned long rate);
int ad9361_rssi_setup(struct ad9361_rf_phy *phy,
struct rssi_control *ctrl,
bool is_update);
int ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi);
int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,u32 rf_rx_bw, u32 rf_tx_bw);
ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
char *buf, unsigned buflen);
int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable);
int ad9361_register_axi_converter(struct ad9361_rf_phy *phy);
struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi);
int ad9361_spi_read(struct spi_device *spi, u32 reg);
int ad9361_spi_write(struct spi_device *spi, u32 reg, u32 val);
int ad9361_bist_loopback(struct ad9361_rf_phy *phy, unsigned mode);
int ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode);
int ad9361_find_opt(u8 *field, u32 size, u32 *ret_start);
int ad9361_ensm_mode_disable_pinctrl(struct ad9361_rf_phy *phy);
int ad9361_ensm_mode_restore_pinctrl(struct ad9361_rf_phy *phy);
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, u8 ensm_state);
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, u8 ensm_state);
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy);
int ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy,
unsigned long freq);
int ad9361_set_trx_clock_chain_default(struct ad9361_rf_phy *phy);
int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq,
enum dig_tune_flags flags);
int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state);
int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num);
int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb, bool tx1, bool tx2, bool immed);
int ad9361_write_bist_reg(struct ad9361_rf_phy *phy, u32 val);
bool ad9361_uses_rx2tx2(struct ad9361_rf_phy *phy);
int ad9361_get_dig_tune_data(struct ad9361_rf_phy *phy,
struct ad9361_dig_tune_data *data);
int ad9361_read_clock_data_delays(struct ad9361_rf_phy *phy);
int ad9361_write_clock_data_delays(struct ad9361_rf_phy *phy);
bool ad9361_uses_lvds_mode(struct ad9361_rf_phy *phy);
int ad9361_set_rx_port(struct ad9361_rf_phy *phy, enum rx_port_sel sel);
int ad9361_set_tx_port(struct ad9361_rf_phy *phy, enum tx_port_sel sel);
#ifdef CONFIG_AD9361_EXT_BAND_CONTROL
int ad9361_register_ext_band_control(struct ad9361_rf_phy *phy);
int ad9361_adjust_rx_ext_band_settings(struct ad9361_rf_phy *phy, u64 freq);
int ad9361_adjust_tx_ext_band_settings(struct ad9361_rf_phy *phy, u64 freq);
void ad9361_unregister_ext_band_control(struct ad9361_rf_phy *phy);
#else
static inline int ad9361_register_ext_band_control(struct ad9361_rf_phy *phy)
{
return 0;
}
static inline int ad9361_adjust_rx_ext_band_settings(
struct ad9361_rf_phy *phy, u64 freq)
{
return 0;
}
static inline int ad9361_adjust_tx_ext_band_settings(
struct ad9361_rf_phy *phy, u64 freq)
{
return 0;
}
static inline void ad9361_unregister_ext_band_control(
struct ad9361_rf_phy *phy)
{}
#endif
#endif

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driver/ad9361/ad9361_conv.c Normal file
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/*
* AD9361 Agile RF Transceiver
*
* Copyright 2013-2017 Analog Devices Inc.
*
* Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*
* Licensed under the GPL-2.
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/string.h>
#include <linux/uaccess.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include "ad9361.h"
#if IS_ENABLED(CONFIG_CF_AXI_ADC)
#include "cf_axi_adc.h"
static void ad9361_set_intf_delay(struct ad9361_rf_phy *phy, bool tx,
unsigned int clock_delay,
unsigned int data_delay, bool clock_changed)
{
if (clock_changed)
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
ad9361_spi_write(phy->spi,
REG_RX_CLOCK_DATA_DELAY + (tx ? 1 : 0),
RX_DATA_DELAY(data_delay) |
DATA_CLK_DELAY(clock_delay));
if (clock_changed)
ad9361_ensm_force_state(phy, ENSM_STATE_FDD);
}
static unsigned int ad9361_num_phy_chan(struct axiadc_converter *conv)
{
if (conv->chip_info->num_channels > 4)
return 4;
return conv->chip_info->num_channels;
}
static int ad9361_check_pn(struct axiadc_converter *conv, bool tx,
unsigned int delay)
{
struct axiadc_state *st = iio_priv(conv->indio_dev);
unsigned int num_chan = ad9361_num_phy_chan(conv);
unsigned int chan;
for (chan = 0; chan < num_chan; chan++)
axiadc_write(st, ADI_REG_CHAN_STATUS(chan),
ADI_PN_ERR | ADI_PN_OOS);
mdelay(delay);
if (!tx && !(axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS))
return 1;
for (chan = 0; chan < num_chan; chan++) {
if (axiadc_read(st, ADI_REG_CHAN_STATUS(chan)))
return 1;
}
return 0;
}
ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
char *buf, unsigned buflen)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct ad9361_dig_tune_data data;
int i, j, len = 0;
int ret;
u8 field[16][16];
u8 rx;
if (!conv)
return -ENODEV;
ret = ad9361_get_dig_tune_data(phy, &data);
if (ret < 0)
return ret;
dev_dbg(&phy->spi->dev, "%s:\n", __func__);
rx = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY);
/* Mute TX, we don't want to transmit the PRBS */
ad9361_tx_mute(phy, 1);
ad9361_ensm_mode_disable_pinctrl(phy);
ad9361_bist_loopback(phy, 0);
ad9361_bist_prbs(phy, BIST_INJ_RX);
for (i = 0; i < 16; i++) {
for (j = 0; j < 16; j++) {
ad9361_set_intf_delay(phy, false, i, j, j == 0);
field[j][i] = ad9361_check_pn(conv, false, 1);
}
}
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, rx);
ad9361_bist_loopback(phy, data.bist_loopback_mode);
ad9361_write_bist_reg(phy, data.bist_config);
ad9361_ensm_mode_restore_pinctrl(phy);
ad9361_ensm_restore_state(phy, data.ensm_state);
ad9361_tx_mute(phy, 0);
len += snprintf(buf + len, buflen, "CLK: %lu Hz 'o' = PASS\n",
clk_get_rate(phy->clks[RX_SAMPL_CLK]));
len += snprintf(buf + len, buflen, "DC");
for (i = 0; i < 16; i++)
len += snprintf(buf + len, buflen, "%x:", i);
len += snprintf(buf + len, buflen, "\n");
for (i = 0; i < 16; i++) {
len += snprintf(buf + len, buflen, "%x:", i);
for (j = 0; j < 16; j++) {
len += snprintf(buf + len, buflen, "%c ",
(field[i][j] ? '.' : 'o'));
}
len += snprintf(buf + len, buflen, "\n");
}
len += snprintf(buf + len, buflen, "\n");
return len;
}
EXPORT_SYMBOL(ad9361_dig_interface_timing_analysis);
static ssize_t samples_pps_read(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan, char *buf)
{
struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
struct axiadc_state *st = iio_priv(conv->indio_dev);
u32 config, val, mode;
config = axiadc_read(st, ADI_REG_CONFIG);
if (!(config & ADI_PPS_RECEIVER_ENABLE))
return -ENODEV;
val = axiadc_read(st, ADI_REG_CLOCKS_PER_PPS_STATUS);
if (val & ADI_CLOCKS_PER_PPS_STAT_INVAL)
return -ETIMEDOUT;
mode = axiadc_read(st, ADI_REG_CNTRL);
/*
* Counts DATA_CLK cycles therefore needs to be corrected
* for 2rx2tx mode or for LVDS vs. CMOS mode.
*/
val = axiadc_read(st, ADI_REG_CLOCKS_PER_PPS);
if (!(mode & ADI_R1_MODE))
val /= 2;
if (!(config & ADI_CMOS_OR_LVDS_N))
val /= 2;
return sprintf(buf, "%u\n", val);
}
/*
* Returns the number of samples during a 1PPS (Pulse Per Second) interval.
*/
static struct iio_chan_spec_ext_info axiadc_ext_info[] = {
{
.name = "samples_pps",
.read = samples_pps_read,
.shared = IIO_SHARED_BY_TYPE,
},
{},
};
#define AIM_CHAN(_chan, _si, _bits, _sign) \
{ .type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = _chan, \
.info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_CALIBBIAS) | \
BIT(IIO_CHAN_INFO_CALIBPHASE), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.ext_info = axiadc_ext_info, \
.scan_index = _si, \
.scan_type = { \
.sign = _sign, \
.realbits = _bits, \
.storagebits = 16, \
.shift = 0, \
}, \
}
#define AIM_MC_CHAN(_chan, _si, _bits, _sign) \
{ .type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = _chan, \
.scan_index = _si, \
.scan_type = { \
.sign = _sign, \
.realbits = _bits, \
.storagebits = 16, \
.shift = 0, \
}, \
}
static const unsigned long ad9361_2x2_available_scan_masks[] = {
0x01, 0x02, 0x04, 0x08, 0x03, 0x0C, /* 1 & 2 chan */
0x10, 0x20, 0x40, 0x80, 0x30, 0xC0, /* 1 & 2 chan */
0x33, 0xCC, 0xC3, 0x3C, 0x0F, 0xF0, /* 4 chan */
0xFF, /* 8 chan */
0x00,
};
static const unsigned long ad9361_available_scan_masks[] = {
0x01, 0x02, 0x04, 0x08, 0x03, 0x0C, 0x0F,
0x00,
};
static const struct axiadc_chip_info axiadc_chip_info_tbl[] = {
[ID_AD9361] = {
.name = "AD9361",
.max_rate = 61440000UL,
.max_testmode = 0,
.num_channels = 4,
.scan_masks = ad9361_available_scan_masks,
.channel[0] = AIM_CHAN(0, 0, 12, 'S'),
.channel[1] = AIM_CHAN(1, 1, 12, 'S'),
.channel[2] = AIM_CHAN(2, 2, 12, 'S'),
.channel[3] = AIM_CHAN(3, 3, 12, 'S'),
},
[ID_AD9361_2] = { /* MCS/MIMO 2x AD9361 */
.name = "AD9361-2",
.max_rate = 61440000UL,
.max_testmode = 0,
.num_channels = 8,
.num_shadow_slave_channels = 4,
.scan_masks = ad9361_2x2_available_scan_masks,
.channel[0] = AIM_CHAN(0, 0, 12, 'S'),
.channel[1] = AIM_CHAN(1, 1, 12, 'S'),
.channel[2] = AIM_CHAN(2, 2, 12, 'S'),
.channel[3] = AIM_CHAN(3, 3, 12, 'S'),
.channel[4] = AIM_MC_CHAN(4, 4, 12, 'S'),
.channel[5] = AIM_MC_CHAN(5, 5, 12, 'S'),
.channel[6] = AIM_MC_CHAN(6, 6, 12, 'S'),
.channel[7] = AIM_MC_CHAN(7, 7, 12, 'S'),
},
[ID_AD9364] = {
.name = "AD9364",
.max_rate = 61440000UL,
.max_testmode = 0,
.num_channels = 2,
.channel[0] = AIM_CHAN(0, 0, 12, 'S'),
.channel[1] = AIM_CHAN(1, 1, 12, 'S'),
},
};
static int ad9361_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long m)
{
struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
switch (m) {
case IIO_CHAN_INFO_SAMP_FREQ:
if (!conv->clk)
return -ENODEV;
*val = conv->adc_clk = clk_get_rate(conv->clk);
return IIO_VAL_INT;
}
return -EINVAL;
}
static int ad9361_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask)
{
struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
unsigned long r_clk;
int ret;
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
if (!conv->clk)
return -ENODEV;
if (chan->extend_name)
return -ENODEV;
r_clk = clk_round_rate(conv->clk, val);
if (r_clk < 0 || r_clk > conv->chip_info->max_rate) {
dev_warn(&conv->spi->dev,
"Error setting ADC sample rate %ld", r_clk);
return -EINVAL;
}
ret = clk_set_rate(conv->clk, r_clk);
if (ret < 0)
return ret;
return 0;
break;
default:
return -EINVAL;
}
return 0;
}
int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct axiadc_state *st;
unsigned reg, addr, chan, version;
if (!conv)
return -ENODEV;
st = iio_priv(conv->indio_dev);
version = axiadc_read(st, 0x4000);
/* Still there but implemented a bit different */
if (PCORE_VERSION_MAJOR(version) > 7)
addr = 0x4418;
else
addr = 0x4414;
for (chan = 0; chan < conv->chip_info->num_channels; chan++) {
reg = axiadc_read(st, addr + (chan) * 0x40);
if (PCORE_VERSION_MAJOR(version) > 7) {
if (enable && reg != 0x8) {
conv->scratch_reg[chan] = reg;
reg = 0x8;
} else if (reg == 0x8) {
reg = conv->scratch_reg[chan];
}
} else {
/* DAC_LB_ENB If set enables loopback of receive data */
if (enable)
reg |= BIT(1);
else
reg &= ~BIT(1);
}
axiadc_write(st, addr + (chan) * 0x40, reg);
}
return 0;
}
EXPORT_SYMBOL(ad9361_hdl_loopback);
static int ad9361_iodelay_set(struct axiadc_state *st, unsigned lane,
unsigned val, bool tx)
{
if (tx) {
if (PCORE_VERSION_MAJOR(st->pcore_version) > 8)
axiadc_write(st, 0x4000 + ADI_REG_DELAY(lane), val);
else
return -ENODEV;
} else {
axiadc_idelay_set(st, lane, val);
}
return 0;
}
static int ad9361_midscale_iodelay(struct ad9361_rf_phy *phy, bool tx)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct axiadc_state *st = iio_priv(conv->indio_dev);
int ret = 0, i;
for (i = 0; i < 7; i++)
ret |= ad9361_iodelay_set(st, i, 15, tx);
return 0;
}
static int ad9361_dig_tune_iodelay(struct ad9361_rf_phy *phy, bool tx)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct axiadc_state *st = iio_priv(conv->indio_dev);
int i, j;
u32 s0, c0;
u8 field[32];
for (i = 0; i < 7; i++) {
for (j = 0; j < 32; j++) {
ad9361_iodelay_set(st, i, j, tx);
mdelay(1);
field[j] = ad9361_check_pn(conv, tx, 10);
}
c0 = ad9361_find_opt(&field[0], 32, &s0);
ad9361_iodelay_set(st, i, s0 + c0 / 2, tx);
dev_info(&phy->spi->dev,
"%s Lane %d, window cnt %d , start %d, IODELAY set to %d\n",
tx ? "TX" :"RX", i , c0, s0, s0 + c0 / 2);
}
return 0;
}
static void ad9361_dig_tune_verbose_print(struct ad9361_rf_phy *phy,
u8 field[][16], bool tx,
int sel_clk, int sel_data)
{
int i, j;
char c;
pr_info("SAMPL CLK: %lu tuning: %s\n",
clk_get_rate(phy->clks[RX_SAMPL_CLK]), tx ? "TX" : "RX");
pr_info(" ");
for (i = 0; i < 16; i++)
pr_cont("%x:", i);
pr_cont("\n");
for (i = 0; i < 2; i++) {
pr_info("%x:", i);
for (j = 0; j < 16; j++) {
if (field[i][j])
c = '#';
else if ((i == 0 && j == sel_data) ||
(i == 1 && j == sel_clk))
c = 'O';
else
c = 'o';
pr_cont("%c ", c);
}
pr_cont("\n");
}
}
static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy,
unsigned long max_freq,
enum dig_tune_flags flags, bool tx)
{
static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
unsigned int s0, s1, c0, c1;
unsigned int i, j, r;
bool half_data_rate;
u8 field[2][16];
if (ad9361_uses_lvds_mode(phy) || !ad9361_uses_rx2tx2(phy))
half_data_rate = false;
else
half_data_rate = true;
memset(field, 0, 32);
for (r = 0; r < (max_freq ? ARRAY_SIZE(rates) : 1); r++) {
if (max_freq)
ad9361_set_trx_clock_chain_freq(phy,
half_data_rate ? rates[r] / 2 : rates[r]);
for (i = 0; i < 2; i++) {
for (j = 0; j < 16; j++) {
/*
* i == 0: clock delay = 0, data delay from 0 to 15
* i == 1: clock delay = 15, data delay from 15 to 0
*/
ad9361_set_intf_delay(phy, tx, i ? 15 : 0,
i ? 15 - j : j, j == 0);
field[i][j] |= ad9361_check_pn(conv, tx, 4);
}
}
if ((flags & BE_MOREVERBOSE) && max_freq) {
ad9361_dig_tune_verbose_print(phy, field, tx, -1, -1);
}
}
c0 = ad9361_find_opt(&field[0][0], 16, &s0);
c1 = ad9361_find_opt(&field[1][0], 16, &s1);
if (!c0 && !c1) {
ad9361_dig_tune_verbose_print(phy, field, tx, -1, -1);
dev_err(&phy->spi->dev, "%s: Tuning %s FAILED!", __func__,
tx ? "TX" : "RX");
return -EIO;
} else if (flags & BE_VERBOSE) {
ad9361_dig_tune_verbose_print(phy, field, tx,
c1 > c0 ? (s1 + c1 / 2) : -1,
c1 > c0 ? -1 : (s0 + c0 / 2));
}
if (c1 > c0)
ad9361_set_intf_delay(phy, tx, s1 + c1 / 2, 0, true);
else
ad9361_set_intf_delay(phy, tx, 0, s0 + c0 / 2, true);
return 0;
}
static int ad9361_dig_tune_rx(struct ad9361_rf_phy *phy, unsigned long max_freq,
enum dig_tune_flags flags)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct axiadc_state *st = iio_priv(conv->indio_dev);
int ret;
ad9361_bist_loopback(phy, 0);
ad9361_bist_prbs(phy, BIST_INJ_RX);
ret = ad9361_dig_tune_delay(phy, max_freq, flags, false);
if (flags & DO_IDELAY)
ad9361_dig_tune_iodelay(phy, false);
axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN);
axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
return ret;
}
static int ad9361_dig_tune_tx(struct ad9361_rf_phy *phy, unsigned long max_freq,
enum dig_tune_flags flags)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct axiadc_state *st = iio_priv(conv->indio_dev);
u32 saved_dsel[4], saved_chan_ctrl6[4], saved_chan_ctrl0[4];
unsigned int chan, num_chan;
unsigned int hdl_dac_version;
u32 tmp, saved = 0;
int ret;
num_chan = ad9361_num_phy_chan(conv);
hdl_dac_version = axiadc_read(st, 0x4000);
ad9361_bist_prbs(phy, BIST_DISABLE);
ad9361_bist_loopback(phy, 1);
axiadc_write(st, 0x4000 + ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
for (chan = 0; chan < num_chan; chan++) {
saved_chan_ctrl0[chan] = axiadc_read(st, ADI_REG_CHAN_CNTRL(chan));
axiadc_write(st, ADI_REG_CHAN_CNTRL(chan),
ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |
ADI_ENABLE | ADI_IQCOR_ENB);
axiadc_set_pnsel(st, chan, ADC_PN_CUSTOM);
saved_chan_ctrl6[chan] = axiadc_read(st, 0x4414 + (chan) * 0x40);
if (PCORE_VERSION_MAJOR(hdl_dac_version) > 7) {
saved_dsel[chan] = axiadc_read(st, 0x4418 + (chan) * 0x40);
axiadc_write(st, 0x4418 + (chan) * 0x40, 9);
axiadc_write(st, 0x4414 + (chan) * 0x40, 0); /* !IQCOR_ENB */
axiadc_write(st, 0x4044, 1);
} else {
axiadc_write(st, 0x4414 + (chan) * 0x40, 1); /* DAC_PN_ENB */
}
}
if (PCORE_VERSION_MAJOR(hdl_dac_version) < 8) {
saved = tmp = axiadc_read(st, 0x4048);
tmp &= ~0xF;
tmp |= 1;
axiadc_write(st, 0x4048, tmp);
}
ret = ad9361_dig_tune_delay(phy, max_freq, flags, true);
if (flags & DO_ODELAY)
ad9361_dig_tune_iodelay(phy, true);
if (PCORE_VERSION_MAJOR(hdl_dac_version) < 8)
axiadc_write(st, 0x4048, saved);
for (chan = 0; chan < num_chan; chan++) {
axiadc_write(st, ADI_REG_CHAN_CNTRL(chan),
saved_chan_ctrl0[chan]);
axiadc_set_pnsel(st, chan, ADC_PN9);
if (PCORE_VERSION_MAJOR(hdl_dac_version) > 7) {
axiadc_write(st, 0x4418 + chan * 0x40,
saved_dsel[chan]);
axiadc_write(st, 0x4044, 1);
}
axiadc_write(st, 0x4414 + chan * 0x40, saved_chan_ctrl6[chan]);
}
return ret;
}
int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq,
enum dig_tune_flags flags)
{
struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
struct ad9361_dig_tune_data data;
struct axiadc_state *st;
bool restore = false;
int ret = 0;
if (!conv)
return -ENODEV;
ret = ad9361_get_dig_tune_data(phy, &data);
if (ret < 0)
return ret;
dev_dbg(&phy->spi->dev, "%s: freq %lu flags 0x%X\n", __func__,
max_freq, flags);
st = iio_priv(conv->indio_dev);
if ((data.skip_mode == SKIP_ALL) ||
(flags & RESTORE_DEFAULT)) {
/* skip completely and use defaults */
restore = true;
} else {
/* Mute TX, we don't want to transmit the PRBS */
ad9361_tx_mute(phy, 1);
ad9361_ensm_mode_disable_pinctrl(phy);
if (flags & DO_IDELAY)
ad9361_midscale_iodelay(phy, false);
if (flags & DO_ODELAY)
ad9361_midscale_iodelay(phy, true);
ret = ad9361_dig_tune_rx(phy, max_freq, flags);
if (ret == 0 && (data.skip_mode == TUNE_RX_TX))
ret = ad9361_dig_tune_tx(phy, max_freq, flags);
ad9361_bist_loopback(phy, data.bist_loopback_mode);
ad9361_write_bist_reg(phy, data.bist_config);
if (ret == -EIO)
restore = true;
if (!max_freq)
ret = 0;
}
if (restore) {
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
ad9361_write_clock_data_delays(phy);
} else if (!(flags & SKIP_STORE_RESULT)) {
ad9361_read_clock_data_delays(phy);
}
ad9361_ensm_mode_restore_pinctrl(phy);
ad9361_ensm_restore_state(phy, data.ensm_state);
axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN);
axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
ad9361_tx_mute(phy, 0);
return ret;
}
EXPORT_SYMBOL(ad9361_dig_tune);
static int ad9361_post_setup(struct iio_dev *indio_dev)
{
struct axiadc_state *st = iio_priv(indio_dev);
struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
struct ad9361_rf_phy *phy = conv->phy;
bool rx2tx2 = ad9361_uses_rx2tx2(phy);
unsigned tmp, num_chan, flags;
int i, ret;
num_chan = ad9361_num_phy_chan(conv);
conv->indio_dev = indio_dev;
axiadc_write(st, ADI_REG_CNTRL, rx2tx2 ? 0 : ADI_R1_MODE);
tmp = axiadc_read(st, 0x4048);
if (!rx2tx2) {
axiadc_write(st, 0x4048, tmp | BIT(5)); /* R1_MODE */
axiadc_write(st, 0x404c,
ad9361_uses_lvds_mode(phy) ? 1 : 0); /* RATE */
} else {
tmp &= ~BIT(5);
axiadc_write(st, 0x4048, tmp);
axiadc_write(st, 0x404c,
ad9361_uses_lvds_mode(phy) ? 3 : 1); /* RATE */
}
for (i = 0; i < num_chan; i++) {
axiadc_write(st, ADI_REG_CHAN_CNTRL_1(i),
ADI_DCFILT_OFFSET(0));
axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i),
(i & 1) ? 0x00004000 : 0x40000000);
axiadc_write(st, ADI_REG_CHAN_CNTRL(i),
ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |
ADI_ENABLE | ADI_IQCOR_ENB);
}
flags = 0;
ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_REG_ID)) ?
0 : 61440000, flags);
if (ret < 0)
goto error;
if (flags & (DO_IDELAY | DO_ODELAY)) {
ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_REG_ID)) ?
0 : 61440000, flags & BE_VERBOSE);
if (ret < 0)
goto error;
}
ret = ad9361_set_trx_clock_chain_default(phy);
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
ad9361_ensm_restore_prev_state(phy);
return 0;
error:
spi_set_drvdata(phy->spi, NULL);
return ret;
}
int ad9361_register_axi_converter(struct ad9361_rf_phy *phy)
{
struct axiadc_converter *conv;
struct spi_device *spi = phy->spi;
int ret;
conv = devm_kzalloc(&spi->dev, sizeof(*conv), GFP_KERNEL);
if (conv == NULL)
return -ENOMEM;
conv->id = ad9361_spi_read(spi, REG_PRODUCT_ID) & PRODUCT_ID_MASK;
if (conv->id != PRODUCT_ID_9361) {
dev_err(&spi->dev, "Unrecognized CHIP_ID 0x%X\n", conv->id);
ret = -ENODEV;
goto out;
}
conv->chip_info = &axiadc_chip_info_tbl[
(spi_get_device_id(spi)->driver_data == ID_AD9361_2) ?
ID_AD9361_2 : ad9361_uses_rx2tx2(phy) ? ID_AD9361 : ID_AD9364];
conv->write_raw = ad9361_write_raw;
conv->read_raw = ad9361_read_raw;
conv->post_setup = ad9361_post_setup;
conv->spi = spi;
conv->phy = phy;
conv->clk = phy->clks[RX_SAMPL_CLK];
conv->adc_clk = clk_get_rate(conv->clk);
spi_set_drvdata(spi, conv); /* Take care here */
return 0;
out:
spi_set_drvdata(spi, NULL);
return ret;
}
EXPORT_SYMBOL(ad9361_register_axi_converter);
struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi)
{
struct axiadc_converter *conv = spi_get_drvdata(spi);
return conv->phy;
}
EXPORT_SYMBOL(ad9361_spi_to_phy);
#else /* CONFIG_CF_AXI_ADC */
int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq,
enum dig_tune_flags flags)
{
return -ENODEV;
}
EXPORT_SYMBOL(ad9361_dig_tune);
ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
char *buf, unsigned buflen)
{
return 0;
}
EXPORT_SYMBOL(ad9361_dig_interface_timing_analysis);
int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
{
return -ENODEV;
}
EXPORT_SYMBOL(ad9361_hdl_loopback);
int ad9361_register_axi_converter(struct ad9361_rf_phy *phy)
{
struct spi_device *spi = phy->spi;
spi_set_drvdata(spi, phy); /* Take care here */
return 0;
}
EXPORT_SYMBOL(ad9361_register_axi_converter);
struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi)
{
return spi_get_drvdata(spi);
}
EXPORT_SYMBOL(ad9361_spi_to_phy);
#endif /* CONFIG_CF_AXI_ADC */

479
driver/ad9361/ad9361_private.h Normal file
View File

@ -0,0 +1,479 @@
/*
* AD9361 - Private definitions to be used only in the ad9361.c file
*
* Copyright 2013-2018 Analog Devices Inc.
*
* Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*
* Licensed under the GPL-2.
*/
#ifndef IIO_AD9361_PRIVATE_H_
#define IIO_AD9361_PRIVATE_H_
#ifndef IIO_AD9361_USE_PRIVATE_H_
#error "Please do not include ad9361_private.h; use ad9361.h instead"
#endif
#include "ad9361.h"
/*
* Driver
*/
enum rx_gain_table_type {
RXGAIN_FULL_TBL,
RXGAIN_SPLIT_TBL,
};
enum rx_gain_table_name {
TBL_200_1300_MHZ,
TBL_1300_4000_MHZ,
TBL_4000_6000_MHZ,
RXGAIN_TBLS_END,
};
enum fir_dest {
FIR_TX1 = 0x01,
FIR_TX2 = 0x02,
FIR_TX1_TX2 = 0x03,
FIR_RX1 = 0x81,
FIR_RX2 = 0x82,
FIR_RX1_RX2 = 0x83,
FIR_IS_RX = 0x80,
};
struct rf_gain_ctrl {
u32 ant;
u8 mode;
};
enum rf_gain_ctrl_mode {
RF_GAIN_MGC,
RF_GAIN_FASTATTACK_AGC,
RF_GAIN_SLOWATTACK_AGC,
RF_GAIN_HYBRID_AGC
};
enum f_agc_target_gain_index_type {
MAX_GAIN,
SET_GAIN,
OPTIMIZED_GAIN,
NO_GAIN_CHANGE,
};
struct gain_control {
enum rf_gain_ctrl_mode rx1_mode;
enum rf_gain_ctrl_mode rx2_mode;
/* Common */
u8 adc_ovr_sample_size; /* 1..8 Sum x samples, AGC_CONFIG_3 */
u8 adc_small_overload_thresh; /* 0..255, 0x105 */
u8 adc_large_overload_thresh; /* 0..255, 0x104 */
u16 lmt_overload_high_thresh; /* 16..800 mV, 0x107 */
u16 lmt_overload_low_thresh; /* 16..800 mV, 0x108 */
u16 dec_pow_measuremnt_duration; /* Samples, 0x15C */
u8 low_power_thresh; /* -64..0 dBFS, 0x114 */
bool use_rx_fir_out_for_dec_pwr_meas; /* clears 0x15C:6 USE_HB1_OUT_FOR_DEC_PWR_MEAS */
bool dig_gain_en; /* should be turned off, since ADI GT doesn't use dig gain */
u8 max_dig_gain; /* 0..31 */
/* MGC */
bool mgc_rx1_ctrl_inp_en; /* Enables Pin control on RX1 default SPI ctrl */
bool mgc_rx2_ctrl_inp_en; /* Enables Pin control on RX2 default SPI ctrl */
u8 mgc_inc_gain_step; /* 1..8 */
u8 mgc_dec_gain_step; /* 1..8 */
u8 mgc_split_table_ctrl_inp_gain_mode; /* 0=AGC determine this, 1=only in LPF, 2=only in LMT */
/* AGC */
u8 agc_attack_delay_extra_margin_us; /* 0..31 us */
u8 agc_outer_thresh_high;
u8 agc_outer_thresh_high_dec_steps;
u8 agc_inner_thresh_high;
u8 agc_inner_thresh_high_dec_steps;
u8 agc_inner_thresh_low;
u8 agc_inner_thresh_low_inc_steps;
u8 agc_outer_thresh_low;
u8 agc_outer_thresh_low_inc_steps;
u8 adc_small_overload_exceed_counter; /* 0..15, 0x122 */
u8 adc_large_overload_exceed_counter; /* 0..15, 0x122 */
u8 adc_large_overload_inc_steps; /* 0..15, 0x106 */
bool adc_lmt_small_overload_prevent_gain_inc; /* 0x120 */
u8 lmt_overload_large_exceed_counter; /* 0..15, 0x121 */
u8 lmt_overload_small_exceed_counter; /* 0..15, 0x121 */
u8 lmt_overload_large_inc_steps; /* 0..7, 0x121 */
u8 dig_saturation_exceed_counter; /* 0..15, 0x128 */
u8 dig_gain_step_size; /* 1..8, 0x100 */
bool sync_for_gain_counter_en; /* 0x128:4 !Hybrid */
u32 gain_update_interval_us; /* in us */
bool immed_gain_change_if_large_adc_overload; /* 0x123:3 */
bool immed_gain_change_if_large_lmt_overload; /* 0x123:7 */
/*
* Fast AGC
*/
u32 f_agc_dec_pow_measuremnt_duration; /* Samples, 0x15C */
u32 f_agc_state_wait_time_ns; /* 0x117 0..31 RX samples -> time_ns */
/* Fast AGC - Low Power */
bool f_agc_allow_agc_gain_increase; /* 0x110:1 */
u8 f_agc_lp_thresh_increment_time; /* 0x11B RX samples */
u8 f_agc_lp_thresh_increment_steps; /* 0x117 1..8 */
/* Fast AGC - Lock Level */
u8 f_agc_lock_level; /* NOT USED: 0x101 0..-127 dBFS same as agc_inner_thresh_high */
bool f_agc_lock_level_lmt_gain_increase_en; /* 0x111:6 */
u8 f_agc_lock_level_gain_increase_upper_limit; /* 0x118 0..63 */
/* Fast AGC - Peak Detectors and Final Settling */
u8 f_agc_lpf_final_settling_steps; /* 0x112:6 0..3 (Post Lock Level Step)*/
u8 f_agc_lmt_final_settling_steps; /* 0x113:6 0..3 (Post Lock Level Step)*/
u8 f_agc_final_overrange_count; /* 0x116:5 0..7 */
/* Fast AGC - Final Power Test */
bool f_agc_gain_increase_after_gain_lock_en; /* 0x110:7 */
/* Fast AGC - Unlocking the Gain */
/* 0 = MAX Gain, 1 = Set Gain, 2 = Optimized Gain */
enum f_agc_target_gain_index_type f_agc_gain_index_type_after_exit_rx_mode; /* 0x110:[4,2] */
bool f_agc_use_last_lock_level_for_set_gain_en; /* 0x111:7 */
u8 f_agc_optimized_gain_offset; /*0x116 0..15 steps */
bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en; /* 0x110:~6 */
u8 f_agc_rst_gla_stronger_sig_thresh_above_ll; /*0x113 0..63 dbFS */
bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* 0x110:6 */
bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en; /* 0x110:6 */
u8 f_agc_rst_gla_engergy_lost_sig_thresh_below_ll; /* 0x112:6 */
u8 f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* 0x119 0..63 RX samples */
bool f_agc_rst_gla_large_adc_overload_en; /*0x110:~1 and 0x114:~7 */
bool f_agc_rst_gla_large_lmt_overload_en; /*0x110:~1 */
bool f_agc_rst_gla_en_agc_pulled_high_en;
/* 0 = Max Gain, 1 = Set Gain, 2 = Optimized Gain, 3 = No Gain Change */
enum f_agc_target_gain_index_type f_agc_rst_gla_if_en_agc_pulled_high_mode; /* 0x0FB, 0x111 */
u8 f_agc_power_measurement_duration_in_state5; /* 0x109, 0x10a RX samples 0..524288*/
u8 f_agc_large_overload_inc_steps; /* 0x106 [D6:D4] 0..7 */
};
struct auxdac_control {
u16 dac1_default_value;
u16 dac2_default_value;
bool auxdac_manual_mode_en;
bool dac1_in_rx_en;
bool dac1_in_tx_en;
bool dac1_in_alert_en;
bool dac2_in_rx_en;
bool dac2_in_tx_en;
bool dac2_in_alert_en;
u8 dac1_rx_delay_us;
u8 dac1_tx_delay_us;
u8 dac2_rx_delay_us;
u8 dac2_tx_delay_us;
};
struct rx_gain_info {
enum rx_gain_table_type tbl_type;
int starting_gain_db;
int max_gain_db;
int gain_step_db;
int max_idx;
int idx_step_offset;
};
struct port_control {
u8 pp_conf[3];
u8 rx_clk_data_delay;
u8 tx_clk_data_delay;
u8 digital_io_ctrl;
u8 lvds_bias_ctrl;
u8 lvds_invert[2];
};
#if 0
struct ctrl_outs_control {
u8 index;
u8 en_mask;
};
#endif
struct elna_control {
u16 gain_mdB;
u16 bypass_loss_mdB;
u32 settling_delay_ns;
bool elna_1_control_en; /* GPO0 */
bool elna_2_control_en; /* GPO1 */
bool elna_in_gaintable_all_index_en;
};
struct auxadc_control {
s8 offset;
u32 temp_time_inteval_ms;
u32 temp_sensor_decimation;
bool periodic_temp_measuremnt;
u32 auxadc_clock_rate;
u32 auxadc_decimation;
};
struct gpo_control {
u32 gpo_manual_mode_enable_mask;
bool gpo_manual_mode_en;
bool gpo0_inactive_state_high_en;
bool gpo1_inactive_state_high_en;
bool gpo2_inactive_state_high_en;
bool gpo3_inactive_state_high_en;
bool gpo0_slave_rx_en;
bool gpo0_slave_tx_en;
bool gpo1_slave_rx_en;
bool gpo1_slave_tx_en;
bool gpo2_slave_rx_en;
bool gpo2_slave_tx_en;
bool gpo3_slave_rx_en;
bool gpo3_slave_tx_en;
u8 gpo0_rx_delay_us;
u8 gpo0_tx_delay_us;
u8 gpo1_rx_delay_us;
u8 gpo1_tx_delay_us;
u8 gpo2_rx_delay_us;
u8 gpo2_tx_delay_us;
u8 gpo3_rx_delay_us;
u8 gpo3_tx_delay_us;
};
struct tx_monitor_control {
bool tx_mon_track_en;
bool one_shot_mode_en;
u32 low_high_gain_threshold_mdB;
u8 low_gain_dB;
u8 high_gain_dB;
u16 tx_mon_delay;
u16 tx_mon_duration;
u8 tx1_mon_front_end_gain;
u8 tx2_mon_front_end_gain;
u8 tx1_mon_lo_cm;
u8 tx2_mon_lo_cm;
};
enum ad9361_pdata_rx_freq {
BBPLL_FREQ,
ADC_FREQ,
R2_FREQ,
R1_FREQ,
CLKRF_FREQ,
RX_SAMPL_FREQ,
NUM_RX_CLOCKS,
};
enum ad9361_pdata_tx_freq {
IGNORE,
DAC_FREQ,
T2_FREQ,
T1_FREQ,
CLKTF_FREQ,
TX_SAMPL_FREQ,
NUM_TX_CLOCKS,
};
enum ad9361_clkout {
CLKOUT_DISABLE,
BUFFERED_XTALN_DCXO,
ADC_CLK_DIV_2,
ADC_CLK_DIV_3,
ADC_CLK_DIV_4,
ADC_CLK_DIV_8,
ADC_CLK_DIV_16,
};
enum synth_pd_ctrl {
LO_DONTCARE,
LO_OFF,
LO_ON,
};
struct ad9361_phy_platform_data {
bool rx2tx2;
bool fdd;
bool fdd_independent_mode;
bool split_gt;
bool use_extclk;
bool ensm_pin_pulse_mode;
bool ensm_pin_ctrl;
bool debug_mode;
bool tdd_use_dual_synth;
bool tdd_skip_vco_cal;
bool use_ext_rx_lo;
bool use_ext_tx_lo;
bool rx1rx2_phase_inversion_en;
bool qec_tracking_slow_mode_en;
bool dig_interface_tune_fir_disable;
bool lo_powerdown_managed_en;
u8 dc_offset_update_events;
u8 dc_offset_attenuation_high;
u8 dc_offset_attenuation_low;
u8 rf_dc_offset_count_high;
u8 rf_dc_offset_count_low;
u8 dig_interface_tune_skipmode;
u32 dcxo_coarse;
u32 dcxo_fine;
bool rf_rx_input_sel_lock;
bool rf_tx_output_sel_lock;
u32 rx1tx1_mode_use_rx_num;
u32 rx1tx1_mode_use_tx_num;
unsigned long rx_path_clks[NUM_RX_CLOCKS];
unsigned long tx_path_clks[NUM_TX_CLOCKS];
u32 trx_synth_max_fref;
u64 rx_synth_freq;
u64 tx_synth_freq;
u32 rf_rx_bandwidth_Hz;
u32 rf_tx_bandwidth_Hz;
int tx_atten;
bool update_tx_gain_via_alert;
u32 rx_fastlock_delay_ns;
u32 tx_fastlock_delay_ns;
bool trx_fastlock_pinctrl_en[2];
enum ad9361_clkout ad9361_clkout_mode;
struct gain_control gain_ctrl;
struct rssi_control rssi_ctrl;
u32 rssi_lna_err_tbl[4];
u32 rssi_mixer_err_tbl[16];
u32 rssi_gain_step_calib_reg_val[5];
bool rssi_skip_calib;
struct port_control port_ctrl;
struct ctrl_outs_control ctrl_outs_ctrl;
struct elna_control elna_ctrl;
struct auxadc_control auxadc_ctrl;
struct auxdac_control auxdac_ctrl;
struct gpo_control gpo_ctrl;
struct tx_monitor_control txmon_ctrl;
struct gpio_desc *reset_gpio;
/* MCS SYNC */
struct gpio_desc *sync_gpio;
struct gpio_desc *cal_sw1_gpio;
struct gpio_desc *cal_sw2_gpio;
};
struct rf_rx_gain {
u32 ant; /* Antenna number to read gain */
s32 gain_db; /* gain value in dB */
u32 fgt_lmt_index; /* Full Gain Table / LNA-MIXER-TIA gain index */
u32 lmt_gain; /* LNA-MIXER-TIA gain in dB (Split GT mode only)*/
u32 lpf_gain; /* Low pass filter gain in dB / index (Split GT mode only)*/
u32 digital_gain; /* Digital gain in dB / index */
/* Debug only */
u32 lna_index; /* LNA Index (Split GT mode only) */
u32 tia_index; /* TIA Index (Split GT mode only) */
u32 mixer_index; /* MIXER Index (Split GT mode only) */
};
struct SynthLUT {
u16 VCO_MHz;
u8 VCO_Output_Level;
u8 VCO_Varactor;
u8 VCO_Bias_Ref;
u8 VCO_Bias_Tcf;
u8 VCO_Cal_Offset;
u8 VCO_Varactor_Reference;
u8 Charge_Pump_Current;
u8 LF_C2;
u8 LF_C1;
u8 LF_R1;
u8 LF_C3;
u8 LF_R3;
};
#define SYNTH_LUT_SIZE 53
enum {
LUT_FTDD_40,
LUT_FTDD_60,
LUT_FTDD_80,
LUT_FTDD_ENT,
};
struct ad9361_fastlock_entry {
#define FASTLOOK_INIT 1
u8 flags;
u8 alc_orig;
u8 alc_written;
};
struct ad9361_fastlock {
u8 save_profile;
u8 current_profile[2];
struct ad9361_fastlock_entry entry[2][8];
};
struct ad9361_rf_phy_state {
u8 prev_ensm_state;
u8 curr_ensm_state;
u8 cached_rx_rfpll_div;
u8 cached_tx_rfpll_div;
u8 cached_synth_pd[2];
int tx_quad_lpf_tia_match;
int current_table;
int rx_sampl_freq_avail[3];
int tx_sampl_freq_avail[3];
int rx_gain_avail[3];
bool ensm_pin_ctl_en;
bool auto_cal_en;
bool manual_tx_quad_cal_en;
u64 last_tx_quad_cal_freq;
u32 last_tx_quad_cal_phase;
u64 current_tx_lo_freq;
u64 current_rx_lo_freq;
bool current_tx_use_tdd_table;
bool current_rx_use_tdd_table;
unsigned long current_rx_path_clks[NUM_RX_CLOCKS];
unsigned long current_tx_path_clks[NUM_TX_CLOCKS];
unsigned long flags;
unsigned long cal_threshold_freq;
u32 current_rx_bw_Hz;
u32 current_tx_bw_Hz;
u32 rxbbf_div;
u32 rate_governor;
bool bypass_rx_fir;
bool bypass_tx_fir;
bool rx_eq_2tx;
bool filt_valid;
unsigned long filt_rx_path_clks[NUM_RX_CLOCKS];
unsigned long filt_tx_path_clks[NUM_TX_CLOCKS];
u32 filt_rx_bw_Hz;
u32 filt_tx_bw_Hz;
u8 tx_fir_int;
u8 tx_fir_ntaps;
u8 rx_fir_dec;
u8 rx_fir_ntaps;
u8 agc_mode[2];
bool rfdc_track_en;
bool bbdc_track_en;
bool quad_track_en;
bool txmon_tdd_en;
u16 auxdac1_value;
u16 auxdac2_value;
u32 tx1_atten_cached;
u32 tx2_atten_cached;
u8 bist_loopback_mode;
u8 bist_config;
u32 rf_rx_input_sel;
u32 rf_tx_output_sel;
struct ad9361_fastlock fastlock;
};
#endif

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/*
* ADI-AIM ADI ADC Interface Module
*
* Copyright 2012-2017 Analog Devices Inc.
*
* Licensed under the GPL-2.
*
* http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467
*
* Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*
*/
#ifndef ADI_AXI_ADC_H_
#define ADI_AXI_ADC_H_
#define ADI_REG_VERSION 0x0000 /*Version and Scratch Registers */
#define ADI_VERSION(x) (((x) & 0xffffffff) << 0) /* RO, Version number. */
#define VERSION_IS(x,y,z) ((x) << 16 | (y) << 8 | (z))
#define ADI_REG_ID 0x0004 /*Version and Scratch Registers */
#define ADI_ID(x) (((x) & 0xffffffff) << 0) /* RO, Instance identifier number. */
#define ADI_REG_SCRATCH 0x0008 /*Version and Scratch Registers */
#define ADI_SCRATCH(x) (((x) & 0xffffffff) << 0) /* RW, Scratch register. */
#define PCORE_VERSION(major, minor, letter) ((major << 16) | (minor << 8) | letter)
#define PCORE_VERSION_MAJOR(version) (version >> 16)
#define PCORE_VERSION_MINOR(version) ((version >> 8) & 0xff)
#define PCORE_VERSION_LETTER(version) (version & 0xff)
/* ADC COMMON */
#define ADI_REG_CONFIG 0x000C
#define ADI_IQCORRECTION_DISABLE (1 << 0)
#define ADI_DCFILTER_DISABLE (1 << 1)
#define ADI_DATAFORMAT_DISABLE (1 << 2)
#define ADI_USERPORTS_DISABLE (1 << 3)
#define ADI_MODE_1R1T (1 << 4)
#define ADI_SCALECORRECTION_ONLY (1 << 5)
#define ADI_CMOS_OR_LVDS_N (1 << 7)
#define ADI_PPS_RECEIVER_ENABLE (1 << 8)
#define ADI_REG_RSTN 0x0040
#define ADI_RSTN (1 << 0)
#define ADI_MMCM_RSTN (1 << 1)
#define ADI_REG_CNTRL 0x0044
#define ADI_R1_MODE (1 << 2)
#define ADI_DDR_EDGESEL (1 << 1)
#define ADI_PIN_MODE (1 << 0)
#define ADI_REG_CLK_FREQ 0x0054
#define ADI_CLK_FREQ(x) (((x) & 0xFFFFFFFF) << 0)
#define ADI_TO_CLK_FREQ(x) (((x) >> 0) & 0xFFFFFFFF)
#define ADI_REG_CLK_RATIO 0x0058
#define ADI_CLK_RATIO(x) (((x) & 0xFFFFFFFF) << 0)
#define ADI_TO_CLK_RATIO(x) (((x) >> 0) & 0xFFFFFFFF)
#define ADI_REG_STATUS 0x005C
#define ADI_MUX_PN_ERR (1 << 3)
#define ADI_MUX_PN_OOS (1 << 2)
#define ADI_MUX_OVER_RANGE (1 << 1)
#define ADI_STATUS (1 << 0)
#define ADI_REG_DELAY_CNTRL 0x0060 /* <= v8.0 */
#define ADI_DELAY_SEL (1 << 17)
#define ADI_DELAY_RWN (1 << 16)
#define ADI_DELAY_ADDRESS(x) (((x) & 0xFF) << 8)
#define ADI_TO_DELAY_ADDRESS(x) (((x) >> 8) & 0xFF)
#define ADI_DELAY_WDATA(x) (((x) & 0x1F) << 0)
#define ADI_TO_DELAY_WDATA(x) (((x) >> 0) & 0x1F)
#define ADI_REG_DELAY_STATUS 0x0064 /* <= v8.0 */
#define ADI_DELAY_LOCKED (1 << 9)
#define ADI_DELAY_STATUS (1 << 8)
#define ADI_DELAY_RDATA(x) (((x) & 0x1F) << 0)
#define ADI_TO_DELAY_RDATA(x) (((x) >> 0) & 0x1F)
#define ADI_REG_DRP_CNTRL 0x0070
#define ADI_DRP_SEL (1 << 29)
#define ADI_DRP_RWN (1 << 28)
#define ADI_DRP_ADDRESS(x) (((x) & 0xFFF) << 16)
#define ADI_TO_DRP_ADDRESS(x) (((x) >> 16) & 0xFFF)
#define ADI_DRP_WDATA(x) (((x) & 0xFFFF) << 0)
#define ADI_TO_DRP_WDATA(x) (((x) >> 0) & 0xFFFF)
#define ADI_REG_DRP_STATUS 0x0074
#define ADI_DRP_STATUS (1 << 16)
#define ADI_DRP_RDATA(x) (((x) & 0xFFFF) << 0)
#define ADI_TO_DRP_RDATA(x) (((x) >> 0) & 0xFFFF)
#define ADI_REG_DMA_STATUS 0x0088
#define ADI_DMA_OVF (1 << 2)
#define ADI_DMA_UNF (1 << 1)
#define ADI_DMA_STATUS (1 << 0)
#define ADI_REG_DMA_BUSWIDTH 0x008C
#define ADI_DMA_BUSWIDTH(x) (((x) & 0xFFFFFFFF) << 0)
#define ADI_TO_DMA_BUSWIDTH(x) (((x) >> 0) & 0xFFFFFFFF)
#define ADI_REG_USR_CNTRL_1 0x00A0
#define ADI_USR_CHANMAX(x) (((x) & 0xFF) << 0)
#define ADI_TO_USR_CHANMAX(x) (((x) >> 0) & 0xFF)
#define ADI_REG_GP_CONTROL 0x00BC
#define ADI_REG_CLOCKS_PER_PPS 0x00C0
#define ADI_REG_CLOCKS_PER_PPS_STATUS 0x00C4
#define ADI_CLOCKS_PER_PPS_STAT_INVAL (1 << 0)
/* ADC CHANNEL */
#define ADI_REG_CHAN_CNTRL(c) (0x0400 + (c) * 0x40)
#define ADI_PN_SEL (1 << 10) /* !v8.0 */
#define ADI_IQCOR_ENB (1 << 9)
#define ADI_DCFILT_ENB (1 << 8)
#define ADI_FORMAT_SIGNEXT (1 << 6)
#define ADI_FORMAT_TYPE (1 << 5)
#define ADI_FORMAT_ENABLE (1 << 4)
#define ADI_PN23_TYPE (1 << 1) /* !v8.0 */
#define ADI_ENABLE (1 << 0)
#define ADI_REG_CHAN_STATUS(c) (0x0404 + (c) * 0x40)
#define ADI_PN_ERR (1 << 2)
#define ADI_PN_OOS (1 << 1)
#define ADI_OVER_RANGE (1 << 0)
#define ADI_REG_CHAN_CNTRL_1(c) (0x0410 + (c) * 0x40)
#define ADI_DCFILT_OFFSET(x) (((x) & 0xFFFF) << 16)
#define ADI_TO_DCFILT_OFFSET(x) (((x) >> 16) & 0xFFFF)
#define ADI_DCFILT_COEFF(x) (((x) & 0xFFFF) << 0)
#define ADI_TO_DCFILT_COEFF(x) (((x) >> 0) & 0xFFFF)
#define ADI_REG_CHAN_CNTRL_2(c) (0x0414 + (c) * 0x40)
#define ADI_IQCOR_COEFF_1(x) (((x) & 0xFFFF) << 16)
#define ADI_TO_IQCOR_COEFF_1(x) (((x) >> 16) & 0xFFFF)
#define ADI_IQCOR_COEFF_2(x) (((x) & 0xFFFF) << 0)
#define ADI_TO_IQCOR_COEFF_2(x) (((x) >> 0) & 0xFFFF)
#define ADI_REG_CHAN_CNTRL_3(c) (0x0418 + (c) * 0x40) /* v8.0 */
#define ADI_ADC_PN_SEL(x) (((x) & 0xF) << 16)
#define ADI_TO_ADC_PN_SEL(x) (((x) >> 16) & 0xF)
#define ADI_ADC_DATA_SEL(x) (((x) & 0xF) << 0)
#define ADI_TO_ADC_DATA_SEL(x) (((x) >> 0) & 0xF)
enum adc_pn_sel {
ADC_PN9 = 0,
ADC_PN23A = 1,
ADC_PN7 = 4,
ADC_PN15 = 5,
ADC_PN23 = 6,
ADC_PN31 = 7,
ADC_PN_CUSTOM = 9,
ADC_PN_OFF = 10,
};
enum adc_data_sel {
ADC_DATA_SEL_NORM,
ADC_DATA_SEL_LB, /* DAC loopback */
ADC_DATA_SEL_RAMP, /* TBD */
};
#define ADI_REG_CHAN_USR_CNTRL_1(c) (0x0420 + (c) * 0x40)
#define ADI_USR_DATATYPE_BE (1 << 25)
#define ADI_USR_DATATYPE_SIGNED (1 << 24)
#define ADI_USR_DATATYPE_SHIFT(x) (((x) & 0xFF) << 16)
#define ADI_TO_USR_DATATYPE_SHIFT(x) (((x) >> 16) & 0xFF)
#define ADI_USR_DATATYPE_TOTAL_BITS(x) (((x) & 0xFF) << 8)
#define ADI_TO_USR_DATATYPE_TOTAL_BITS(x) (((x) >> 8) & 0xFF)
#define ADI_USR_DATATYPE_BITS(x) (((x) & 0xFF) << 0)
#define ADI_TO_USR_DATATYPE_BITS(x) (((x) >> 0) & 0xFF)
#define ADI_REG_CHAN_USR_CNTRL_2(c) (0x0424 + (c) * 0x40)
#define ADI_USR_DECIMATION_M(x) (((x) & 0xFFFF) << 16)
#define ADI_TO_USR_DECIMATION_M(x) (((x) >> 16) & 0xFFFF)
#define ADI_USR_DECIMATION_N(x) (((x) & 0xFFFF) << 0)
#define ADI_TO_USR_DECIMATION_N(x) (((x) >> 0) & 0xFFFF)
#define ADI_REG_ADC_DP_DISABLE 0x00C0
/* PCORE Version > 8.00 */
#define ADI_REG_DELAY(l) (0x0800 + (l) * 0x4)
/* debugfs direct register access */
#define DEBUGFS_DRA_PCORE_REG_MAGIC 0x80000000
#define AXIADC_MAX_CHANNEL 16
#include <linux/spi/spi.h>
#include <linux/clk/clkscale.h>
struct axiadc_chip_info {
char *name;
unsigned num_channels;
unsigned num_shadow_slave_channels;
const unsigned long *scan_masks;
const int (*scale_table)[2];
int num_scales;
int max_testmode;
unsigned long max_rate;
struct iio_chan_spec channel[AXIADC_MAX_CHANNEL];
};
struct axiadc_state {
struct device *dev_spi;
struct iio_info iio_info;
struct clk *clk;
size_t regs_size;
void __iomem *regs;
void __iomem *slave_regs;
unsigned max_usr_channel;
unsigned adc_def_output_mode;
unsigned max_count;
unsigned id;
unsigned pcore_version;
unsigned decimation_factor;
bool dp_disable;
unsigned long long adc_clk;
unsigned have_slave_channels;
struct iio_hw_consumer *frontend;
struct iio_chan_spec channels[AXIADC_MAX_CHANNEL];
};
struct axiadc_converter {
struct spi_device *spi;
struct clk *clk;
struct clock_scale adc_clkscale;
struct clk *lane_clk;
struct clk *sysref_clk;
void *phy;
struct gpio_desc *pwrdown_gpio;
struct gpio_desc *reset_gpio;
unsigned id;
unsigned adc_output_mode;
unsigned testmode[AXIADC_MAX_CHANNEL];
unsigned scratch_reg[AXIADC_MAX_CHANNEL];
unsigned long adc_clk;
const struct axiadc_chip_info *chip_info;
bool sample_rate_read_only;
int (*reg_access)(struct iio_dev *indio_dev, unsigned int reg,
unsigned int writeval, unsigned int *readval);
int (*setup)(struct spi_device *spi, unsigned mode);
struct iio_chan_spec const *channels;
int num_channels;
const struct attribute_group *attrs;
struct iio_dev *indio_dev;
int (*read_raw)(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val,
int *val2,
long mask);
int (*write_raw)(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val,
int val2,
long mask);
int (*read_event_value)(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val,
int *val2);
int (*write_event_value)(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val,
int val2);
int (*read_event_config)(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir);
int (*write_event_config)(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
int state);
int (*post_setup)(struct iio_dev *indio_dev);
int (*set_pnsel)(struct iio_dev *indio_dev, unsigned chan,
enum adc_pn_sel sel);
};
static inline struct axiadc_converter *to_converter(struct device *dev)
{
struct axiadc_converter *conv = spi_get_drvdata(to_spi_device(dev));
if (conv)
return conv;
return ERR_PTR(-ENODEV);
};
struct axiadc_spidev {
struct device_node *of_nspi;
struct device *dev_spi;
};
/*
* IO accessors
*/
static inline void axiadc_write(struct axiadc_state *st, unsigned reg, unsigned val)
{
iowrite32(val, st->regs + reg);
}
static inline unsigned int axiadc_read(struct axiadc_state *st, unsigned reg)
{
return ioread32(st->regs + reg);
}
static inline void axiadc_slave_write(struct axiadc_state *st, unsigned reg, unsigned val)
{
iowrite32(val, st->slave_regs + reg);
}
static inline unsigned int axiadc_slave_read(struct axiadc_state *st, unsigned reg)
{
return ioread32(st->slave_regs + reg);
}
static inline void axiadc_idelay_set(struct axiadc_state *st,
unsigned lane, unsigned val)
{
if (PCORE_VERSION_MAJOR(st->pcore_version) > 8) {
axiadc_write(st, ADI_REG_DELAY(lane), val);
} else {
axiadc_write(st, ADI_REG_DELAY_CNTRL, 0);
axiadc_write(st, ADI_REG_DELAY_CNTRL,
ADI_DELAY_ADDRESS(lane)
| ADI_DELAY_WDATA(val)
| ADI_DELAY_SEL);
}
}
int axiadc_set_pnsel(struct axiadc_state *st, int channel, enum adc_pn_sel sel);
enum adc_pn_sel axiadc_get_pnsel(struct axiadc_state *st,
int channel, const char **name);
int axiadc_configure_ring_stream(struct iio_dev *indio_dev,
const char *dma_name);
void axiadc_unconfigure_ring_stream(struct iio_dev *indio_dev);
#endif /* ADI_AXI_ADC_H_ */

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// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
const char *sdr_compatible_str = "sdr,sdr";
enum openwifi_band {
BAND_900M = 0,
BAND_2_4GHZ,
BAND_3_65GHZ,
BAND_5_0GHZ,
BAND_5_8GHZ,
BAND_5_9GHZ,
BAND_60GHZ,
};
// ------------------------------------tx interface----------------------------------------
const char *tx_intf_compatible_str = "sdr,tx_intf";
#define TX_INTF_REG_MULTI_RST_ADDR (0*4)
#define TX_INTF_REG_MIXER_CFG_ADDR (1*4)
#define TX_INTF_REG_WIFI_TX_MODE_ADDR (2*4)
#define TX_INTF_REG_IQ_SRC_SEL_ADDR (3*4)
#define TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR (4*4)
#define TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4)
#define TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR (6*4)
#define TX_INTF_REG_MISC_SEL_ADDR (7*4)
#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4)
#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4)
#define TX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4)
#define TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL1_ADDR (12*4)
#define TX_INTF_REG_BB_GAIN_ADDR (13*4)
#define TX_INTF_REG_INTERRUPT_SEL_ADDR (14*4)
#define TX_INTF_REG_ANT_SEL_ADDR (16*4)
#define TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR (21*4)
#define TX_INTF_REG_PKT_INFO_ADDR (22*4)
#define TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR (24*4)
#define TX_INTF_NUM_ANTENNA 2
#define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8)
#define TX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3
enum tx_intf_mode {
TX_INTF_AXIS_LOOP_BACK = 0,
TX_INTF_BYPASS,
TX_INTF_BW_20MHZ_AT_0MHZ_ANT0,
TX_INTF_BW_20MHZ_AT_0MHZ_ANT1,
TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,
TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,
TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,
TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
};
const int tx_intf_fo_mapping[] = {0, 0, 0, 0,-10,10,-10,10};
struct tx_intf_driver_api {
u32 (*hw_init)(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
u32 (*TX_INTF_REG_MULTI_RST_read)(void);
u32 (*TX_INTF_REG_MIXER_CFG_read)(void);
u32 (*TX_INTF_REG_WIFI_TX_MODE_read)(void);
u32 (*TX_INTF_REG_IQ_SRC_SEL_read)(void);
u32 (*TX_INTF_REG_CTS_TOSELF_CONFIG_read)(void);
u32 (*TX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);
u32 (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read)(void);
u32 (*TX_INTF_REG_MISC_SEL_read)(void);
u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
u32 (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
u32 (*TX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
u32 (*TX_INTF_REG_INTERRUPT_SEL_read)(void);
u32 (*TX_INTF_REG_BB_GAIN_read)(void);
u32 (*TX_INTF_REG_ANT_SEL_read)(void);
u32 (*TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read)(void);
u32 (*TX_INTF_REG_PKT_INFO_read)(void);
u32 (*TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read)(void);
void (*TX_INTF_REG_MULTI_RST_write)(u32 value);
void (*TX_INTF_REG_MIXER_CFG_write)(u32 value);
void (*TX_INTF_REG_WIFI_TX_MODE_write)(u32 value);
void (*TX_INTF_REG_IQ_SRC_SEL_write)(u32 value);
void (*TX_INTF_REG_CTS_TOSELF_CONFIG_write)(u32 value);
void (*TX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);
void (*TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write)(u32 value);
void (*TX_INTF_REG_MISC_SEL_write)(u32 value);
void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
void (*TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
void (*TX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
void (*TX_INTF_REG_INTERRUPT_SEL_write)(u32 value);
void (*TX_INTF_REG_BB_GAIN_write)(u32 value);
void (*TX_INTF_REG_ANT_SEL_write)(u32 value);
void (*TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write)(u32 value);
void (*TX_INTF_REG_PKT_INFO_write)(u32 value);
};
// ------------------------------------rx interface----------------------------------------
const char *rx_intf_compatible_str = "sdr,rx_intf";
#define RX_INTF_REG_MULTI_RST_ADDR (0*4)
#define RX_INTF_REG_MIXER_CFG_ADDR (1*4)
#define RX_INTF_REG_INTERRUPT_TEST_ADDR (2*4)
#define RX_INTF_REG_IQ_SRC_SEL_ADDR (3*4)
#define RX_INTF_REG_IQ_CTRL_ADDR (4*4)
#define RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR (5*4)
#define RX_INTF_REG_START_TRANS_TO_PS_ADDR (6*4)
#define RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR (7*4)
#define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR (8*4)
#define RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR (9*4)
#define RX_INTF_REG_CFG_DATA_TO_ANT_ADDR (10*4)
#define RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR (12*4)
#define RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR (13*4)
#define RX_INTF_REG_ANT_SEL_ADDR (16*4)
#define RX_INTF_NUM_ANTENNA 2
#define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL (64/8)
#define RX_INTF_NUM_BYTE_PER_DMA_SYMBOL_IN_BITS 3
enum rx_intf_mode {
RX_INTF_AXIS_LOOP_BACK = 0,
RX_INTF_BYPASS,
RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,
RX_INTF_BW_20MHZ_AT_0MHZ_ANT1,
RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0,
RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1,
RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0,
RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1,
};
const int rx_intf_fo_mapping[] = {0,0,0,0,-10,-10,10,10};
struct rx_intf_driver_api {
u32 io_start;
u32 base_addr;
u32 (*hw_init)(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
u32 (*RX_INTF_REG_MULTI_RST_read)(void);
u32 (*RX_INTF_REG_MIXER_CFG_read)(void);
u32 (*RX_INTF_REG_IQ_SRC_SEL_read)(void);
u32 (*RX_INTF_REG_IQ_CTRL_read)(void);
u32 (*RX_INTF_REG_START_TRANS_TO_PS_MODE_read)(void);
u32 (*RX_INTF_REG_START_TRANS_TO_PS_read)(void);
u32 (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read)(void);
u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read)(void);
u32 (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read)(void);
u32 (*RX_INTF_REG_CFG_DATA_TO_ANT_read)(void);
u32 (*RX_INTF_REG_ANT_SEL_read)(void);
u32 (*RX_INTF_REG_INTERRUPT_TEST_read)(void);
void (*RX_INTF_REG_MULTI_RST_write)(u32 value);
void (*RX_INTF_REG_MIXER_CFG_write)(u32 value);
void (*RX_INTF_REG_IQ_SRC_SEL_write)(u32 value);
void (*RX_INTF_REG_IQ_CTRL_write)(u32 value);
void (*RX_INTF_REG_START_TRANS_TO_PS_MODE_write)(u32 value);
void (*RX_INTF_REG_START_TRANS_TO_PS_write)(u32 value);
void (*RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write)(u32 value);
void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write)(u32 value);
void (*RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write)(u32 value);
void (*RX_INTF_REG_CFG_DATA_TO_ANT_write)(u32 value);
void (*RX_INTF_REG_ANT_SEL_write)(u32 value);
void (*RX_INTF_REG_INTERRUPT_TEST_write)(u32 value);
void (*RX_INTF_REG_M_AXIS_RST_write)(u32 value);
void (*RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write)(u32 value);
void (*RX_INTF_REG_TLAST_TIMEOUT_TOP_write)(u32 value);
};
// ----------------------------------openofdm rx-------------------------------
const char *openofdm_rx_compatible_str = "sdr,openofdm_rx";
#define OPENOFDM_RX_REG_MULTI_RST_ADDR (0*4)
#define OPENOFDM_RX_REG_ENABLE_ADDR (1*4)
#define OPENOFDM_RX_REG_POWER_THRES_ADDR (2*4)
#define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR (3*4)
#define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4)
enum openofdm_rx_mode {
OPENOFDM_RX_TEST = 0,
OPENOFDM_RX_NORMAL,
};
struct openofdm_rx_driver_api {
u32 power_thres;
u32 min_plateau;
u32 (*hw_init)(enum openofdm_rx_mode mode);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
u32 (*OPENOFDM_RX_REG_STATE_HISTORY_read)(void);
void (*OPENOFDM_RX_REG_MULTI_RST_write)(u32 value);
void (*OPENOFDM_RX_REG_ENABLE_write)(u32 value);
void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value);
void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value);
};
// ---------------------------------------openofdm tx-------------------------------
const char *openofdm_tx_compatible_str = "sdr,openofdm_tx";
#define OPENOFDM_TX_REG_MULTI_RST_ADDR (0*4)
#define OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR (1*4)
#define OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR (2*4)
enum openofdm_tx_mode {
OPENOFDM_TX_TEST = 0,
OPENOFDM_TX_NORMAL,
};
struct openofdm_tx_driver_api {
u32 (*hw_init)(enum openofdm_tx_mode mode);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
void (*OPENOFDM_TX_REG_MULTI_RST_write)(u32 value);
void (*OPENOFDM_TX_REG_INIT_PILOT_STATE_write)(u32 value);
void (*OPENOFDM_TX_REG_INIT_DATA_STATE_write)(u32 value);
};
// ---------------------------------------xpu low MAC controller-------------------------------
// extra filter flag together with enum ieee80211_filter_flags in mac80211.h
#define UNICAST_FOR_US (1<<9)
#define BROADCAST_ALL_ONE (1<<10)
#define BROADCAST_ALL_ZERO (1<<11)
#define MY_BEACON (1<<12)
#define MONITOR_ALL (1<<13)
const char *xpu_compatible_str = "sdr,xpu";
#define XPU_REG_MULTI_RST_ADDR (0*4)
#define XPU_REG_SRC_SEL_ADDR (1*4)
#define XPU_REG_TSF_LOAD_VAL_LOW_ADDR (2*4)
#define XPU_REG_TSF_LOAD_VAL_HIGH_ADDR (3*4)
#define XPU_REG_BAND_CHANNEL_ADDR (4*4)
#define XPU_REG_RSSI_DB_CFG_ADDR (7*4)
#define XPU_REG_LBT_TH_ADDR (8*4)
#define XPU_REG_CSMA_DEBUG_ADDR (9*4)
#define XPU_REG_BB_RF_DELAY_ADDR (10*4)
#define XPU_REG_MAX_NUM_RETRANS_ADDR (11*4)
#define XPU_REG_RECV_ACK_COUNT_TOP0_ADDR (16*4)
#define XPU_REG_RECV_ACK_COUNT_TOP1_ADDR (17*4)
#define XPU_REG_SEND_ACK_WAIT_TOP_ADDR (18*4)
#define XPU_REG_CSMA_CFG_ADDR (19*4)
#define XPU_REG_SLICE_COUNT_TOTAL0_ADDR (20*4)
#define XPU_REG_SLICE_COUNT_START0_ADDR (21*4)
#define XPU_REG_SLICE_COUNT_END0_ADDR (22*4)
#define XPU_REG_SLICE_COUNT_TOTAL1_ADDR (23*4)
#define XPU_REG_SLICE_COUNT_START1_ADDR (24*4)
#define XPU_REG_SLICE_COUNT_END1_ADDR (25*4)
#define XPU_REG_CTS_TO_RTS_CONFIG_ADDR (26*4)
#define XPU_REG_FILTER_FLAG_ADDR (27*4)
#define XPU_REG_BSSID_FILTER_LOW_ADDR (28*4)
#define XPU_REG_BSSID_FILTER_HIGH_ADDR (29*4)
#define XPU_REG_MAC_ADDR_LOW_ADDR (30*4)
#define XPU_REG_MAC_ADDR_HIGH_ADDR (31*4)
#define XPU_REG_FC_DI_ADDR (34*4)
#define XPU_REG_ADDR1_LOW_ADDR (35*4)
#define XPU_REG_ADDR1_HIGH_ADDR (36*4)
#define XPU_REG_ADDR2_LOW_ADDR (37*4)
#define XPU_REG_ADDR2_HIGH_ADDR (38*4)
#define XPU_REG_ADDR3_LOW_ADDR (39*4)
#define XPU_REG_ADDR3_HIGH_ADDR (40*4)
#define XPU_REG_SC_LOW_ADDR (41*4)
#define XPU_REG_ADDR4_HIGH_ADDR (42*4)
#define XPU_REG_ADDR4_LOW_ADDR (43*4)
#define XPU_REG_TRX_STATUS_ADDR (50*4)
#define XPU_REG_TX_RESULT_ADDR (51*4)
#define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR (58*4)
#define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4)
#define XPU_REG_RSSI_HALF_DB_ADDR (60*4)
#define XPU_REG_IQ_RSSI_HALF_DB_ADDR (61*4)
enum xpu_mode {
XPU_TEST = 0,
XPU_NORMAL,
};
struct xpu_driver_api {
u32 (*hw_init)(enum xpu_mode mode);
u32 (*reg_read)(u32 reg);
void (*reg_write)(u32 reg, u32 value);
void (*XPU_REG_MULTI_RST_write)(u32 value);
u32 (*XPU_REG_MULTI_RST_read)(void);
void (*XPU_REG_SRC_SEL_write)(u32 value);
u32 (*XPU_REG_SRC_SEL_read)(void);
void (*XPU_REG_RECV_ACK_COUNT_TOP0_write)(u32 value);
u32 (*XPU_REG_RECV_ACK_COUNT_TOP0_read)(void);
void (*XPU_REG_RECV_ACK_COUNT_TOP1_write)(u32 value);
u32 (*XPU_REG_RECV_ACK_COUNT_TOP1_read)(void);
void (*XPU_REG_SEND_ACK_WAIT_TOP_write)(u32 value);
u32 (*XPU_REG_SEND_ACK_WAIT_TOP_read)(void);
void (*XPU_REG_ACK_FC_FILTER_write)(u32 value);
u32 (*XPU_REG_ACK_FC_FILTER_read)(void);
void (*XPU_REG_CTS_TO_RTS_CONFIG_write)(u32 value);
u32 (*XPU_REG_CTS_TO_RTS_CONFIG_read)(void);
void (*XPU_REG_FILTER_FLAG_write)(u32 value);
u32 (*XPU_REG_FILTER_FLAG_read)(void);
void (*XPU_REG_MAC_ADDR_LOW_write)(u32 value);
u32 (*XPU_REG_MAC_ADDR_LOW_read)(void);
void (*XPU_REG_MAC_ADDR_HIGH_write)(u32 value);
u32 (*XPU_REG_MAC_ADDR_HIGH_read)(void);
void (*XPU_REG_BSSID_FILTER_LOW_write)(u32 value);
u32 (*XPU_REG_BSSID_FILTER_LOW_read)(void);
void (*XPU_REG_BSSID_FILTER_HIGH_write)(u32 value);
u32 (*XPU_REG_BSSID_FILTER_HIGH_read)(void);
void (*XPU_REG_BAND_CHANNEL_write)(u32 value);
u32 (*XPU_REG_BAND_CHANNEL_read)(void);
u32 (*XPU_REG_TRX_STATUS_read)(void);
u32 (*XPU_REG_TX_RESULT_read)(void);
u32 (*XPU_REG_TSF_RUNTIME_VAL_LOW_read)(void);
u32 (*XPU_REG_TSF_RUNTIME_VAL_HIGH_read)(void);
void (*XPU_REG_TSF_LOAD_VAL_LOW_write)(u32 value);
void (*XPU_REG_TSF_LOAD_VAL_HIGH_write)(u32 value);
void (*XPU_REG_TSF_LOAD_VAL_write)(u32 high_value, u32 low_value);
u32 (*XPU_REG_FC_DI_read)(void);
u32 (*XPU_REG_ADDR1_LOW_read)(void);
u32 (*XPU_REG_ADDR1_HIGH_read)(void);
u32 (*XPU_REG_ADDR2_LOW_read)(void);
u32 (*XPU_REG_ADDR2_HIGH_read)(void);
void (*XPU_REG_LBT_TH_write)(u32 value);
u32 (*XPU_REG_LBT_TH_read)(void);
void (*XPU_REG_RSSI_DB_CFG_write)(u32 value);
u32 (*XPU_REG_RSSI_DB_CFG_read)(void);
void (*XPU_REG_CSMA_DEBUG_write)(u32 value);
u32 (*XPU_REG_CSMA_DEBUG_read)(void);
void (*XPU_REG_CSMA_CFG_write)(u32 value);
u32 (*XPU_REG_CSMA_CFG_read)(void);
void (*XPU_REG_SLICE_COUNT_TOTAL0_write)(u32 value);
void (*XPU_REG_SLICE_COUNT_START0_write)(u32 value);
void (*XPU_REG_SLICE_COUNT_END0_write)(u32 value);
void (*XPU_REG_SLICE_COUNT_TOTAL1_write)(u32 value);
void (*XPU_REG_SLICE_COUNT_START1_write)(u32 value);
void (*XPU_REG_SLICE_COUNT_END1_write)(u32 value);
u32 (*XPU_REG_SLICE_COUNT_TOTAL0_read)(void);
u32 (*XPU_REG_SLICE_COUNT_START0_read)(void);
u32 (*XPU_REG_SLICE_COUNT_END0_read)(void);
u32 (*XPU_REG_SLICE_COUNT_TOTAL1_read)(void);
u32 (*XPU_REG_SLICE_COUNT_START1_read)(void);
u32 (*XPU_REG_SLICE_COUNT_END1_read)(void);
void (*XPU_REG_BB_RF_DELAY_write)(u32 value);
void (*XPU_REG_MAX_NUM_RETRANS_write)(u32 value);
void (*XPU_REG_MAC_ADDR_write)(u8 *mac_addr);
};

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driver/make_all.sh Executable file
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#!/bin/bash
xilinx_sdk_dir=$1
adi_lnx_dir=$2\
if [ "$#" -ne 2 ]; then
echo "You must enter exactly 2 command line arguments"
echo "First argument is the path, second argument is the path to adi linux repository, please don't add slash at the end of the path"
echo "Eg, ./make_all.sh /opt/Xilinx/SDK/2017.4 /home/gitfolder/linux"
exit 1
fi
# check if user entered the right path to SDK
if [ -d "$xilinx_sdk_dir" ]; then
echo " setup sdk path ${xilinx_sdk_dir}"
tmp=/settings64.sh
sdk_setting="$xilinx_sdk_dir$tmp"
source ${sdk_setting}
else
echo "Error: sdk: ${xilinx_sdk_dir} not found. Can not continue."
exit 1
fi
# check if user entered the right path to analog device linux
if [ -d "$adi_lnx_dir" ]; then
echo " setup linux kernel path ${adi_lnx_dir}"
else
echo "Error: path to adi linux: ${adi_lnx_dir} not found. Can not continue."
exit 1
fi
#source ~/Xilinx/SDK/2017.4/settings64.sh
#set -x
make KDIR=$adi_lnx_dir
cd openofdm_tx
make KDIR=$adi_lnx_dir
cd ../openofdm_rx
make KDIR=$adi_lnx_dir
cd ../tx_intf
make KDIR=$adi_lnx_dir
cd ../rx_intf
make KDIR=$adi_lnx_dir
cd ../xpu
make KDIR=$adi_lnx_dir
cd ../ad9361
make KDIR=$adi_lnx_dir
cd ../xilinx_dma
./make_xilinx_dma.sh $adi_lnx_dir $sdk_setting
cd ..

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driver/openofdm_rx/Makefile Normal file
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# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += openofdm_rx.o
all:
make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order

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driver/openofdm_rx/openofdm_rx.c Normal file
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/*
* axi lite register access driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>
#include <linux/dma/xilinx_dma.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_dma.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/delay.h>
#include "../hw_def.h"
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline u32 OPENOFDM_RX_REG_STATE_HISTORY_read(void){
return reg_read(OPENOFDM_RX_REG_STATE_HISTORY_ADDR);
}
static inline void OPENOFDM_RX_REG_MULTI_RST_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_MULTI_RST_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_ENABLE_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_ENABLE_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_POWER_THRES_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_POWER_THRES_ADDR, Data);
}
static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) {
reg_write(OPENOFDM_RX_REG_MIN_PLATEAU_ADDR, Data);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,openofdm_rx", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static struct openofdm_rx_driver_api openofdm_rx_driver_api_inst;
static struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst;
EXPORT_SYMBOL(openofdm_rx_api);
static inline u32 hw_init(enum openofdm_rx_mode mode){
int err=0;
printk("%s hw_init mode %d\n", openofdm_rx_compatible_str, mode);
switch(mode)
{
case OPENOFDM_RX_TEST:
{
printk("%s hw_init mode OPENOFDM_RX_TEST\n", openofdm_rx_compatible_str);
break;
}
case OPENOFDM_RX_NORMAL:
{
printk("%s hw_init mode OPENOFDM_RX_NORMAL\n", openofdm_rx_compatible_str);
openofdm_rx_api->power_thres = 0;
openofdm_rx_api->min_plateau = 100;
break;
}
default:
{
printk("%s hw_init mode %d is wrong!\n", openofdm_rx_compatible_str, mode);
err=1;
}
}
printk("%s hw_init input:\npower_thres %d\nmin_plateau %d\n",
openofdm_rx_compatible_str,
openofdm_rx_api->power_thres, openofdm_rx_api->min_plateau);
// 1) power threshold configuration and reset
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write(0);
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(100);
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write(0);
printk("%s hw_init err %d\n", openofdm_rx_compatible_str, err);
reg_write(4*4,1);//enable soft decoding
return(err);
}
static int dev_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *io;
int err=1;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe match!\n", openofdm_rx_compatible_str);
err = 0;
}
}
if (err)
return err;
openofdm_rx_api->hw_init=hw_init;
openofdm_rx_api->reg_read=reg_read;
openofdm_rx_api->reg_write=reg_write;
openofdm_rx_api->OPENOFDM_RX_REG_MULTI_RST_write=OPENOFDM_RX_REG_MULTI_RST_write;
openofdm_rx_api->OPENOFDM_RX_REG_ENABLE_write=OPENOFDM_RX_REG_ENABLE_write;
openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write;
openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", openofdm_rx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr);
printk("%s dev_probe openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst);
printk("%s dev_probe openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api);
printk("%s dev_probe succeed!\n", openofdm_rx_compatible_str);
err = hw_init(OPENOFDM_RX_NORMAL);
return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove base_addr 0x%08x\n", openofdm_rx_compatible_str,(u32)base_addr);
printk("%s dev_remove openofdm_rx_driver_api_inst 0x%08x\n", openofdm_rx_compatible_str, (u32)&openofdm_rx_driver_api_inst);
printk("%s dev_remove openofdm_rx_api 0x%08x\n", openofdm_rx_compatible_str, (u32)openofdm_rx_api);
printk("%s dev_remove succeed!\n", openofdm_rx_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,openofdm_rx",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,openofdm_rx");
MODULE_LICENSE("GPL v2");

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driver/openofdm_tx/Makefile Normal file
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# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += openofdm_tx.o
all:
make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order

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/*
* axi lite register access driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>
#include <linux/dma/xilinx_dma.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_dma.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/delay.h>
#include "../hw_def.h"
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline void OPENOFDM_TX_REG_MULTI_RST_write(u32 Data) {
reg_write(OPENOFDM_TX_REG_MULTI_RST_ADDR, Data);
}
static inline void OPENOFDM_TX_REG_INIT_PILOT_STATE_write(u32 Data) {
reg_write(OPENOFDM_TX_REG_INIT_PILOT_STATE_ADDR, Data);
}
static inline void OPENOFDM_TX_REG_INIT_DATA_STATE_write(u32 Data) {
reg_write(OPENOFDM_TX_REG_INIT_DATA_STATE_ADDR, Data);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,openofdm_tx", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static struct openofdm_tx_driver_api openofdm_tx_driver_api_inst;
static struct openofdm_tx_driver_api *openofdm_tx_api = &openofdm_tx_driver_api_inst;
EXPORT_SYMBOL(openofdm_tx_api);
static inline u32 hw_init(enum openofdm_tx_mode mode){
int err=0;
printk("%s hw_init mode %d\n", openofdm_tx_compatible_str, mode);
switch(mode)
{
case OPENOFDM_TX_TEST:
printk("%s hw_init mode OPENOFDM_TX_TEST\n", openofdm_tx_compatible_str);
break;
case OPENOFDM_TX_NORMAL:
printk("%s hw_init mode OPENOFDM_TX_NORMAL\n", openofdm_tx_compatible_str);
break;
default:
printk("%s hw_init mode %d is wrong!\n", openofdm_tx_compatible_str, mode);
err=1;
}
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0xFFFFFFFF);
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write(0);
openofdm_tx_api->OPENOFDM_TX_REG_INIT_PILOT_STATE_write(0x7E);
openofdm_tx_api->OPENOFDM_TX_REG_INIT_DATA_STATE_write(0x7F);
printk("%s hw_init err %d\n", openofdm_tx_compatible_str, err);
return(err);
}
static int dev_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *io;
int err=1;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe match!\n", openofdm_tx_compatible_str);
err = 0;
}
}
if (err)
return err;
openofdm_tx_api->hw_init=hw_init;
openofdm_tx_api->reg_read=reg_read;
openofdm_tx_api->reg_write=reg_write;
openofdm_tx_api->OPENOFDM_TX_REG_MULTI_RST_write=OPENOFDM_TX_REG_MULTI_RST_write;
openofdm_tx_api->OPENOFDM_TX_REG_INIT_PILOT_STATE_write=OPENOFDM_TX_REG_INIT_PILOT_STATE_write;
openofdm_tx_api->OPENOFDM_TX_REG_INIT_DATA_STATE_write=OPENOFDM_TX_REG_INIT_DATA_STATE_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", openofdm_tx_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%08x\n", openofdm_tx_compatible_str,(u32)base_addr);
printk("%s dev_probe openofdm_tx_driver_api_inst 0x%08x\n", openofdm_tx_compatible_str, (u32)&openofdm_tx_driver_api_inst);
printk("%s dev_probe openofdm_tx_api 0x%08x\n", openofdm_tx_compatible_str, (u32)openofdm_tx_api);
printk("%s dev_probe succeed!\n", openofdm_tx_compatible_str);
err = hw_init(OPENOFDM_TX_NORMAL);
return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove base_addr 0x%08x\n", openofdm_tx_compatible_str,(u32)base_addr);
printk("%s dev_remove openofdm_tx_driver_api_inst 0x%08x\n", openofdm_tx_compatible_str, (u32)&openofdm_tx_driver_api_inst);
printk("%s dev_remove openofdm_tx_api 0x%08x\n", openofdm_tx_compatible_str, (u32)openofdm_tx_api);
printk("%s dev_remove succeed!\n", openofdm_tx_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,openofdm_tx",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,openofdm_tx");
MODULE_LICENSE("GPL v2");

9
driver/rx_intf/Makefile Normal file
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@ -0,0 +1,9 @@
# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += rx_intf.o
all:
make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order

447
driver/rx_intf/rx_intf.c Normal file
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@ -0,0 +1,447 @@
/*
* axi lite register access driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>
#include <linux/dma/xilinx_dma.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_dma.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include "../hw_def.h"
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline u32 RX_INTF_REG_MULTI_RST_read(void){
return reg_read(RX_INTF_REG_MULTI_RST_ADDR);
}
static inline u32 RX_INTF_REG_MIXER_CFG_read(void){
return reg_read(RX_INTF_REG_MIXER_CFG_ADDR);
}
static inline u32 RX_INTF_REG_IQ_SRC_SEL_read(void){
return reg_read(RX_INTF_REG_IQ_SRC_SEL_ADDR);
}
static inline u32 RX_INTF_REG_IQ_CTRL_read(void){
return reg_read(RX_INTF_REG_IQ_CTRL_ADDR);
}
static inline u32 RX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){
return reg_read(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR);
}
static inline u32 RX_INTF_REG_START_TRANS_TO_PS_read(void){
return reg_read(RX_INTF_REG_START_TRANS_TO_PS_ADDR);
}
static inline u32 RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read(void){
return reg_read(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR);
}
static inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){
return reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR);
}
static inline u32 RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){
return reg_read(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR);
}
static inline u32 RX_INTF_REG_CFG_DATA_TO_ANT_read(void){
return reg_read(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR);
}
static inline u32 RX_INTF_REG_ANT_SEL_read(void){
return reg_read(RX_INTF_REG_ANT_SEL_ADDR);
}
static inline u32 RX_INTF_REG_INTERRUPT_TEST_read(void) {
return reg_read(RX_INTF_REG_INTERRUPT_TEST_ADDR);
}
static inline void RX_INTF_REG_MULTI_RST_write(u32 value){
reg_write(RX_INTF_REG_MULTI_RST_ADDR, value);
}
static inline void RX_INTF_REG_M_AXIS_RST_write(u32 value){
u32 reg_val;
if (value==0) {
reg_val = RX_INTF_REG_MULTI_RST_read();
reg_val = ( reg_val&(~(1<<4)) );
RX_INTF_REG_MULTI_RST_write(reg_val);
} else {
reg_val = RX_INTF_REG_MULTI_RST_read();
reg_val = ( reg_val|(1<<4) );
RX_INTF_REG_MULTI_RST_write(reg_val);
}
}
static inline void RX_INTF_REG_MIXER_CFG_write(u32 value){
reg_write(RX_INTF_REG_MIXER_CFG_ADDR, value);
}
static inline void RX_INTF_REG_IQ_SRC_SEL_write(u32 value){
reg_write(RX_INTF_REG_IQ_SRC_SEL_ADDR, value);
}
static inline void RX_INTF_REG_IQ_CTRL_write(u32 value){
reg_write(RX_INTF_REG_IQ_CTRL_ADDR, value);
}
static inline void RX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){
reg_write(RX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value);
}
static inline void RX_INTF_REG_START_TRANS_TO_PS_write(u32 value){
reg_write(RX_INTF_REG_START_TRANS_TO_PS_ADDR, value);
}
static inline void RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(u32 value){
reg_write(RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_ADDR, value);
}
static inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){
reg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value);
}
static inline void RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){
reg_write(RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value);
}
static inline void RX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){
reg_write(RX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value);
}
static inline void RX_INTF_REG_ANT_SEL_write(u32 value){
reg_write(RX_INTF_REG_ANT_SEL_ADDR, value);
}
static inline void RX_INTF_REG_INTERRUPT_TEST_write(u32 value) {
reg_write(RX_INTF_REG_INTERRUPT_TEST_ADDR, value);
}
static inline void RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(u32 value) {
reg_write(RX_INTF_REG_S2MM_INTR_DELAY_COUNT_ADDR, value);
}
static inline void RX_INTF_REG_TLAST_TIMEOUT_TOP_write(u32 value) {
reg_write(RX_INTF_REG_TLAST_TIMEOUT_TOP_ADDR, value);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,rx_intf", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static struct rx_intf_driver_api rx_intf_driver_api_inst;
//EXPORT_SYMBOL(rx_intf_driver_api_inst);
static struct rx_intf_driver_api *rx_intf_api = &rx_intf_driver_api_inst;
EXPORT_SYMBOL(rx_intf_api);
static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){
int err=0;
u32 reg_val, mixer_cfg=0, ant_sel=0;
printk("%s hw_init mode %d\n", rx_intf_compatible_str, mode);
////rst wifi rx -- slv_reg11[2] is actual rx reset. slv_reg11[0] only reset axi lite of rx
//printk("%s hw_init reset wifi rx\n", rx_intf_compatible_str);
//rx_intf_api->RX_INTF_REG_RST_START_TO_EXT_write(0);
//rx_intf_api->RX_INTF_REG_RST_START_TO_EXT_write(4);
//rx_intf_api->RX_INTF_REG_RST_START_TO_EXT_write(0);
rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write(7000);
//rst ddc internal module
for (reg_val=0;reg_val<32;reg_val++)
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0xFFFFFFFF);
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start
switch(mode)
{
case RX_INTF_AXIS_LOOP_BACK:
printk("%s hw_init mode RX_INTF_AXIS_LOOP_BACK\n", rx_intf_compatible_str);
//setting the path and mode. This must be done before our dma end reset
rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0x15);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(1);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x37);// endless mode to support sg DMA loop back, start 1 trans from sw trigger
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl);
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
// put bb_en to constant 1
reg_val = rx_intf_api->RX_INTF_REG_IQ_CTRL_read();
reg_val = (reg_val|0x8);
rx_intf_api->RX_INTF_REG_IQ_CTRL_write(reg_val);
// connect axis slave and master directly for loopback
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x1037);
// reset dma end point in our design
reg_val = rx_intf_api->RX_INTF_REG_MULTI_RST_read();
reg_val = (reg_val&(~0x14) );
rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val);
reg_val = reg_val|(0x14);
rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val);
reg_val = reg_val&(~0x14);
rx_intf_api->RX_INTF_REG_MULTI_RST_write(reg_val);
//start 1 trans now from our m_axis to ps dma
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(1);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0);
break;
case RX_INTF_BW_20MHZ_AT_0MHZ_ANT0:
printk("%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x300200F4;
ant_sel=0;
break;
case RX_INTF_BW_20MHZ_AT_0MHZ_ANT1:
printk("%s hw_init mode DDC_BW_20MHZ_AT_0MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x300200F4;
ant_sel=1;
break;
case RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0:
printk("%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x300202F6;
ant_sel=0;
break;
case RX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1:
printk("%s hw_init mode DDC_BW_20MHZ_AT_N_10MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x300202F6;
ant_sel=1;
break;
case RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0:
printk("%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x3001F602;
ant_sel=0;
break;
case RX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1:
printk("%s hw_init mode DDC_BW_20MHZ_AT_P_10MHZ\n", rx_intf_compatible_str);
mixer_cfg = 0x3001F602;
ant_sel=1;
break;
case RX_INTF_BYPASS:
printk("%s hw_init mode DDC_BYPASS\n", rx_intf_compatible_str);
mixer_cfg = 0x3001F602;
break;
default:
printk("%s hw_init mode %d is wrong!\n", rx_intf_compatible_str, mode);
err=1;
}
if (mode!=RX_INTF_AXIS_LOOP_BACK) {
rx_intf_api->RX_INTF_REG_MIXER_CFG_write(mixer_cfg);
// 0x000202F6 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: -2, -7, -12, -17MHz; zigbee 4 ch ant1: +3, +8, +13, +18MHz
// 0x0001F602 for: wifi ant0: +10MHz; wifi ant1: -10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz
// 0x0001F206 for: wifi ant0: -10MHz; wifi ant1: +10MHz; zigbee 4 ch ant0: +3, +8, +13, +18MHz; zigbee 4 ch ant1: -2, -7, -12, -17MHz
// 0x2101F602 for: wifi gain 4; zigbee gain 2
// 0xFE01F602 for: wifi gain 1/2; zigbee gain 1/4
// bits definitions:
// wifi ch selection: ant0 bit1~0; ant1 bit 9~8; ch offset: 0-0MHz; 1-5MHz; 2-10MHz; 3-15MHz(severe distortion)
// wifi ch +/- selection: ant0 bit2; ant1 bit 10; 0-positive; 1-negative
// zigbee 2M mixer +/- selection: ant0 bit3; ant1 bit 11; 0-positive; 1-negative
// zigbee secondary mixer +/- selection: ant0 bit4~7; ant1 bit 12~15; 0-positive; 1-negative
// zigbee ch slip offset: ant0 bit16; ant1 bit17; 0-select ch offset 0, 5, 10, 15; 1-select ch offset 5 10 15 20
// wifi gain: bit31~28; number of bits shifted to left in 2'complement code
// zigb gain: bit27~24; number of bits shifted to left in 2'complement code
// max amplitude calibration info (agc low, ddc w/o gain adj 0x0001F602): 5GHz, max amplitude 1.26e4. According to simulation, schr shrink 1bit should be enough
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start
//rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x000);
rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100);
//0x000-normal; 0x100-sig and fcs valid are controled by bit4 and bit0;
//0x111-sig and fcs high; 0x110-sig high fcs low; 0x101-sig low fcs high; 0x100-sig and fcs low
rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0);
// 0-bw20-ch0; 1-bw2-ch0; 2-bw2-ch2; 3-bw2-ch4; 4-bw2-ch6; 5-s_axis-ch0
// 8-bw20-ch1; 9-bw2-ch1; 10-bw2-ch3; 11-bw2-ch5; 12-bw2-ch7; 13-s_axis-ch1
//rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(1000|0x80000000); //0x80000000 to enable tsft and rssi gpio test magic value
//rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(200*10); //0x80000000 to enable tsft and rssi gpio test magic value
rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(30*200); // delayed interrupt
rx_intf_api->RX_INTF_REG_IQ_CTRL_write(0);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x10025); //now bit 5 should be 1 to let pl_to_m_axis_intf decide num_dma_symbol_to_ps automatically
//rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write(0x00025); //bit16 enable_m_axis_auto_rst
//bit2-0: source of M AXIS transfer trigger
// -0 fcs_valid_from_acc
// -1 sig_valid_from_acc
// -2 sig_invalid_from_acc
// -3 start_1trans_s_axis_tlast_trigger
// -4 start_1trans_s_axis_tready_trigger
// -5 internal state machine together with bit5 1. By parsing signal field, num_dma_symbol_to_ps can be decided automatically
// -6 start_1trans_monitor_dma_to_ps_start_trigger
// -7 start_1trans_ext_trigger
//bit3: 1-fcs valid and invalid both connected; 0-only fcs valid connected (fcs_invalid_mode)
//bit4: 1-num_dma_symbol_to_pl from monitor; 0-num_dma_symbol_to_pl from slv_reg8
//bit5: 1-num_dma_symbol_to_ps from monitor; 0-num_dma_symbol_to_ps from slv_reg9
//bit6: 1-pl_to_m_axis_intf will try to send both ht and non-ht; 0-only send non-ht
//bit8: 1-endless S AXIS; 0-normal
//bit9: 1-endless M AXIS; 0-normal
//bit12: 1-direct loop back; 0-normal
//bit16: 1-auto m_axis rst (sig_valid_from_acc|sig_invalid_from_acc|ht_sig_valid|ht_sig_invalid|ht_unsupported); 0-normal
//bit24: 1-disable m_axis fifo_rst_by_fcs_invalid; 0-enable
//bit29,28: sig_valid_mode. 0- non-ht sig valid; 1- ht sig valid other- both
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write(0);
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write(0);
// 0-wifi_rx packet out; 1-loopback from input of wifi_rx
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl);
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(1<<8);
rx_intf_api->RX_INTF_REG_ANT_SEL_write(ant_sel);
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0x14);//rst m/s axis
rx_intf_api->RX_INTF_REG_MULTI_RST_write(0);
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status. will be released when openwifi_start
}
if (mode==RX_INTF_BYPASS) {
rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write(0x10); //bit4 bypass enable
}
printk("%s hw_init err %d\n", rx_intf_compatible_str, err);
return(err);
}
static int dev_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *io;
int err=1;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe match!\n", rx_intf_compatible_str);
err = 0;
}
}
if (err)
return err;
rx_intf_api->hw_init=hw_init;
rx_intf_api->reg_read=reg_read;
rx_intf_api->reg_write=reg_write;
rx_intf_api->RX_INTF_REG_MULTI_RST_read=RX_INTF_REG_MULTI_RST_read;
rx_intf_api->RX_INTF_REG_MIXER_CFG_read=RX_INTF_REG_MIXER_CFG_read;
rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_read=RX_INTF_REG_IQ_SRC_SEL_read;
rx_intf_api->RX_INTF_REG_IQ_CTRL_read=RX_INTF_REG_IQ_CTRL_read;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_read=RX_INTF_REG_START_TRANS_TO_PS_MODE_read;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_read=RX_INTF_REG_START_TRANS_TO_PS_read;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_read;
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read;
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read;
rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_read=RX_INTF_REG_CFG_DATA_TO_ANT_read;
rx_intf_api->RX_INTF_REG_ANT_SEL_read=RX_INTF_REG_ANT_SEL_read;
rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_read=RX_INTF_REG_INTERRUPT_TEST_read;
rx_intf_api->RX_INTF_REG_MULTI_RST_write=RX_INTF_REG_MULTI_RST_write;
rx_intf_api->RX_INTF_REG_M_AXIS_RST_write=RX_INTF_REG_M_AXIS_RST_write;
rx_intf_api->RX_INTF_REG_MIXER_CFG_write=RX_INTF_REG_MIXER_CFG_write;
rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write=RX_INTF_REG_IQ_SRC_SEL_write;
rx_intf_api->RX_INTF_REG_IQ_CTRL_write=RX_INTF_REG_IQ_CTRL_write;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_MODE_write=RX_INTF_REG_START_TRANS_TO_PS_MODE_write;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_write=RX_INTF_REG_START_TRANS_TO_PS_write;
rx_intf_api->RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write=RX_INTF_REG_START_TRANS_TO_PS_SRC_SEL_write;
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write;
rx_intf_api->RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=RX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write;
rx_intf_api->RX_INTF_REG_CFG_DATA_TO_ANT_write=RX_INTF_REG_CFG_DATA_TO_ANT_write;
rx_intf_api->RX_INTF_REG_ANT_SEL_write=RX_INTF_REG_ANT_SEL_write;
rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write=RX_INTF_REG_INTERRUPT_TEST_write;
rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write=RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write;
rx_intf_api->RX_INTF_REG_TLAST_TIMEOUT_TOP_write=RX_INTF_REG_TLAST_TIMEOUT_TOP_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
rx_intf_api->io_start = io->start;
rx_intf_api->base_addr = (u32)base_addr;
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", rx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%08x\n", rx_intf_compatible_str,(u32)base_addr);
printk("%s dev_probe rx_intf_driver_api_inst 0x%08x\n", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) );
printk("%s dev_probe rx_intf_api 0x%08x\n", rx_intf_compatible_str, (u32)rx_intf_api);
printk("%s dev_probe succeed!\n", rx_intf_compatible_str);
//err = hw_init(DDC_CURRENT_CH_OFFSET_CFG,8,8);
err = hw_init(RX_INTF_BW_20MHZ_AT_0MHZ_ANT0,8,8);
return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove base_addr 0x%08x\n", rx_intf_compatible_str, (u32)base_addr);
printk("%s dev_remove rx_intf_driver_api_inst 0x%08x\n", rx_intf_compatible_str, (u32)(&rx_intf_driver_api_inst) );
printk("%s dev_remove rx_intf_api 0x%08x\n", rx_intf_compatible_str, (u32)rx_intf_api);
printk("%s dev_remove succeed!\n", rx_intf_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,rx_intf",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,rx_intf");
MODULE_LICENSE("GPL v2");

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// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
#ifndef OPENWIFI_SDR
#define OPENWIFI_SDR
// -------------------for leds--------------------------------
struct gpio_led_data { //pleas always align with the leds-gpio.c in linux kernel
struct led_classdev cdev;
struct gpio_desc *gpiod;
u8 can_sleep;
u8 blinking;
gpio_blink_set_t platform_gpio_blink_set;
};
struct gpio_leds_priv { //pleas always align with the leds-gpio.c in linux kernel
int num_leds;
struct gpio_led_data leds[];
};
struct openwifi_rf_ops {
char *name;
// void (*init)(struct ieee80211_hw *);
// void (*stop)(struct ieee80211_hw *);
void (*set_chan)(struct ieee80211_hw *, struct ieee80211_conf *);
// u8 (*calc_rssi)(u8 agc, u8 sq);
};
struct openwifi_buffer_descriptor {
u32 num_dma_byte;
u32 sn;
u32 hw_queue_idx;
u32 retry_limit;
u32 need_ack;
struct sk_buff *skb_linked;
dma_addr_t dma_mapping_addr;
u32 reserved;
} __packed;
struct openwifi_ring {
struct openwifi_buffer_descriptor *bds;
u32 bd_wr_idx;
u32 bd_rd_idx;
u32 reserved;
} __packed;
struct openwifi_vif {
struct ieee80211_hw *dev;
int idx; // this vif's idx on the dev
/* beaconing */
struct delayed_work beacon_work;
bool enable_beacon;
};
union u32_byte4 {
u32 a;
u8 c[4];
};
union u16_byte2 {
u16 a;
u8 c[2];
};
#define MAX_NUM_DRV_REG 32
#define MAX_NUM_LED 4
#define OPENWIFI_LED_MAX_NAME_LEN 32
#define MAX_NUM_VIF 4
#define LEN_PHY_HEADER 16
#define LEN_PHY_CRC 4
#define NUM_TX_BD 32
#define NUM_RX_BD 16
#define TX_BD_BUF_SIZE (8192)
#define RX_BD_BUF_SIZE (8192)
#define NUM_BIT_MAX_NUM_HW_QUEUE 2
#define MAX_NUM_HW_QUEUE 2
#define NUM_BIT_MAX_PHY_TX_SN 12
#define MAX_PHY_TX_SN ((1<<NUM_BIT_MAX_PHY_TX_SN)-1)
#define AD9361_RADIO_OFF_TX_ATT 89750 //please align with ad9361.c
#define AD9361_RADIO_ON_TX_ATT 000 //please align with rf_init.sh
#define SDR_SUPPORTED_FILTERS \
(FIF_ALLMULTI | \
FIF_BCN_PRBRESP_PROMISC | \
FIF_CONTROL | \
FIF_OTHER_BSS | \
FIF_PSPOLL | \
FIF_PROBE_REQ)
#define HIGH_PRIORITY_DISCARD_FLAG ((~0x040)<<16) // don't force drop OTHER_BSS by high priority discard
//#define HIGH_PRIORITY_DISCARD_FLAG ((~0x140)<<16) // don't force drop OTHER_BSS and PROB_REQ by high priority discard
/* 5G chan 36 - chan 64*/
#define SDR_5GHZ_CH36_64 \
REG_RULE(5150-10, 5350+10, 80, 0, 20, 0)
/* 5G chan 36 - chan 48*/
#define SDR_5GHZ_CH36_48 \
REG_RULE(5150-10, 5270+10, 80, 0, 20, 0)
/*
*Only these channels all allow active
*scan on all world regulatory domains
*/
#define SDR_2GHZ_CH01_13 REG_RULE(2412-10, 2472+10, 40, 0, 20, NL80211_RRF_NO_CCK) // disable 11b
#define SDR_2GHZ_CH01_14 REG_RULE(2412-10, 2484+10, 40, 0, 20, NL80211_RRF_NO_CCK) // disable 11b
// regulatory.h alpha2
// * 00 - World regulatory domain
// * 99 - built by driver but a specific alpha2 cannot be determined
// * 98 - result of an intersection between two regulatory domains
// * 97 - regulatory domain has not yet been configured
static const struct ieee80211_regdomain sdr_regd = { // for wiphy_apply_custom_regulatory
.n_reg_rules = 2,
.alpha2 = "99",
.dfs_region = NL80211_DFS_ETSI,
.reg_rules = {
//SDR_2GHZ_CH01_13,
//SDR_5GHZ_CH36_48, //Avoid radar!
SDR_2GHZ_CH01_14,
SDR_5GHZ_CH36_64,
}
};
#define CHAN2G(_channel, _freq, _flags) { \
.band = NL80211_BAND_2GHZ, \
.hw_value = (_channel), \
.center_freq = (_freq), \
.flags = (_flags), \
.max_antenna_gain = 0, \
.max_power = 0, \
}
#define CHAN5G(_channel, _freq, _flags) { \
.band = NL80211_BAND_5GHZ, \
.hw_value = (_channel), \
.center_freq = (_freq), \
.flags = (_flags), \
.max_antenna_gain = 0, \
.max_power = 0, \
}
static const struct ieee80211_rate openwifi_5GHz_rates[] = {
{ .bitrate = 10, .hw_value = 0, .flags = 0},
{ .bitrate = 20, .hw_value = 1, .flags = 0},
{ .bitrate = 55, .hw_value = 2, .flags = 0},
{ .bitrate = 110, .hw_value = 3, .flags = 0},
{ .bitrate = 60, .hw_value = 4, .flags = IEEE80211_RATE_MANDATORY_A},
{ .bitrate = 90, .hw_value = 5, .flags = IEEE80211_RATE_MANDATORY_A},
{ .bitrate = 120, .hw_value = 6, .flags = IEEE80211_RATE_MANDATORY_A},
{ .bitrate = 180, .hw_value = 7, .flags = IEEE80211_RATE_MANDATORY_A},
{ .bitrate = 240, .hw_value = 8, .flags = IEEE80211_RATE_MANDATORY_A},
{ .bitrate = 360, .hw_value = 9, .flags = IEEE80211_RATE_MANDATORY_A},
{ .bitrate = 480, .hw_value = 10, .flags = IEEE80211_RATE_MANDATORY_A},
{ .bitrate = 540, .hw_value = 11, .flags = IEEE80211_RATE_MANDATORY_A},
};
static const struct ieee80211_rate openwifi_2GHz_rates[] = {
{ .bitrate = 10, .hw_value = 0, .flags = 0},
{ .bitrate = 20, .hw_value = 1, .flags = 0},
{ .bitrate = 55, .hw_value = 2, .flags = 0},
{ .bitrate = 110, .hw_value = 3, .flags = 0},
{ .bitrate = 60, .hw_value = 4, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},
{ .bitrate = 90, .hw_value = 5, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},
{ .bitrate = 120, .hw_value = 6, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},
{ .bitrate = 180, .hw_value = 7, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},
{ .bitrate = 240, .hw_value = 8, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},
{ .bitrate = 360, .hw_value = 9, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},
{ .bitrate = 480, .hw_value = 10, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},
{ .bitrate = 540, .hw_value = 11, .flags = IEEE80211_RATE_MANDATORY_G|IEEE80211_RATE_ERP_G},
};
static const struct ieee80211_channel openwifi_2GHz_channels[] = {
CHAN2G(1, 2412, 0),
CHAN2G(2, 2417, 0),
CHAN2G(3, 2422, 0),
CHAN2G(4, 2427, 0),
CHAN2G(5, 2432, 0),
CHAN2G(6, 2437, 0),
CHAN2G(7, 2442, 0),
CHAN2G(8, 2447, 0),
CHAN2G(9, 2452, 0),
CHAN2G(10, 2457, 0),
CHAN2G(11, 2462, 0),
CHAN2G(12, 2467, 0),
CHAN2G(13, 2472, 0),
CHAN2G(14, 2484, 0),
};
static const struct ieee80211_channel openwifi_5GHz_channels[] = {
CHAN5G(36, 5180, 0),
CHAN5G(38, 5190, 0),
CHAN5G(40, 5200, 0),
CHAN5G(42, 5210, 0),
CHAN5G(44, 5220, 0),
CHAN5G(46, 5230, 0),
CHAN5G(48, 5240, 0),
CHAN5G(52, 5260, IEEE80211_CHAN_RADAR),
CHAN5G(56, 5280, IEEE80211_CHAN_RADAR),
CHAN5G(60, 5300, IEEE80211_CHAN_RADAR),
CHAN5G(64, 5320, IEEE80211_CHAN_RADAR),
// CHAN5G(100, 5500, 0),
// CHAN5G(104, 5520, 0),
// CHAN5G(108, 5540, 0),
// CHAN5G(112, 5560, 0),
// CHAN5G(116, 5580, 0),
// CHAN5G(120, 5600, 0),
// CHAN5G(124, 5620, 0),
// CHAN5G(128, 5640, 0),
// CHAN5G(132, 5660, 0),
// CHAN5G(136, 5680, 0),
// CHAN5G(140, 5700, 0),
// CHAN5G(144, 5720, 0),
// CHAN5G(149, 5745, 0),
// CHAN5G(153, 5765, 0),
// CHAN5G(157, 5785, 0),
// CHAN5G(161, 5805, 0),
// CHAN5G(165, 5825, 0),
// CHAN5G(169, 5845, 0),
};
static const struct ieee80211_iface_limit openwifi_if_limits[] = {
{ .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
{ .max = 4, .types =
#ifdef CONFIG_MAC80211_MESH
BIT(NL80211_IFTYPE_MESH_POINT) |
#endif
BIT(NL80211_IFTYPE_AP) },
};
static const struct ieee80211_iface_combination openwifi_if_comb = {
.limits = openwifi_if_limits,
.n_limits = ARRAY_SIZE(openwifi_if_limits),
.max_interfaces = 2048,
.num_different_channels = 1,
.radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
BIT(NL80211_CHAN_WIDTH_20) |
BIT(NL80211_CHAN_WIDTH_40) |
BIT(NL80211_CHAN_WIDTH_80),
};
static const u8 wifi_rate_table_mapping[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 10, 8, 6, 4, 11, 9, 7, 5};
static const u8 wifi_rate_table[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 48, 24, 12, 6, 54, 36, 18, 9};
static const u8 wifi_rate_all[16] = { 1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54, 0, 0, 0, 0};
static const u8 wifi_mcs_table_11b_force_up[16] = {11, 11, 11, 11, 11, 15, 10, 14, 9, 13, 8, 12, 0, 0, 0, 0};
static const u16 wifi_n_dbps_table[16] = {24, 24, 24, 24, 24, 36, 48, 72, 96, 144, 192, 216, 0, 0, 0, 0};
// static const u8 wifi_mcs_table[8] = {6,9,12,18,24,36,48,54};
// static const u8 wifi_mcs_table_phy_tx[8] = {11,15,10,14,9,13,8,12};
#define RX_DMA_CYCLIC_MODE
struct openwifi_priv {
struct platform_device *pdev;
struct ieee80211_vif *vif[MAX_NUM_VIF];
const struct openwifi_rf_ops *rf;
struct cf_axi_dds_state *dds_st; //axi_ad9361 hdl ref design module, dac channel
struct axiadc_state *adc_st; //axi_ad9361 hdl ref design module, adc channel
struct ad9361_rf_phy *ad9361_phy; //ad9361 chip
struct ctrl_outs_control ctrl_out;
int rx_freq_offset_to_lo_MHz;
int tx_freq_offset_to_lo_MHz;
u32 rf_bw;
u32 actual_rx_lo;
struct ieee80211_rate rates_2GHz[12];
struct ieee80211_rate rates_5GHz[12];
struct ieee80211_channel channels_2GHz[14];
struct ieee80211_channel channels_5GHz[11];
struct ieee80211_supported_band band_2GHz;
struct ieee80211_supported_band band_5GHz;
bool rfkill_off;
int rssi_correction; // dynamic RSSI correction according to current channel in _rf_set_channel()
enum rx_intf_mode rx_intf_cfg;
enum tx_intf_mode tx_intf_cfg;
enum openofdm_rx_mode openofdm_rx_cfg;
enum openofdm_tx_mode openofdm_tx_cfg;
enum xpu_mode xpu_cfg;
int irq_rx;
int irq_tx;
u8 *rx_cyclic_buf;
dma_addr_t rx_cyclic_buf_dma_mapping_addr;
struct dma_chan *rx_chan;
struct dma_async_tx_descriptor *rxd;
dma_cookie_t rx_cookie;
struct openwifi_ring tx_ring;
struct scatterlist tx_sg;
struct dma_chan *tx_chan;
struct dma_async_tx_descriptor *txd;
dma_cookie_t tx_cookie;
bool tx_queue_stopped;
int phy_tx_sn;
u32 dest_mac_addr_queue_map[MAX_NUM_HW_QUEUE];
u8 mac_addr[ETH_ALEN];
u16 seqno;
bool use_short_slot;
u8 band;
u16 channel;
u32 drv_rx_reg_val[MAX_NUM_DRV_REG];
u32 drv_tx_reg_val[MAX_NUM_DRV_REG];
u32 drv_xpu_reg_val[MAX_NUM_DRV_REG];
// u8 num_led;
// struct led_classdev *led[MAX_NUM_LED];//zc706 has 4 user leds. please find openwifi_dev_probe to see how we get them.
// char led_name[MAX_NUM_LED][OPENWIFI_LED_MAX_NAME_LEN];
spinlock_t lock;
};
#endif /* OPENWIFI_SDR */

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# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += tx_intf.o
all:
make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order

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/*
* axi lite register access driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>
#include <linux/dma/xilinx_dma.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_dma.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include "../hw_def.h"
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline u32 TX_INTF_REG_MULTI_RST_read(void){
return reg_read(TX_INTF_REG_MULTI_RST_ADDR);
}
static inline u32 TX_INTF_REG_MIXER_CFG_read(void){
return reg_read(TX_INTF_REG_MIXER_CFG_ADDR);
}
static inline u32 TX_INTF_REG_WIFI_TX_MODE_read(void){
return reg_read(TX_INTF_REG_WIFI_TX_MODE_ADDR);
}
static inline u32 TX_INTF_REG_IQ_SRC_SEL_read(void){
return reg_read(TX_INTF_REG_IQ_SRC_SEL_ADDR);
}
static inline u32 TX_INTF_REG_CTS_TOSELF_CONFIG_read(void){
return reg_read(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR);
}
static inline u32 TX_INTF_REG_START_TRANS_TO_PS_MODE_read(void){
return reg_read(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR);
}
static inline u32 TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read(void){
return reg_read(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR);
}
static inline u32 TX_INTF_REG_MISC_SEL_read(void){
return reg_read(TX_INTF_REG_MISC_SEL_ADDR);
}
static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read(void){
return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR);
}
static inline u32 TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read(void){
return reg_read(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR);
}
static inline u32 TX_INTF_REG_CFG_DATA_TO_ANT_read(void){
return reg_read(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR);
}
static inline u32 TX_INTF_REG_INTERRUPT_SEL_read(void){
return reg_read(TX_INTF_REG_INTERRUPT_SEL_ADDR);
}
static inline u32 TX_INTF_REG_BB_GAIN_read(void){
return reg_read(TX_INTF_REG_BB_GAIN_ADDR);
}
static inline u32 TX_INTF_REG_ANT_SEL_read(void){
return reg_read(TX_INTF_REG_ANT_SEL_ADDR);
}
static inline u32 TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read(void){
return reg_read(TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR);
}
static inline u32 TX_INTF_REG_PKT_INFO_read(void){
return reg_read(TX_INTF_REG_PKT_INFO_ADDR);
}
static inline u32 TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read(void){
return reg_read(TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_ADDR);
}
//--------------------------------------------------------
static inline void TX_INTF_REG_MULTI_RST_write(u32 value){
reg_write(TX_INTF_REG_MULTI_RST_ADDR, value);
}
static inline void TX_INTF_REG_MIXER_CFG_write(u32 value){
reg_write(TX_INTF_REG_MIXER_CFG_ADDR, value);
}
static inline void TX_INTF_REG_WIFI_TX_MODE_write(u32 value){
reg_write(TX_INTF_REG_WIFI_TX_MODE_ADDR, value);
}
static inline void TX_INTF_REG_IQ_SRC_SEL_write(u32 value){
reg_write(TX_INTF_REG_IQ_SRC_SEL_ADDR, value);
}
static inline void TX_INTF_REG_CTS_TOSELF_CONFIG_write(u32 value){
reg_write(TX_INTF_REG_CTS_TOSELF_CONFIG_ADDR, value);
}
static inline void TX_INTF_REG_START_TRANS_TO_PS_MODE_write(u32 value){
reg_write(TX_INTF_REG_START_TRANS_TO_PS_MODE_ADDR, value);
}
static inline void TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write(u32 value){
reg_write(TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_ADDR, value);
}
static inline void TX_INTF_REG_MISC_SEL_write(u32 value){
reg_write(TX_INTF_REG_MISC_SEL_ADDR, value);
}
static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(u32 value){
reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_ADDR, value);
}
static inline void TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(u32 value){
reg_write(TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_ADDR, value);
}
static inline void TX_INTF_REG_CFG_DATA_TO_ANT_write(u32 value){
reg_write(TX_INTF_REG_CFG_DATA_TO_ANT_ADDR, value);
}
static inline void TX_INTF_REG_INTERRUPT_SEL_write(u32 value){
reg_write(TX_INTF_REG_INTERRUPT_SEL_ADDR, value);
}
static inline void TX_INTF_REG_BB_GAIN_write(u32 value){
reg_write(TX_INTF_REG_BB_GAIN_ADDR, value);
}
static inline void TX_INTF_REG_ANT_SEL_write(u32 value){
reg_write(TX_INTF_REG_ANT_SEL_ADDR, value);
}
static inline void TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write(u32 value){
reg_write(TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_ADDR, value);
}
static inline void TX_INTF_REG_PKT_INFO_write(u32 value){
reg_write(TX_INTF_REG_PKT_INFO_ADDR,value);
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,tx_intf", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static struct tx_intf_driver_api tx_intf_driver_api_inst;
static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst;
EXPORT_SYMBOL(tx_intf_api);
static inline u32 hw_init(enum tx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){
int err=0;
u32 reg_val, mixer_cfg=0, duc_input_ch_sel = 0, ant_sel=0;
printk("%s hw_init mode %d\n", tx_intf_compatible_str, mode);
//rst duc internal module
for (reg_val=0;reg_val<32;reg_val++)
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0xFFFFFFFF);
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
switch(mode)
{
case TX_INTF_AXIS_LOOP_BACK:
tx_intf_api->TX_INTF_REG_MISC_SEL_write(0<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf
printk("%s hw_init mode TX_INTF_AXIS_LOOP_BACK\n", tx_intf_compatible_str);
break;
case TX_INTF_BW_20MHZ_AT_0MHZ_ANT0:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\n", tx_intf_compatible_str);
mixer_cfg = 0x2001F400;
duc_input_ch_sel = 0;
ant_sel=1;
break;
case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT0\n", tx_intf_compatible_str);
mixer_cfg = 0x2001F602;
duc_input_ch_sel = 0;
ant_sel=1;
break;
case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT0\n", tx_intf_compatible_str);
mixer_cfg = 0x200202F6;
duc_input_ch_sel = 0;
ant_sel=1;
break;
case TX_INTF_BW_20MHZ_AT_0MHZ_ANT1:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT1\n", tx_intf_compatible_str);
mixer_cfg = 0x2001F400;
duc_input_ch_sel = 0;
ant_sel=2;
break;
case TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1\n", tx_intf_compatible_str);
mixer_cfg = 0x2001F602;
duc_input_ch_sel = 0;
ant_sel=2;
break;
case TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1:
printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1\n", tx_intf_compatible_str);
mixer_cfg = 0x200202F6;
duc_input_ch_sel = 0;
ant_sel=2;
break;
case TX_INTF_BYPASS:
printk("%s hw_init mode TX_INTF_BYPASS\n", tx_intf_compatible_str);
mixer_cfg = 0x200202F6;
duc_input_ch_sel = 0;
ant_sel=2;
break;
default:
printk("%s hw_init mode %d is wrong!\n", tx_intf_compatible_str, mode);
err=1;
}
if (mode!=TX_INTF_AXIS_LOOP_BACK) {
tx_intf_api->TX_INTF_REG_MISC_SEL_write(1<<1);// bit1: 0-connect dac to ADI dma; 1-connect dac to our intf
tx_intf_api->TX_INTF_REG_MIXER_CFG_write(mixer_cfg);
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write(duc_input_ch_sel);
tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write(2);
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*200)<<16)|(10*200) );//high 16bit 5GHz; low 16 bit 2.4GHz
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write(num_dma_symbol_to_pl);
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0);
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x40); //.src_sel0(slv_reg14[2:0]), .src_sel1(slv_reg14[6:4]), 0-s00_axis_tlast,1-ap_start,2-tx_start_from_acc,3-tx_end_from_acc,4-xpu signal
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write(0x30040); //disable interrupt
tx_intf_api->TX_INTF_REG_BB_GAIN_write(237);
tx_intf_api->TX_INTF_REG_ANT_SEL_write(ant_sel);
tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write((1<<3)|(2<<4));
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0x434);
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
}
if (mode == TX_INTF_BYPASS) {
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8]
}
printk("%s hw_init err %d\n", tx_intf_compatible_str, err);
return(err);
}
static int dev_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *io;
int err=1;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe match!\n", tx_intf_compatible_str);
err = 0;
}
}
if (err)
return err;
tx_intf_api->hw_init=hw_init;
tx_intf_api->reg_read=reg_read;
tx_intf_api->reg_write=reg_write;
tx_intf_api->TX_INTF_REG_MULTI_RST_read=TX_INTF_REG_MULTI_RST_read;
tx_intf_api->TX_INTF_REG_MIXER_CFG_read=TX_INTF_REG_MIXER_CFG_read;
tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_read=TX_INTF_REG_WIFI_TX_MODE_read;
tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_read=TX_INTF_REG_IQ_SRC_SEL_read;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_read=TX_INTF_REG_CTS_TOSELF_CONFIG_read;
tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_read=TX_INTF_REG_START_TRANS_TO_PS_MODE_read;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_read;
tx_intf_api->TX_INTF_REG_MISC_SEL_read=TX_INTF_REG_MISC_SEL_read;
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_read;
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_read;
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_read=TX_INTF_REG_CFG_DATA_TO_ANT_read;
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_read=TX_INTF_REG_INTERRUPT_SEL_read;
tx_intf_api->TX_INTF_REG_BB_GAIN_read=TX_INTF_REG_BB_GAIN_read;
tx_intf_api->TX_INTF_REG_ANT_SEL_read=TX_INTF_REG_ANT_SEL_read;
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read=TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_read;
tx_intf_api->TX_INTF_REG_PKT_INFO_read=TX_INTF_REG_PKT_INFO_read;
tx_intf_api->TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read=TX_INTF_REG_QUEUE_FIFO_DATA_COUNT_read;
tx_intf_api->TX_INTF_REG_MULTI_RST_write=TX_INTF_REG_MULTI_RST_write;
tx_intf_api->TX_INTF_REG_MIXER_CFG_write=TX_INTF_REG_MIXER_CFG_write;
tx_intf_api->TX_INTF_REG_WIFI_TX_MODE_write=TX_INTF_REG_WIFI_TX_MODE_write;
tx_intf_api->TX_INTF_REG_IQ_SRC_SEL_write=TX_INTF_REG_IQ_SRC_SEL_write;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_CONFIG_write=TX_INTF_REG_CTS_TOSELF_CONFIG_write;
tx_intf_api->TX_INTF_REG_START_TRANS_TO_PS_MODE_write=TX_INTF_REG_START_TRANS_TO_PS_MODE_write;
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write=TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write;
tx_intf_api->TX_INTF_REG_MISC_SEL_write=TX_INTF_REG_MISC_SEL_write;
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PL_write;
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write=TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write;
tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write=TX_INTF_REG_CFG_DATA_TO_ANT_write;
tx_intf_api->TX_INTF_REG_INTERRUPT_SEL_write=TX_INTF_REG_INTERRUPT_SEL_write;
tx_intf_api->TX_INTF_REG_BB_GAIN_write=TX_INTF_REG_BB_GAIN_write;
tx_intf_api->TX_INTF_REG_ANT_SEL_write=TX_INTF_REG_ANT_SEL_write;
tx_intf_api->TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write=TX_INTF_REG_S_AXIS_FIFO_DATA_COUNT_write;
tx_intf_api->TX_INTF_REG_PKT_INFO_write=TX_INTF_REG_PKT_INFO_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%08x\n", tx_intf_compatible_str,(u32)base_addr);
printk("%s dev_probe tx_intf_driver_api_inst 0x%08x\n", tx_intf_compatible_str, (u32)(&tx_intf_driver_api_inst) );
printk("%s dev_probe tx_intf_api 0x%08x\n", tx_intf_compatible_str, (u32)tx_intf_api);
printk("%s dev_probe succeed!\n", tx_intf_compatible_str);
//err = hw_init(TX_INTF_BW_20MHZ_AT_P_10MHZ_ANT1, 8, 8);
//err = hw_init(TX_INTF_BYPASS, 8, 8);
err = hw_init(TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1, 8, 8); // make sure dac is connected to original ad9361 dma
return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove base_addr 0x%08x\n", tx_intf_compatible_str,(u32)base_addr);
printk("%s dev_remove tx_intf_driver_api_inst 0x%08x\n", tx_intf_compatible_str, (u32)(&tx_intf_driver_api_inst) );
printk("%s dev_remove tx_intf_api 0x%08x\n", tx_intf_compatible_str, (u32)tx_intf_api);
printk("%s dev_remove succeed!\n", tx_intf_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,tx_intf",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,tx_intf");
MODULE_LICENSE("GPL v2");

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driver/xilinx_dma/README.md Normal file
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Currently used driver xilinx_dma-orig.c is based on 552d3f11e374ca0d435aa93a571507819eabdda2 of https://github.com/Xilinx/linux-xlnx )
instruction to generate our customized xilinx dma driver:
./make_xilinx_dma.sh
instruction to generate our customized xilinx dma test program:
./make_xilinx_dma_test.sh
test dma driver on board: login to zc706, then:
rm axidmatest.ko
wget ftp://192.168.10.1/driver/xilinx_dma/axidmatest.ko
rm ddc.ko
wget ftp://192.168.10.1/driver/ddc/ddc.ko
rm xilinx_dma.ko
wget ftp://192.168.10.1/driver/xilinx_dma/xilinx_dma.ko
rmmod axidmatest
rmmod ddc
rmmod xilinx_dma
insmod xilinx_dma.ko
insmod ddc.ko
insmod axidmatest.ko
dmesg -c
dmesg will show test result printed by "insmod axidmatest.ko". Like this:
root@analog:~# dmesg -c
xilinx_dmatest: dropped channel dma5chan0
xilinx_dmatest: dropped channel dma5chan1
sdr,ddc dev_remove base_addr 0xf14e0000
sdr,ddc dev_remove ddc_driver_api_inst 0xbf032284
sdr,ddc dev_remove ddc_api 0xbf032284
sdr,ddc dev_remove succeed!
xilinx-vdma 43000000.axivdma: Xilinx AXI VDMA Engine Driver Probed!!
xilinx-vdma 80400000.dma: Xilinx AXI DMA Engine Driver Probed!!
xilinx-vdma 80410000.dma: Xilinx AXI DMA Engine Driver Probed!!
sdr,ddc dev_probe match!
sdr,ddc dev_probe io start 0x83c20000 end 0x83c2ffff name /fpga-axi@0/rx_intf@83c20000 flags 0x00000200 desc 0x00000000
sdr,ddc dev_probe base_addr 0xf18e0000
sdr,ddc dev_probe ddc_driver_api_inst 0xbf0e1284
sdr,ddc dev_probe ddc_api 0xbf0e1284
sdr,ddc dev_probe reset tsf timer
sdr,ddc dev_probe tsf timer runtime read 1 33007 100015us
sdr,ddc dev_probe succeed!
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
dmatest: Started 1 threads using dma5chan0 dma5chan1
align 3
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
tx_tmo 99 status 0 len 6448 DMA_COMPLETE 0
dma5chan0-dma5c: verifying source buffer...
dma5chan0-dma5c: verifying dest buffer...
dma5chan0-dma5c: #0: No errors with
src_off=0x448 dst_off=0x568 len=0x1930
align 3
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
tx_tmo 100 status 0 len 3248 DMA_COMPLETE 0
dma5chan0-dma5c: verifying source buffer...
dma5chan0-dma5c: verifying dest buffer...
dma5chan0-dma5c: #1: No errors with
src_off=0x458 dst_off=0xf08 len=0xcb0
align 3
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
tx_tmo 100 status 0 len 8112 DMA_COMPLETE 0
dma5chan0-dma5c: verifying source buffer...
dma5chan0-dma5c: verifying dest buffer...
dma5chan0-dma5c: #2: No errors with
src_off=0x10 dst_off=0x20 len=0x1fb0
align 3
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
tx_tmo 100 status 0 len 840 DMA_COMPLETE 0
dma5chan0-dma5c: verifying source buffer...
dma5chan0-dma5c: verifying dest buffer...
dma5chan0-dma5c: #3: No errors with
src_off=0x1890 dst_off=0x1268 len=0x348
align 3
sdr,ddc hw_init mode 0
sdr,ddc hw_init mode DDC_AXIS_LOOP_BACK
sdr,ddc hw_init err 0
tx_tmo 100 status 0 len 7816 DMA_COMPLETE 0
dma5chan0-dma5c: verifying source buffer...
dma5chan0-dma5c: verifying dest buffer...
dma5chan0-dma5c: #4: No errors with
src_off=0x80 dst_off=0x168 len=0x1e88
dma5chan0-dma5c: terminating after 5 tests, 0 failures (status 0)

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driver/xilinx_dma/make_xilinx_dma.sh Executable file
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#!/bin/bash
set -x
WORKDIR=$PWD
KDIR=$1
SUBMODULE=xilinx_dma
source $2
export ARCH=arm
export CROSS_COMPILE=arm-linux-gnueabihf-
cp xilinx_dma.c $KDIR/drivers/dma/xilinx -rf
cd $KDIR
make $KDIR/drivers/dma/xilinx/$SUBMODULE.ko
cp $KDIR/drivers/dma/xilinx/$SUBMODULE.ko $WORKDIR -rf
cd $WORKDIR
ls $SUBMODULE.ko

2855
driver/xilinx_dma/xilinx_dma.c Normal file
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File diff suppressed because it is too large Load Diff

10
driver/xpu/Makefile Normal file
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# by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
obj-m += xpu.o
all:
make -C $(KDIR) M=$(PWD) modules ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
clean:
rm -f *.ko *.o *.mod.o *.mod.c *.symvers *.order

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driver/xpu/xpu.c Normal file
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/*
* axi lite register access driver
* Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
*/
#include <linux/bitops.h>
#include <linux/dmapool.h>
#include <linux/dma/xilinx_dma.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_dma.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/delay.h>
#include <net/mac80211.h>
#include "../hw_def.h"
static void __iomem *base_addr; // to store driver specific base address needed for mmu to translate virtual address to physical address in our FPGA design
/* IO accessors */
static inline u32 reg_read(u32 reg)
{
return ioread32(base_addr + reg);
}
static inline void reg_write(u32 reg, u32 value)
{
iowrite32(value, base_addr + reg);
}
static inline void XPU_REG_MULTI_RST_write(u32 Data) {
reg_write(XPU_REG_MULTI_RST_ADDR, Data);
}
static inline u32 XPU_REG_MULTI_RST_read(void){
return reg_read(XPU_REG_MULTI_RST_ADDR);
}
static inline void XPU_REG_SRC_SEL_write(u32 Data) {
reg_write(XPU_REG_SRC_SEL_ADDR, Data);
}
static inline u32 XPU_REG_SRC_SEL_read(void){
return reg_read(XPU_REG_SRC_SEL_ADDR);
}
static inline void XPU_REG_RECV_ACK_COUNT_TOP0_write(u32 Data) {
reg_write(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR, Data);
}
static inline u32 XPU_REG_RECV_ACK_COUNT_TOP0_read(void){
return reg_read(XPU_REG_RECV_ACK_COUNT_TOP0_ADDR);
}
static inline void XPU_REG_RECV_ACK_COUNT_TOP1_write(u32 Data) {
reg_write(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR, Data);
}
static inline u32 XPU_REG_RECV_ACK_COUNT_TOP1_read(void){
return reg_read(XPU_REG_RECV_ACK_COUNT_TOP1_ADDR);
}
static inline void XPU_REG_SEND_ACK_WAIT_TOP_write(u32 Data) {
reg_write(XPU_REG_SEND_ACK_WAIT_TOP_ADDR, Data);
}
static inline u32 XPU_REG_SEND_ACK_WAIT_TOP_read(void){
return reg_read(XPU_REG_SEND_ACK_WAIT_TOP_ADDR);
}
static inline void XPU_REG_FILTER_FLAG_write(u32 Data) {
reg_write(XPU_REG_FILTER_FLAG_ADDR, Data);
}
static inline u32 XPU_REG_FILTER_FLAG_read(void){
return reg_read(XPU_REG_FILTER_FLAG_ADDR);
}
static inline void XPU_REG_CTS_TO_RTS_CONFIG_write(u32 Data) {
reg_write(XPU_REG_CTS_TO_RTS_CONFIG_ADDR, Data);
}
static inline u32 XPU_REG_CTS_TO_RTS_CONFIG_read(void){
return reg_read(XPU_REG_CTS_TO_RTS_CONFIG_ADDR);
}
static inline void XPU_REG_MAC_ADDR_LOW_write(u32 Data) {
reg_write(XPU_REG_MAC_ADDR_LOW_ADDR, Data);
}
static inline u32 XPU_REG_MAC_ADDR_LOW_read(void){
return reg_read(XPU_REG_MAC_ADDR_LOW_ADDR);
}
static inline void XPU_REG_MAC_ADDR_HIGH_write(u32 Data) {
reg_write(XPU_REG_MAC_ADDR_HIGH_ADDR, Data);
}
static inline u32 XPU_REG_MAC_ADDR_HIGH_read(void){
return reg_read(XPU_REG_MAC_ADDR_HIGH_ADDR);
}
static inline void XPU_REG_BSSID_FILTER_LOW_write(u32 Data) {
reg_write(XPU_REG_BSSID_FILTER_LOW_ADDR, Data);
}
static inline u32 XPU_REG_BSSID_FILTER_LOW_read(void){
return reg_read(XPU_REG_BSSID_FILTER_LOW_ADDR);
}
static inline void XPU_REG_BSSID_FILTER_HIGH_write(u32 Data) {
reg_write(XPU_REG_BSSID_FILTER_HIGH_ADDR, Data);
}
static inline u32 XPU_REG_BSSID_FILTER_HIGH_read(void){
return reg_read(XPU_REG_BSSID_FILTER_HIGH_ADDR);
}
static inline void XPU_REG_BAND_CHANNEL_write(u32 Data) {
reg_write(XPU_REG_BAND_CHANNEL_ADDR, Data);
}
static inline u32 XPU_REG_BAND_CHANNEL_read(void){
return reg_read(XPU_REG_BAND_CHANNEL_ADDR);
}
static inline u32 XPU_REG_TRX_STATUS_read(void){
return reg_read(XPU_REG_TRX_STATUS_ADDR);
}
static inline u32 XPU_REG_TX_RESULT_read(void){
return reg_read(XPU_REG_TX_RESULT_ADDR);
}
static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){
return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR);
}
static inline u32 XPU_REG_TSF_RUNTIME_VAL_HIGH_read(void){
return reg_read(XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR);
}
static inline void XPU_REG_TSF_LOAD_VAL_LOW_write(u32 value){
reg_write(XPU_REG_TSF_LOAD_VAL_LOW_ADDR, value);
}
static inline void XPU_REG_TSF_LOAD_VAL_HIGH_write(u32 value){
reg_write(XPU_REG_TSF_LOAD_VAL_HIGH_ADDR, value);
}
static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){
XPU_REG_TSF_LOAD_VAL_LOW_write(low_value);
XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value|0x80000000); // msb high
XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low
}
static inline u32 XPU_REG_FC_DI_read(void){
return reg_read(XPU_REG_FC_DI_ADDR);
}
static inline u32 XPU_REG_ADDR1_LOW_read(void){
return reg_read(XPU_REG_ADDR1_LOW_ADDR);
}
static inline u32 XPU_REG_ADDR1_HIGH_read(void){
return reg_read(XPU_REG_ADDR1_HIGH_ADDR);
}
static inline u32 XPU_REG_ADDR2_LOW_read(void){
return reg_read(XPU_REG_ADDR2_LOW_ADDR);
}
static inline u32 XPU_REG_ADDR2_HIGH_read(void){
return reg_read(XPU_REG_ADDR2_HIGH_ADDR);
}
// static inline void XPU_REG_LBT_TH_write(u32 value, u32 en_flag) {
// if (en_flag) {
// reg_write(XPU_REG_LBT_TH_ADDR, value&0x7FFFFFFF);
// } else {
// reg_write(XPU_REG_LBT_TH_ADDR, value|0x80000000);
// }
// }
static inline void XPU_REG_LBT_TH_write(u32 value) {
reg_write(XPU_REG_LBT_TH_ADDR, value);
}
static inline u32 XPU_REG_RSSI_DB_CFG_read(void){
return reg_read(XPU_REG_RSSI_DB_CFG_ADDR);
}
static inline void XPU_REG_RSSI_DB_CFG_write(u32 Data) {
reg_write(XPU_REG_RSSI_DB_CFG_ADDR, Data);
}
static inline u32 XPU_REG_LBT_TH_read(void){
return reg_read(XPU_REG_LBT_TH_ADDR);
}
static inline void XPU_REG_CSMA_DEBUG_write(u32 value){
reg_write(XPU_REG_CSMA_DEBUG_ADDR, value);
}
static inline u32 XPU_REG_CSMA_DEBUG_read(void){
return reg_read(XPU_REG_CSMA_DEBUG_ADDR);
}
static inline void XPU_REG_CSMA_CFG_write(u32 value){
reg_write(XPU_REG_CSMA_CFG_ADDR, value);
}
static inline u32 XPU_REG_CSMA_CFG_read(void){
return reg_read(XPU_REG_CSMA_CFG_ADDR);
}
static inline void XPU_REG_SLICE_COUNT_TOTAL0_write(u32 value){
reg_write(XPU_REG_SLICE_COUNT_TOTAL0_ADDR, value);
}
static inline void XPU_REG_SLICE_COUNT_START0_write(u32 value){
reg_write(XPU_REG_SLICE_COUNT_START0_ADDR, value);
}
static inline void XPU_REG_SLICE_COUNT_END0_write(u32 value){
reg_write(XPU_REG_SLICE_COUNT_END0_ADDR, value);
}
static inline void XPU_REG_SLICE_COUNT_TOTAL1_write(u32 value){
reg_write(XPU_REG_SLICE_COUNT_TOTAL1_ADDR, value);
}
static inline void XPU_REG_SLICE_COUNT_START1_write(u32 value){
reg_write(XPU_REG_SLICE_COUNT_START1_ADDR, value);
}
static inline void XPU_REG_SLICE_COUNT_END1_write(u32 value){
reg_write(XPU_REG_SLICE_COUNT_END1_ADDR, value);
}
static inline u32 XPU_REG_SLICE_COUNT_TOTAL0_read(void){
return reg_read(XPU_REG_SLICE_COUNT_TOTAL0_ADDR);
}
static inline u32 XPU_REG_SLICE_COUNT_START0_read(void){
return reg_read(XPU_REG_SLICE_COUNT_START0_ADDR);
}
static inline u32 XPU_REG_SLICE_COUNT_END0_read(void){
return reg_read(XPU_REG_SLICE_COUNT_END0_ADDR);
}
static inline u32 XPU_REG_SLICE_COUNT_TOTAL1_read(void){
return reg_read(XPU_REG_SLICE_COUNT_TOTAL1_ADDR);
}
static inline u32 XPU_REG_SLICE_COUNT_START1_read(void){
return reg_read(XPU_REG_SLICE_COUNT_START1_ADDR);
}
static inline u32 XPU_REG_SLICE_COUNT_END1_read(void){
return reg_read(XPU_REG_SLICE_COUNT_END1_ADDR);
}
static inline void XPU_REG_BB_RF_DELAY_write(u32 value){
reg_write(XPU_REG_BB_RF_DELAY_ADDR, value);
}
static inline void XPU_REG_MAX_NUM_RETRANS_write(u32 value){
reg_write(XPU_REG_MAX_NUM_RETRANS_ADDR, value);
}
static inline void XPU_REG_MAC_ADDR_write(u8 *mac_addr) {//, u32 en_flag){
XPU_REG_MAC_ADDR_LOW_write( *( (u32*)(mac_addr) ) );
XPU_REG_MAC_ADDR_HIGH_write( *( (u16*)(mac_addr + 4) ) );
#if 0
if (en_flag) {
XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) | 0x80000000 ); // 0x80000000 by default we turn on mac addr filter
} else {
XPU_REG_MAC_ADDR_HIGH_write( (*( (u16*)(mac_addr + 4) )) & 0x7FFFFFFF );
}
#endif
}
static const struct of_device_id dev_of_ids[] = {
{ .compatible = "sdr,xpu", },
{}
};
MODULE_DEVICE_TABLE(of, dev_of_ids);
static struct xpu_driver_api xpu_driver_api_inst;
static struct xpu_driver_api *xpu_api = &xpu_driver_api_inst;
EXPORT_SYMBOL(xpu_api);
static inline u32 hw_init(enum xpu_mode mode){
int err=0, rssi_half_db_th, rssi_half_db_offset, agc_gain_delay;
u32 reg_val;
u32 filter_flag = 0;
printk("%s hw_init mode %d\n", xpu_compatible_str, mode);
//rst internal module
for (reg_val=0;reg_val<32;reg_val++)
xpu_api->XPU_REG_MULTI_RST_write(0xFFFFFFFF);
xpu_api->XPU_REG_MULTI_RST_write(0);
// http://www.studioreti.it/slide/802-11-Frame_E_C.pdf
// https://mrncciew.com/2014/10/14/cwap-802-11-phy-ppdu/
// https://mrncciew.com/2014/09/27/cwap-mac-header-frame-control/
// https://mrncciew.com/2014/10/25/cwap-mac-header-durationid/
// https://mrncciew.com/2014/11/01/cwap-mac-header-sequence-control/
// https://witestlab.poly.edu/blog/802-11-wireless-lan-2/
// phy_rx byte idx:
// 5(3 sig + 2 service), -- PHY
// 2 frame control, 2 duration/conn ID, --MAC PDU
// 6 receiver address, 6 destination address, 6 transmitter address
// 2 sequence control
// 6 source address
// reg_val = 5 + 0;
// xpu_api->XPU_REG_PHY_RX_PKT_READ_OFFSET_write(reg_val);
// printk("%s hw_init XPU_REG_PHY_RX_PKT_READ_OFFSET_write %d\n", xpu_compatible_str, reg_val);
// by default turn off filter, because all register are zeros
// let's filter out packet according to: enum ieee80211_filter_flags at: https://www.kernel.org/doc/html/v4.9/80211/mac80211.html
#if 0 // define in FPGA
localparam [13:0] FIF_ALLMULTI = 14b00000000000010, //get all mac addr like 01:00:5E:xx:xx:xx and 33:33:xx:xx:xx:xx through to ARM
FIF_FCSFAIL = 14b00000000000100, //not support
FIF_PLCPFAIL = 14b00000000001000, //not support
FIF_BCN_PRBRESP_PROMISC= 14b00000000010000,
FIF_CONTROL = 14b00000000100000,
FIF_OTHER_BSS = 14b00000001000000,
FIF_PSPOLL = 14b00000010000000,
FIF_PROBE_REQ = 14b00000100000000,
UNICAST_FOR_US = 14b00001000000000,
BROADCAST_ALL_ONE = 14b00010000000000,
BROADCAST_ALL_ZERO = 14b00100000000000,
MY_BEACON = 14b01000000000000,
MONITOR_ALL = 14b10000000000000;
#endif
filter_flag = (FIF_ALLMULTI|FIF_FCSFAIL|FIF_PLCPFAIL|FIF_BCN_PRBRESP_PROMISC|FIF_CONTROL|FIF_OTHER_BSS|FIF_PSPOLL|FIF_PROBE_REQ|UNICAST_FOR_US|BROADCAST_ALL_ONE|BROADCAST_ALL_ZERO|MY_BEACON|MONITOR_ALL);
xpu_api->XPU_REG_FILTER_FLAG_write(filter_flag);
xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write(0xB<<16);//6M 1011:0xB
////set up FC type filter for packet needs ACK -- no use, FPGA handle by itself
//xpu_api->XPU_REG_ACK_FC_FILTER_write((3<<(2+16))|(2<<2)); // low 16 bits target FC 16 bits; high 16 bits -- mask
// after send data frame wait for ACK, this will be set in real time in function ad9361_rf_set_channel
// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*200)<<16) | 200 ); // high 16 bits to cover sig valid of ACK packet, low 16 bits is adjustment of fcs valid waiting time. let's add 2us for those device that is really "slow"!
// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( 1200 ); // +6 = 16us for 5GHz
//xpu_api->XPU_REG_MAX_NUM_RETRANS_write(3); // if this > 0, it will override mac80211 set value, and set static retransmission limit
xpu_api->XPU_REG_BB_RF_DELAY_write(975);
xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_write(50000-1); // total 50ms
xpu_api->XPU_REG_SLICE_COUNT_START0_write(0); //start 0ms
xpu_api->XPU_REG_SLICE_COUNT_END0_write(50000-1); //end 10ms
xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_write(50000-1); // total 50ms
xpu_api->XPU_REG_SLICE_COUNT_START1_write(0000); //start 0ms
xpu_api->XPU_REG_SLICE_COUNT_END1_write(1000-1); //end 1ms
switch(mode)
{
case XPU_TEST:
printk("%s hw_init mode XPU_TEST\n", xpu_compatible_str);
break;
case XPU_NORMAL:
printk("%s hw_init mode XPU_NORMAL\n", xpu_compatible_str);
break;
default:
printk("%s hw_init mode %d is wrong!\n", xpu_compatible_str, mode);
err=1;
}
xpu_api->XPU_REG_BAND_CHANNEL_write((false<<24)|(BAND_5_8GHZ<<16)|44);//use_short_slot==false; 5.8GHz; channel 44 -- default setting to sync with priv->band/channel/use_short_slot
agc_gain_delay = 50; //samples
rssi_half_db_offset = 75<<1;
xpu_api->XPU_REG_RSSI_DB_CFG_write(0x80000000|((rssi_half_db_offset<<16)|agc_gain_delay) );
xpu_api->XPU_REG_RSSI_DB_CFG_write((~0x80000000)&((rssi_half_db_offset<<16)|agc_gain_delay) );
//rssi_half_db_th = 70<<1; // with splitter
rssi_half_db_th = 87<<1; // -62dBm
xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it
//xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5));
xpu_api->XPU_REG_CSMA_DEBUG_write(0);
//xpu_api->XPU_REG_CSMA_CFG_write(3); //normal CSMA
xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); //high priority
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((1030-238)<<16)|0 );//high 16bit 5GHz; low 16 bit 2.4GHz (Attention, current tx core has around 1.19us starting delay that makes the ack fall behind 10us SIFS in 2.4GHz! Need to improve TX in 2.4GHz!)
//xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+2)*200)<<16) | 400 );//2.4GHz
//xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2+2)*200)<<16) | 400 );//5GHz
// // value from openwifi-preo csma_test
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (((45+2+6)*200)<<16) | 200 );//2.4GHz, still need to find out why sometimes the PI in ad-hoc 2.4GHz mode give ack so slow: 18us
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (((51+2)*200)<<16) | 200 );//5GHz
printk("%s hw_init err %d\n", xpu_compatible_str, err);
return(err);
}
static int dev_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *io;
u32 test_us0, test_us1, test_us2;
int err=1;
printk("\n");
if (np) {
const struct of_device_id *match;
match = of_match_node(dev_of_ids, np);
if (match) {
printk("%s dev_probe match!\n", xpu_compatible_str);
err = 0;
}
}
if (err)
return err;
xpu_api->hw_init=hw_init;
xpu_api->reg_read=reg_read;
xpu_api->reg_write=reg_write;
xpu_api->XPU_REG_MULTI_RST_write=XPU_REG_MULTI_RST_write;
xpu_api->XPU_REG_MULTI_RST_read=XPU_REG_MULTI_RST_read;
xpu_api->XPU_REG_SRC_SEL_write=XPU_REG_SRC_SEL_write;
xpu_api->XPU_REG_SRC_SEL_read=XPU_REG_SRC_SEL_read;
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write=XPU_REG_RECV_ACK_COUNT_TOP0_write;
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_read=XPU_REG_RECV_ACK_COUNT_TOP0_read;
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write=XPU_REG_RECV_ACK_COUNT_TOP1_write;
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_read=XPU_REG_RECV_ACK_COUNT_TOP1_read;
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write=XPU_REG_SEND_ACK_WAIT_TOP_write;
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_read=XPU_REG_SEND_ACK_WAIT_TOP_read;
xpu_api->XPU_REG_MAC_ADDR_LOW_write=XPU_REG_MAC_ADDR_LOW_write;
xpu_api->XPU_REG_MAC_ADDR_LOW_read=XPU_REG_MAC_ADDR_LOW_read;
xpu_api->XPU_REG_MAC_ADDR_HIGH_write=XPU_REG_MAC_ADDR_HIGH_write;
xpu_api->XPU_REG_MAC_ADDR_HIGH_read=XPU_REG_MAC_ADDR_HIGH_read;
xpu_api->XPU_REG_FILTER_FLAG_write=XPU_REG_FILTER_FLAG_write;
xpu_api->XPU_REG_FILTER_FLAG_read=XPU_REG_FILTER_FLAG_read;
xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_write=XPU_REG_CTS_TO_RTS_CONFIG_write;
xpu_api->XPU_REG_CTS_TO_RTS_CONFIG_read=XPU_REG_CTS_TO_RTS_CONFIG_read;
xpu_api->XPU_REG_BSSID_FILTER_LOW_write=XPU_REG_BSSID_FILTER_LOW_write;
xpu_api->XPU_REG_BSSID_FILTER_LOW_read=XPU_REG_BSSID_FILTER_LOW_read;
xpu_api->XPU_REG_BSSID_FILTER_HIGH_write=XPU_REG_BSSID_FILTER_HIGH_write;
xpu_api->XPU_REG_BSSID_FILTER_HIGH_read=XPU_REG_BSSID_FILTER_HIGH_read;
xpu_api->XPU_REG_BAND_CHANNEL_write=XPU_REG_BAND_CHANNEL_write;
xpu_api->XPU_REG_BAND_CHANNEL_read=XPU_REG_BAND_CHANNEL_read;
xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read;
xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read;
xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read;
xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read;
xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write;
xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write;
xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write;
xpu_api->XPU_REG_FC_DI_read=XPU_REG_FC_DI_read;
xpu_api->XPU_REG_ADDR1_LOW_read=XPU_REG_ADDR1_LOW_read;
xpu_api->XPU_REG_ADDR1_HIGH_read=XPU_REG_ADDR1_HIGH_read;
xpu_api->XPU_REG_ADDR2_LOW_read=XPU_REG_ADDR2_LOW_read;
xpu_api->XPU_REG_ADDR2_HIGH_read=XPU_REG_ADDR2_HIGH_read;
xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write;
xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read;
xpu_api->XPU_REG_RSSI_DB_CFG_read=XPU_REG_RSSI_DB_CFG_read;
xpu_api->XPU_REG_RSSI_DB_CFG_write=XPU_REG_RSSI_DB_CFG_write;
xpu_api->XPU_REG_CSMA_DEBUG_write=XPU_REG_CSMA_DEBUG_write;
xpu_api->XPU_REG_CSMA_DEBUG_read=XPU_REG_CSMA_DEBUG_read;
xpu_api->XPU_REG_CSMA_CFG_write=XPU_REG_CSMA_CFG_write;
xpu_api->XPU_REG_CSMA_CFG_read=XPU_REG_CSMA_CFG_read;
xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_write=XPU_REG_SLICE_COUNT_TOTAL0_write;
xpu_api->XPU_REG_SLICE_COUNT_START0_write=XPU_REG_SLICE_COUNT_START0_write;
xpu_api->XPU_REG_SLICE_COUNT_END0_write=XPU_REG_SLICE_COUNT_END0_write;
xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_write=XPU_REG_SLICE_COUNT_TOTAL1_write;
xpu_api->XPU_REG_SLICE_COUNT_START1_write=XPU_REG_SLICE_COUNT_START1_write;
xpu_api->XPU_REG_SLICE_COUNT_END1_write=XPU_REG_SLICE_COUNT_END1_write;
xpu_api->XPU_REG_SLICE_COUNT_TOTAL0_read=XPU_REG_SLICE_COUNT_TOTAL0_read;
xpu_api->XPU_REG_SLICE_COUNT_START0_read=XPU_REG_SLICE_COUNT_START0_read;
xpu_api->XPU_REG_SLICE_COUNT_END0_read=XPU_REG_SLICE_COUNT_END0_read;
xpu_api->XPU_REG_SLICE_COUNT_TOTAL1_read=XPU_REG_SLICE_COUNT_TOTAL1_read;
xpu_api->XPU_REG_SLICE_COUNT_START1_read=XPU_REG_SLICE_COUNT_START1_read;
xpu_api->XPU_REG_SLICE_COUNT_END1_read=XPU_REG_SLICE_COUNT_END1_read;
xpu_api->XPU_REG_BB_RF_DELAY_write=XPU_REG_BB_RF_DELAY_write;
xpu_api->XPU_REG_MAX_NUM_RETRANS_write=XPU_REG_MAX_NUM_RETRANS_write;
xpu_api->XPU_REG_MAC_ADDR_write=XPU_REG_MAC_ADDR_write;
/* Request and map I/O memory */
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_addr = devm_ioremap_resource(&pdev->dev, io);
if (IS_ERR(base_addr))
return PTR_ERR(base_addr);
printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", xpu_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
printk("%s dev_probe base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr);
printk("%s dev_probe xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst);
printk("%s dev_probe xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api);
printk("%s dev_probe reset tsf timer\n", xpu_compatible_str);
xpu_api->XPU_REG_TSF_LOAD_VAL_write(0,0);
test_us0 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();
mdelay(33);
test_us1 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();
mdelay(67);
test_us2 = xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read();
printk("%s dev_probe XPU_REG_TSF_RUNTIME_VAL_LOW_read %d %d %dus\n", xpu_compatible_str, test_us0, test_us1, test_us2);
printk("%s dev_probe succeed!\n", xpu_compatible_str);
err = hw_init(XPU_NORMAL);
return err;
}
static int dev_remove(struct platform_device *pdev)
{
printk("\n");
printk("%s dev_remove base_addr 0x%08x\n", xpu_compatible_str,(u32)base_addr);
printk("%s dev_remove xpu_driver_api_inst 0x%08x\n", xpu_compatible_str, (u32)&xpu_driver_api_inst);
printk("%s dev_remove xpu_api 0x%08x\n", xpu_compatible_str, (u32)xpu_api);
printk("%s dev_remove succeed!\n", xpu_compatible_str);
return 0;
}
static struct platform_driver dev_driver = {
.driver = {
.name = "sdr,xpu",
.owner = THIS_MODULE,
.of_match_table = dev_of_ids,
},
.probe = dev_probe,
.remove = dev_remove,
};
module_platform_driver(dev_driver);
MODULE_AUTHOR("Xianjun Jiao");
MODULE_DESCRIPTION("sdr,xpu");
MODULE_LICENSE("GPL v2");

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SUBSYSTEM=="net", ACTION=="add", DRIVERS=="?*", ATTR{address}=="66:55:44:33:22:*", ATTR{dev_id}=="0x0", ATTR{type}=="1", KERNEL=="wlan*", NAME="sdr0"

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#!/bin/bash
set -ex
HDF_FILE=$1
UBOOT_FILE=$2
BUILD_DIR=build_boot_bin
OUTPUT_DIR=output_boot_bin
usage () {
echo usage: $0 system_top.hdf u-boot.elf [output-archive]
exit 1
}
depends () {
echo Xilinx $1 must be installed and in your PATH
echo try: source /opt/Xilinx/Vivado/201x.x/settings64.sh
exit 1
}
### Check command line parameters
echo $HDF_FILE | grep -q ".hdf" || usage
echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" || usage
if [ ! -f $HDF_FILE ]; then
echo $HDF_FILE: File not found!
usage
fi
if [ ! -f $UBOOT_FILE ]; then
echo $UBOOT_FILE: File not found!
usage
fi
### Check for required Xilinx tools
command -v xsdk >/dev/null 2>&1 || depends xsdk
command -v bootgen >/dev/null 2>&1 || depends bootgen
rm -Rf $BUILD_DIR $OUTPUT_DIR
mkdir -p $OUTPUT_DIR
mkdir -p $BUILD_DIR
cp $HDF_FILE $BUILD_DIR/
cp $UBOOT_FILE $OUTPUT_DIR/u-boot.elf
cp $HDF_FILE $OUTPUT_DIR/
### Create create_fsbl_project.tcl file used by xsdk to create the fsbl
echo "hsi open_hw_design `basename $HDF_FILE`" > $BUILD_DIR/create_fsbl_project.tcl
echo 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl
echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl
echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl
echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl
echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl
echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl
### Create zynq.bif file used by bootgen
echo 'the_ROM_image:' > $OUTPUT_DIR/zynq.bif
echo '{' >> $OUTPUT_DIR/zynq.bif
echo '[bootloader] fsbl.elf' >> $OUTPUT_DIR/zynq.bif
echo 'system_top.bit' >> $OUTPUT_DIR/zynq.bif
echo 'u-boot.elf' >> $OUTPUT_DIR/zynq.bif
echo '}' >> $OUTPUT_DIR/zynq.bif
### Build fsbl.elf
(
cd $BUILD_DIR
xsdk -batch -source create_fsbl_project.tcl
)
### Copy fsbl and system_top.bit into the output folder
cp $BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf $OUTPUT_DIR/fsbl.elf
cp $BUILD_DIR/build/sdk/hw_0/system_top.bit $OUTPUT_DIR/system_top.bit
### Build BOOT.BIN
(
cd $OUTPUT_DIR
bootgen -arch zynq -image zynq.bif -o BOOT.BIN -w
)
### clean up BUILD_DIR and copy ILA definition together with .bit into OUTPUT_DIR
(
rm $BUILD_DIR -rf
)
### Optionally tar.gz the entire output folder with the name given in argument 3
if [ ${#3} -ne 0 ]; then
tar czvf $3.tar.gz $OUTPUT_DIR
fi

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#
# Sample configuration file for ISC dhcpd for Debian
#
# Attention: If /etc/ltsp/dhcpd.conf exists, that will be used as
# configuration file instead of this file.
#
#
# The ddns-updates-style parameter controls whether or not the server will
# attempt to do a DNS update when a lease is confirmed. We default to the
# behavior of the version 2 packages ('none', since DHCP v2 didn't
# have support for DDNS.)
ddns-update-style none;
# option definitions common to all supported networks...
option domain-name "orca-project.eu";
#option domain-name-servers ns1.example.org, ns2.example.org;
default-lease-time 600;
max-lease-time 7200;
# If this DHCP server is the official DHCP server for the local
# network, the authoritative directive should be uncommented.
#authoritative;
# Use this to send dhcp log messages to a different log file (you also
# have to hack syslog.conf to complete the redirection).
log-facility local7;
# No service will be given on this subnet, but declaring it helps the
# DHCP server to understand the network topology.
option subnet-mask 255.255.255.0;
option broadcast-address 192.168.13.255;
option routers 192.168.13.1;
option domain-name-servers 8.8.8.8, 4.4.4.4;
option domain-name "mydomain.example";
subnet 192.168.13.0 netmask 255.255.255.0 {
# default-lease-time 6000;
# max-lease-time 7200;
option routers 192.168.13.1;
range 192.168.13.2 192.168.13.254;
}
#subnet 10.152.187.0 netmask 255.255.255.0 {
#}
# This is a very basic subnet declaration.
#subnet 10.254.239.0 netmask 255.255.255.224 {
# range 10.254.239.10 10.254.239.20;
# option routers rtr-239-0-1.example.org, rtr-239-0-2.example.org;
#}
# This declaration allows BOOTP clients to get dynamic addresses,
# which we don't really recommend.
#subnet 10.254.239.32 netmask 255.255.255.224 {
# range dynamic-bootp 10.254.239.40 10.254.239.60;
# option broadcast-address 10.254.239.31;
# option routers rtr-239-32-1.example.org;
#}
# A slightly different configuration for an internal subnet.
#subnet 10.5.5.0 netmask 255.255.255.224 {
# range 10.5.5.26 10.5.5.30;
# option domain-name-servers ns1.internal.example.org;
# option domain-name "internal.example.org";
# option routers 10.5.5.1;
# option broadcast-address 10.5.5.31;
# default-lease-time 600;
# max-lease-time 7200;
#}
# Hosts which require special configuration options can be listed in
# host statements. If no address is specified, the address will be
# allocated dynamically (if possible), but the host-specific information
# will still come from the host declaration.
#host passacaglia {
# hardware ethernet 0:0:c0:5d:bd:95;
# filename "vmunix.passacaglia";
# server-name "toccata.fugue.com";
#}
# Fixed IP addresses can also be specified for hosts. These addresses
# should not also be listed as being available for dynamic assignment.
# Hosts for which fixed IP addresses have been specified can boot using
# BOOTP or DHCP. Hosts for which no fixed address is specified can only
# be booted with DHCP, unless there is an address range on the subnet
# to which a BOOTP client is connected which has the dynamic-bootp flag
# set.
#host fantasia {
# hardware ethernet 08:00:07:26:c0:a5;
# fixed-address fantasia.fugue.com;
#}
# You can declare a class of clients and then do address allocation
# based on that. The example below shows a case where all clients
# in a certain class get addresses on the 10.17.224/24 subnet, and all
# other clients get addresses on the 10.0.29/24 subnet.
#class "foo" {
# match if substring (option vendor-class-identifier, 0, 4) = "SUNW";
#}
#shared-network 224-29 {
# subnet 10.17.224.0 netmask 255.255.255.0 {
# option routers rtr-224.example.org;
# }
# subnet 10.0.29.0 netmask 255.255.255.0 {
# option routers rtr-29.example.org;
# }
# pool {
# allow members of "foo";
# range 10.17.224.10 10.17.224.250;
# }
# pool {
# deny members of "foo";
# range 10.0.29.10 10.0.29.230;
# }
#}

11
user_space/hostapd-openwifi.conf Normal file
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interface=sdr0
driver=nl80211
country_code=BE
ssid=openwifi
hw_mode=a
channel=44
#ieee80211d=1
#ieee80211h=1
#wpa=2
#wpa_passphrase=myrabbit
#wpa_key_mgmt=WPA-PSK

23
user_space/monitor_ch.sh Executable file
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#!/bin/bash
if [ $# -ne 2 ]
then
echo "Please input NIC_name ch_number as input parameter!"
exit
fi
nic_name=$1
ch_number=$2
echo $nic_name
echo $ch_number
# sudo service network-manager stop
sudo ip link set $nic_name down
sudo iwconfig $nic_name mode monitor
sudo ip link set $nic_name up
sudo iwconfig $nic_name channel $ch_number
# sudo iwconfig $nic_name modulation 11g
# sudo iwconfig $nic_name rate 6M
ifconfig
iwconfig $nic_name

19
user_space/nic_back_to_normal.sh Executable file
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#!/bin/bash
if [ $# -ne 1 ]
then
echo "Please input NIC name as input parameter!"
exit
fi
nic_name=$1
echo $nic_name
# sudo service network-manager stop
sudo ip link set $nic_name down
sudo iwconfig $nic_name mode managed
#sudo iwconfig $nic_name modulation 11g
sudo ip link set $nic_name up
ifconfig
iwconfig $nic_name

100
user_space/rf_init.sh Executable file
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#!/bin/sh
home_dir=$(pwd)
cd /sys/bus/iio/devices/iio:device2
echo "rx bw"
cat in_voltage_rf_bandwidth
#echo 37500000 > in_voltage_rf_bandwidth
echo 17500000 > in_voltage_rf_bandwidth
cat in_voltage_rf_bandwidth
sync
echo "tx_bw"
cat out_voltage_rf_bandwidth
echo 37500000 > out_voltage_rf_bandwidth
#echo 40000000 > out_voltage_rf_bandwidth
#echo 20000000 > out_voltage_rf_bandwidth
cat out_voltage_rf_bandwidth
sync
#sleep 0.5
echo "rx rate"
cat in_voltage_sampling_frequency
echo 40000000 > in_voltage_sampling_frequency
#echo 20000000 > in_voltage_sampling_frequency
cat in_voltage_sampling_frequency
sync
echo "tx rate"
cat out_voltage_sampling_frequency
echo 40000000 > out_voltage_sampling_frequency
#echo 20000000 > out_voltage_sampling_frequency
cat out_voltage_sampling_frequency
sync
sleep 1
echo "rx lo"
cat out_altvoltage0_RX_LO_frequency
#echo 2427000000 > out_altvoltage0_RX_LO_frequency
echo 5240000000 > out_altvoltage0_RX_LO_frequency
#echo 2320000000 > out_altvoltage0_RX_LO_frequency
cat out_altvoltage0_RX_LO_frequency
sync
echo "tx lo"
cat out_altvoltage1_TX_LO_frequency
#echo 2447000000 > out_altvoltage1_TX_LO_frequency
echo 5250000000 > out_altvoltage1_TX_LO_frequency
#echo 2320000000 > out_altvoltage1_TX_LO_frequency
cat out_altvoltage1_TX_LO_frequency
sync
#sleep 1
echo "rx0 agc fast_attack"
#echo "rx0 agc manual"
cat in_voltage0_gain_control_mode
echo fast_attack > in_voltage0_gain_control_mode
#echo manual > in_voltage0_gain_control_mode
cat in_voltage0_gain_control_mode
sync
echo "rx1 agc fast_attack"
#echo "rx1 agc manual"
cat in_voltage1_gain_control_mode
echo fast_attack > in_voltage1_gain_control_mode
#echo manual > in_voltage1_gain_control_mode
cat in_voltage1_gain_control_mode
sync
sleep 1
echo "rx0 gain to 70" # this set gain is gpio gain - 5dB (test with agc and read back gpio in driver)
cat in_voltage0_hardwaregain
echo 70 > in_voltage0_hardwaregain
cat in_voltage0_hardwaregain
sync
echo "rx1 gain to 70"
cat in_voltage1_hardwaregain
echo 70 > in_voltage1_hardwaregain
cat in_voltage1_hardwaregain
sync
echo "tx0 gain -89dB"
cat out_voltage0_hardwaregain
echo -89 > out_voltage0_hardwaregain
cat out_voltage0_hardwaregain
sync
echo "tx1 gain 0dB"
cat out_voltage1_hardwaregain
echo 0 > out_voltage1_hardwaregain
cat out_voltage1_hardwaregain
sync
echo "rssi"
cat in_voltage0_rssi
cat in_voltage1_rssi
cd $home_dir

29
user_space/sdcard_boot_update.sh Executable file
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#!/bin/bash
set -x
rm BOOT.BIN
sync
wget ftp://192.168.10.1/kernel_boot/output_boot_bin/BOOT.BIN
sync
rm uImage
sync
wget ftp://192.168.10.1/adi-linux/arch/arm/boot/uImage
sync
rm devicetree.dtb
sync
wget ftp://192.168.10.1/kernel_boot/devicetree.dtb
sync
#slepp 0.5
mount /dev/mmcblk0p1 /sdcard
sync
#sleep 0.5
cp BOOT.BIN /sdcard/ -f
cp uImage /sdcard/ -f
cp devicetree.dtb /sdcard/ -f
sync
#sleep 0.5
umount /sdcard
sync
#sleep 3
sudo reboot now

30
user_space/sdr-ad-hoc-join.sh Executable file
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#!/bin/bash
if [ $# -ne 4 ]
then
echo "Please input NIC_name ch_number ip_addr cell as input parameter!"
exit
fi
nic_name=$1
ch_number=$2
ip_addr=$3
cell=$4
echo $nic_name
echo $ch_number
echo $ip_addr
echo $cell
# sudo service network-manager stop
sudo ip link set $nic_name down
sudo iwconfig $nic_name mode ad-hoc
sudo iwconfig $nic_name essid 'sdr-ad-hoc'
sudo ip link set $nic_name up
sudo iwconfig $nic_name channel $ch_number
sudo iwconfig $nic_name ap $cell
#sudo iwconfig $nic_name modulation 11g
#sudo iwconfig $nic_name rate 6M
sudo ifconfig $nic_name $ip_addr netmask 255.255.255.0
ifconfig
iwconfig $nic_name

25
user_space/sdr-ad-hoc-up.sh Executable file
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#!/bin/bash
if [ $# -ne 3 ]
then
echo "Please input NIC_name ch_number ip_addr as input parameter!"
exit
fi
nic_name=$1
ch_number=$2
ip_addr=$3
echo $nic_name
echo $ch_number
echo $ip_addr
sudo ip link set $nic_name down
sudo iwconfig $nic_name mode ad-hoc
sudo iwconfig $nic_name essid 'sdr-ad-hoc'
sudo ip link set $nic_name up
sudo iwconfig $nic_name channel $ch_number
#sudo iwconfig $nic_name modulation 11g
#sudo iwconfig $nic_name rate 6M
sudo ifconfig $nic_name $ip_addr netmask 255.255.255.0
ifconfig
iwconfig $nic_name

127
user_space/sdrctl_src/Makefile Normal file
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MAKEFLAGS += --no-print-directory
PREFIX ?= /usr
SBINDIR ?= $(PREFIX)/sbin
MANDIR ?= $(PREFIX)/share/man
PKG_CONFIG ?= pkg-config
MKDIR ?= mkdir -p
INSTALL ?= install
CC ?= "gcc"
CFLAGS ?= -O2 -g
CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Werror-implicit-function-declaration
# OBJS = iw.o genl.o event.o info.o phy.o \
interface.o ibss.o station.o survey.o util.o \
mesh.o mpath.o scan.o reg.o version.o \
reason.o status.o connect.o link.o offch.o ps.o cqm.o \
bitrate.o wowlan.o coalesce.o roc.o p2p.o
OBJS = sdrctl.o cmd.o version.o
OBJS += sections.o
# OBJS-$(HWSIM) += hwsim.o
OBJS += $(OBJS-y) $(OBJS-Y)
ALL = sdrctl
ifeq ($(NO_PKG_CONFIG),)
NL3xFOUND := $(shell $(PKG_CONFIG) --atleast-version=3.2 libnl-3.0 && echo Y)
ifneq ($(NL3xFOUND),Y)
NL31FOUND := $(shell $(PKG_CONFIG) --exact-version=3.1 libnl-3.1 && echo Y)
ifneq ($(NL31FOUND),Y)
NL3FOUND := $(shell $(PKG_CONFIG) --atleast-version=3 libnl-3.0 && echo Y)
ifneq ($(NL3FOUND),Y)
NL2FOUND := $(shell $(PKG_CONFIG) --atleast-version=2 libnl-2.0 && echo Y)
ifneq ($(NL2FOUND),Y)
NL1FOUND := $(shell $(PKG_CONFIG) --atleast-version=1 libnl-1 && echo Y)
endif
endif
endif
endif
ifeq ($(NL1FOUND),Y)
NLLIBNAME = libnl-1
endif
ifeq ($(NL2FOUND),Y)
CFLAGS += -DCONFIG_LIBNL20
LIBS += -lnl-genl
NLLIBNAME = libnl-2.0
endif
ifeq ($(NL3xFOUND),Y)
# libnl 3.2 might be found as 3.2 and 3.0
NL3FOUND = N
CFLAGS += -DCONFIG_LIBNL30
LIBS += -lnl-genl-3
NLLIBNAME = libnl-3.0
endif
ifeq ($(NL3FOUND),Y)
CFLAGS += -DCONFIG_LIBNL30
LIBS += -lnl-genl
NLLIBNAME = libnl-3.0
endif
# nl-3.1 has a broken libnl-gnl-3.1.pc file
# as show by pkg-config --debug --libs --cflags --exact-version=3.1 libnl-genl-3.1;echo $?
ifeq ($(NL31FOUND),Y)
CFLAGS += -DCONFIG_LIBNL30
LIBS += -lnl-genl
NLLIBNAME = libnl-3.1
endif
ifeq ($(NLLIBNAME),)
$(error Cannot find development files for any supported version of libnl)
endif
LIBS += $(shell $(PKG_CONFIG) --libs $(NLLIBNAME))
CFLAGS += $(shell $(PKG_CONFIG) --cflags $(NLLIBNAME))
endif # NO_PKG_CONFIG
ifeq ($(V),1)
Q=
NQ=true
else
Q=@
NQ=echo
endif
all: $(ALL)
VERSION_OBJS := $(filter-out version.o, $(OBJS))
version.c: version.sh $(patsubst %.o,%.c,$(VERSION_OBJS)) nl80211.h sdrctl.h Makefile \
$(wildcard .git/index .git/refs/tags)
@$(NQ) ' GEN ' $@
$(Q)./version.sh $@
%.o: %.c sdrctl.h nl80211.h
@$(NQ) ' CC ' $@
$(Q)$(CC) $(CFLAGS) -c -o $@ $<
sdrctl: $(OBJS)
@$(NQ) ' CC ' sdrctl
$(Q)$(CC) $(LDFLAGS) $(OBJS) $(LIBS) -o sdrctl
check:
$(Q)$(MAKE) all CC="REAL_CC=$(CC) CHECK=\"sparse -Wall\" cgcc"
%.gz: %
@$(NQ) ' GZIP' $<
$(Q)gzip < $< > $@
install: sdrctl sdrctl.8.gz
@$(NQ) ' INST sdrctl'
$(Q)$(MKDIR) $(DESTDIR)$(SBINDIR)
$(Q)$(INSTALL) -m 755 sdrctl $(DESTDIR)$(SBINDIR)
@$(NQ) ' INST sdrctl.8'
$(Q)$(MKDIR) $(DESTDIR)$(MANDIR)/man8/
$(Q)$(INSTALL) -m 644 sdrctl.8.gz $(DESTDIR)$(MANDIR)/man8/
clean:
$(Q)rm -f sdrctl *.o *~ *.gz version.c *-stamp

937
user_space/sdrctl_src/cmd.c Normal file
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// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
#include <stdbool.h>
#include <errno.h>
#include <net/if.h>
#include <strings.h>
#include <netlink/genl/genl.h>
#include <netlink/genl/family.h>
#include <netlink/genl/ctrl.h>
#include <netlink/msg.h>
#include <netlink/attr.h>
#include "nl80211.h"
#include "sdrctl.h"
#include "nl80211_testmode_def.h"
static int cb_reg_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
//printf("cb_reg_handler\n");
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
//printf("reg addr: %08x\n", nla_get_u32(tb[REG_ATTR_ADDR]));
printf("reg val: %08x\n", nla_get_u32(tb[REG_ATTR_VAL]));
return NL_SKIP;
}
static int handle_set_reg(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int reg_cat, reg_addr, reg_val;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata) {
return 1;
}
if (strcasecmp(argv[0],"rf")==0)
reg_cat=1;
else if (strcasecmp(argv[0],"rx_intf")==0)
reg_cat = 2;
else if (strcasecmp(argv[0],"tx_intf")==0)
reg_cat = 3;
else if (strcasecmp(argv[0],"rx")==0)
reg_cat = 4;
else if (strcasecmp(argv[0],"tx")==0)
reg_cat = 5;
else if (strcasecmp(argv[0],"xpu")==0)
reg_cat = 6;
else if (strcasecmp(argv[0],"drv_rx")==0)
reg_cat = 7;
else if (strcasecmp(argv[0],"drv_tx")==0)
reg_cat = 8;
else if (strcasecmp(argv[0],"drv_xpu")==0)
reg_cat = 9;
else {
printf("Wrong the 1st argument. Should be rf/rx_intf/tx_intf/rx/tx/xpu/drv_rx/drv_tx/drv_xpu\n");
return 1;
}
reg_addr = strtoul(argv[1], &end, 10);
if (*end) {
return 1;
}
reg_addr = reg_addr<<2;//from idx to addr
reg_addr = ((reg_cat<<16)|reg_addr);
reg_val = strtoul(argv[2], &end, 10);
if (*end) {
return 1;
}
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, REG_CMD_SET);
NLA_PUT_U32(msg, REG_ATTR_ADDR, reg_addr);
NLA_PUT_U32(msg, REG_ATTR_VAL, reg_val);
nla_nest_end(msg, tmdata);
printf("reg cat: %d\n", reg_cat);
printf("reg addr: %08x\n", reg_addr);
printf("reg val: %08x\n", reg_val);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, reg, "<rf/rx_intf/tx_intf/rx/tx/xpu/drv_rx/drv_tx/drv_xpu reg_idx value>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_reg, "set reg");
static int handle_get_reg(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
char *end;
struct nlattr *tmdata;
unsigned int reg_cat, reg_addr;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
if (strcasecmp(argv[0],"rf")==0)
reg_cat=1;
else if (strcasecmp(argv[0],"rx_intf")==0)
reg_cat = 2;
else if (strcasecmp(argv[0],"tx_intf")==0)
reg_cat = 3;
else if (strcasecmp(argv[0],"rx")==0)
reg_cat = 4;
else if (strcasecmp(argv[0],"tx")==0)
reg_cat = 5;
else if (strcasecmp(argv[0],"xpu")==0)
reg_cat = 6;
else if (strcasecmp(argv[0],"drv_rx")==0)
reg_cat = 7;
else if (strcasecmp(argv[0],"drv_tx")==0)
reg_cat = 8;
else if (strcasecmp(argv[0],"drv_xpu")==0)
reg_cat = 9;
else {
printf("Wrong the 1st argument. Should be rf/rx_intf/tx_intf/rx/tx/xpu/drv_rx/drv_tx/drv_xpu\n");
return 1;
}
reg_addr = strtoul(argv[1], &end, 10);
if (*end) {
return 1;
}
reg_addr = reg_addr<<2;//from idx to addr
reg_addr = ((reg_cat<<16)|reg_addr);
printf("SENDaddr: %08x\n", reg_addr);
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, REG_CMD_GET);
NLA_PUT_U32(msg, REG_ATTR_ADDR, reg_addr);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_reg_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, reg, "<rf/rx_intf/tx_intf/rx/tx/xpu/drv_rx/drv_tx/drv_xpu reg_idx>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_reg, "get reg");
static int cb_openwifi_rssi_th_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
printf("openwifi rssi_th: %d\n", nla_get_u32(tb[OPENWIFI_ATTR_RSSI_TH]));
return NL_SKIP;
}
static int handle_set_rssi_th(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int tmp;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata) {
return 1;
}
tmp = strtoul(argv[0], &end, 10);
if (*end) {
return 1;
}
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_RSSI_TH);
NLA_PUT_U32(msg, OPENWIFI_ATTR_RSSI_TH, tmp);
nla_nest_end(msg, tmdata);
printf("openwifi rssi_th: %d\n", tmp);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, rssi_th, "<rssi_th in value>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_rssi_th, "set rssi_th");
static int handle_get_rssi_th(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_RSSI_TH);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_rssi_th_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, rssi_th, "<rssi_th in value>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_rssi_th, "get rssi_th");
static int cb_openwifi_slice_total0_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
printf("openwifi slice_total0 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL0]));
return NL_SKIP;
}
static int handle_set_slice_total0(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int tmp;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata) {
return 1;
}
tmp = strtoul(argv[0], &end, 10);
if (*end) {
return 1;
}
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_TOTAL0);
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_TOTAL0, tmp);
nla_nest_end(msg, tmdata);
printf("openwifi slice_total0 (duration): %dus\n", tmp);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, slice_total0, "<slice_total0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_total0, "set slice_total0");
static int handle_get_slice_total0(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_TOTAL0);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_total0_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, slice_total0, "<slice_total0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_total0, "get slice_total0");
static int cb_openwifi_slice_total1_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
printf("openwifi slice_total1 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_TOTAL1]));
return NL_SKIP;
}
static int handle_set_slice_total1(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int tmp;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata) {
return 1;
}
tmp = strtoul(argv[0], &end, 10);
if (*end) {
return 1;
}
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_TOTAL1);
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_TOTAL1, tmp);
nla_nest_end(msg, tmdata);
printf("openwifi slice_total1 (duration): %dus\n", tmp);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, slice_total1, "<slice_total1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_total1, "set slice_total1");
static int handle_get_slice_total1(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_TOTAL1);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_total1_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, slice_total1, "<slice_total1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_total1, "get slice_total1");
static int cb_openwifi_slice_start0_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
printf("openwifi slice_start0 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START0]));
return NL_SKIP;
}
static int handle_set_slice_start0(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int tmp;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata) {
return 1;
}
tmp = strtoul(argv[0], &end, 10);
if (*end) {
return 1;
}
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_START0);
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_START0, tmp);
nla_nest_end(msg, tmdata);
printf("openwifi slice_start0 (duration): %dus\n", tmp);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, slice_start0, "<slice_start0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_start0, "set slice_start0");
static int handle_get_slice_start0(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_START0);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_start0_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, slice_start0, "<slice_start0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_start0, "get slice_start0");
static int cb_openwifi_slice_start1_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
printf("openwifi slice_start1 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_START1]));
return NL_SKIP;
}
static int handle_set_slice_start1(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int tmp;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata) {
return 1;
}
tmp = strtoul(argv[0], &end, 10);
if (*end) {
return 1;
}
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_START1);
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_START1, tmp);
nla_nest_end(msg, tmdata);
printf("openwifi slice_start1 (duration): %dus\n", tmp);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, slice_start1, "<slice_start1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_start1, "set slice_start1");
static int handle_get_slice_start1(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_START1);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_start1_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, slice_start1, "<slice_start1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_start1, "get slice_start1");
static int cb_openwifi_slice_end0_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
printf("openwifi slice_end0 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END0]));
return NL_SKIP;
}
static int handle_set_slice_end0(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int tmp;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata) {
return 1;
}
tmp = strtoul(argv[0], &end, 10);
if (*end) {
return 1;
}
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_END0);
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_END0, tmp);
nla_nest_end(msg, tmdata);
printf("openwifi slice_end0 (duration): %dus\n", tmp);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, slice_end0, "<slice_end0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_end0, "set slice_end0");
static int handle_get_slice_end0(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_END0);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_end0_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, slice_end0, "<slice_end0(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_end0, "get slice_end0");
static int cb_openwifi_slice_end1_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
printf("openwifi slice_end1 (duration): %dus\n", nla_get_u32(tb[OPENWIFI_ATTR_SLICE_END1]));
return NL_SKIP;
}
static int handle_set_slice_end1(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int tmp;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata) {
return 1;
}
tmp = strtoul(argv[0], &end, 10);
if (*end) {
return 1;
}
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_SLICE_END1);
NLA_PUT_U32(msg, OPENWIFI_ATTR_SLICE_END1, tmp);
nla_nest_end(msg, tmdata);
printf("openwifi slice_end1 (duration): %dus\n", tmp);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, slice_end1, "<slice_end1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice_end1, "set slice_end1");
static int handle_get_slice_end1(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_SLICE_END1);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice_end1_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, slice_end1, "<slice_end1(duration) in us>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice_end1, "get slice_end1");
static int cb_openwifi_slice0_target_mac_addr_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
printf("openwifi slice0_target_mac_addr(low32) in hex: %08x\n", nla_get_u32(tb[OPENWIFI_ATTR_ADDR0]));
return NL_SKIP;
}
static int handle_set_addr0(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int slice0_target_mac_addr;
//printf("handle_set_slice0_target_mac_addr\n");
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata) {
//printf("handle_set_slice0_target_mac_addr 1\n");
return 1;
}
slice0_target_mac_addr = strtoul(argv[0], &end, 16);
if (*end) {
//printf("handle_set_slice0_target_mac_addr 2 %d\n", slice0_target_mac_addr);
return 1;
}
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_ADDR0);
NLA_PUT_U32(msg, OPENWIFI_ATTR_ADDR0, slice0_target_mac_addr);
nla_nest_end(msg, tmdata);
printf("openwifi slice0_target_mac_addr(low32) in hex: %08x\n", slice0_target_mac_addr);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, addr0, "<slice0_target_mac_addr(low32) in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_addr0, "set addr0");
static int handle_get_slice0_target_mac_addr(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_ADDR0);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice0_target_mac_addr_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, addr0, "<slice0_target_mac_addr(low32) in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice0_target_mac_addr, "get addr0");
static int cb_openwifi_slice1_target_mac_addr_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
printf("openwifi slice1_target_mac_addr(low32) in hex: %08x\n", nla_get_u32(tb[OPENWIFI_ATTR_ADDR1]));
return NL_SKIP;
}
static int handle_set_slice1_target_mac_addr(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int slice1_target_mac_addr;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
slice1_target_mac_addr = strtoul(argv[0], &end, 16);
if (*end)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_ADDR1);
NLA_PUT_U32(msg, OPENWIFI_ATTR_ADDR1, slice1_target_mac_addr);
nla_nest_end(msg, tmdata);
printf("openwifi slice1_target_mac_addr(low32) in hex: %08x\n", slice1_target_mac_addr);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, addr1, "<slice1_target_mac_addr(low32) in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_slice1_target_mac_addr, "set addr1");
static int handle_get_slice1_target_mac_addr(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_ADDR1);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_slice1_target_mac_addr_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, addr1, "<slice1_target_mac_addr(low32) in hex>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_slice1_target_mac_addr, "get addr1");
static int cb_openwifi_gap_handler(struct nl_msg *msg, void *arg)
{
struct nlattr *attrs[NL80211_ATTR_MAX + 1];
struct nlattr *tb[OPENWIFI_ATTR_MAX + 1];
struct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));
nla_parse(attrs, NL80211_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL);
if (!attrs[NL80211_ATTR_TESTDATA])
return NL_SKIP;
nla_parse(tb, OPENWIFI_ATTR_MAX, nla_data(attrs[NL80211_ATTR_TESTDATA]), nla_len(attrs[NL80211_ATTR_TESTDATA]), NULL);
printf("openwifi GAP (usec): %d\n", nla_get_u32(tb[OPENWIFI_ATTR_GAP]));
return NL_SKIP;
}
static int handle_set_gap(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
char *end;
unsigned int gap_us;
//printf("handle_set_gap\n");
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
gap_us = strtoul(argv[0], &end, 10);
if (*end)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_SET_GAP);
NLA_PUT_U32(msg, OPENWIFI_ATTR_GAP, gap_us);
nla_nest_end(msg, tmdata);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(set, gap, "<gap in usec>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_set_gap, "set inter frame gap of openwifi radio");
static int handle_get_gap(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
struct nlattr *tmdata;
tmdata = nla_nest_start(msg, NL80211_ATTR_TESTDATA);
if (!tmdata)
return 1;
NLA_PUT_U32(msg, OPENWIFI_ATTR_CMD, OPENWIFI_CMD_GET_GAP);
nla_nest_end(msg, tmdata);
nl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, cb_openwifi_gap_handler, NULL);
return 0;
nla_put_failure:
return -ENOBUFS;
}
COMMAND(get, gap, "<gap in usec>", NL80211_CMD_TESTMODE, 0, CIB_NETDEV, handle_get_gap, "get inter frame gap of openwifi radio");

61
user_space/sdrctl_src/ieee80211.h Normal file
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@ -0,0 +1,61 @@
#ifndef __IEEE80211
#define __IEEE80211
/* 802.11n HT capability AMPDU settings (for ampdu_params_info) */
#define IEEE80211_HT_AMPDU_PARM_FACTOR 0x03
#define IEEE80211_HT_AMPDU_PARM_DENSITY 0x1C
#define IEEE80211_HT_CAP_SUP_WIDTH_20_40 0x0002
#define IEEE80211_HT_CAP_SGI_40 0x0040
#define IEEE80211_HT_CAP_MAX_AMSDU 0x0800
#define IEEE80211_HT_MCS_MASK_LEN 10
/**
* struct ieee80211_mcs_info - MCS information
* @rx_mask: RX mask
* @rx_highest: highest supported RX rate. If set represents
* the highest supported RX data rate in units of 1 Mbps.
* If this field is 0 this value should not be used to
* consider the highest RX data rate supported.
* @tx_params: TX parameters
*/
struct ieee80211_mcs_info {
__u8 rx_mask[IEEE80211_HT_MCS_MASK_LEN];
__u16 rx_highest;
__u8 tx_params;
__u8 reserved[3];
} __attribute__ ((packed));
/**
* struct ieee80211_ht_cap - HT capabilities
*
* This structure is the "HT capabilities element" as
* described in 802.11n D5.0 7.3.2.57
*/
struct ieee80211_ht_cap {
__u16 cap_info;
__u8 ampdu_params_info;
/* 16 bytes MCS information */
struct ieee80211_mcs_info mcs;
__u16 extended_ht_cap_info;
__u32 tx_BF_cap_info;
__u8 antenna_selection_info;
} __attribute__ ((packed));
struct ieee80211_vht_mcs_info {
__u16 rx_vht_mcs;
__u16 rx_highest;
__u16 tx_vht_mcs;
__u16 tx_highest;
} __attribute__ ((packed));
struct ieee80211_vht_cap {
__u32 cap_info;
struct ieee80211_vht_mcs_info mcs;
} __attribute__ ((packed));
#endif /* __IEEE80211 */

4284
user_space/sdrctl_src/nl80211.h Normal file
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File diff suppressed because it is too large Load Diff

76
user_space/sdrctl_src/nl80211_testmode_def.h Normal file
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@ -0,0 +1,76 @@
//---nl80211 cmd testmode definitions
//---should be used in driver sdr.c and user space app like sdrctl, iw
enum openwifi_testmode_attr {
__OPENWIFI_ATTR_INVALID = 0,
OPENWIFI_ATTR_CMD = 1,
OPENWIFI_ATTR_GAP = 2,
OPENWIFI_ATTR_ADDR0 = 3,
OPENWIFI_ATTR_ADDR1 = 4,
OPENWIFI_ATTR_SLICE_TOTAL0 = 5,
OPENWIFI_ATTR_SLICE_START0 = 6,
OPENWIFI_ATTR_SLICE_END0 = 7,
OPENWIFI_ATTR_SLICE_TOTAL1 = 8,
OPENWIFI_ATTR_SLICE_START1 = 9,
OPENWIFI_ATTR_SLICE_END1 = 10,
OPENWIFI_ATTR_RSSI_TH = 11,
REG_ATTR_ADDR = 12,
REG_ATTR_VAL = 13,
/* keep last */
__OPENWIFI_ATTR_AFTER_LAST,
OPENWIFI_ATTR_MAX = __OPENWIFI_ATTR_AFTER_LAST - 1
};
enum openwifi_testmode_cmd {
OPENWIFI_CMD_SET_GAP = 0,
OPENWIFI_CMD_GET_GAP = 1,
OPENWIFI_CMD_SET_ADDR0 = 2,
OPENWIFI_CMD_GET_ADDR0 = 3,
OPENWIFI_CMD_SET_ADDR1 = 4,
OPENWIFI_CMD_GET_ADDR1 = 5,
OPENWIFI_CMD_SET_SLICE_TOTAL0 = 6,
OPENWIFI_CMD_GET_SLICE_TOTAL0 = 7,
OPENWIFI_CMD_SET_SLICE_START0 = 8,
OPENWIFI_CMD_GET_SLICE_START0 = 9,
OPENWIFI_CMD_SET_SLICE_END0 = 10,
OPENWIFI_CMD_GET_SLICE_END0 = 11,
OPENWIFI_CMD_SET_SLICE_TOTAL1 = 12,
OPENWIFI_CMD_GET_SLICE_TOTAL1 = 13,
OPENWIFI_CMD_SET_SLICE_START1 = 14,
OPENWIFI_CMD_GET_SLICE_START1 = 15,
OPENWIFI_CMD_SET_SLICE_END1 = 16,
OPENWIFI_CMD_GET_SLICE_END1 = 17,
OPENWIFI_CMD_SET_RSSI_TH = 18,
OPENWIFI_CMD_GET_RSSI_TH = 19,
REG_CMD_SET = 20,
REG_CMD_GET = 21,
};
static const struct nla_policy openwifi_testmode_policy[OPENWIFI_ATTR_MAX + 1] = {
[OPENWIFI_ATTR_CMD] = { .type = NLA_U32 },
[OPENWIFI_ATTR_GAP] = { .type = NLA_U32 },
[OPENWIFI_ATTR_ADDR0] = { .type = NLA_U32 },
[OPENWIFI_ATTR_ADDR1] = { .type = NLA_U32 },
[OPENWIFI_ATTR_SLICE_TOTAL0] = { .type = NLA_U32 },
[OPENWIFI_ATTR_SLICE_START0] = { .type = NLA_U32 },
[OPENWIFI_ATTR_SLICE_END0] = { .type = NLA_U32 },
[OPENWIFI_ATTR_SLICE_TOTAL1] = { .type = NLA_U32 },
[OPENWIFI_ATTR_SLICE_START1] = { .type = NLA_U32 },
[OPENWIFI_ATTR_SLICE_END1] = { .type = NLA_U32 },
[OPENWIFI_ATTR_RSSI_TH] = { .type = NLA_U32 },
[REG_ATTR_ADDR] = { .type = NLA_U32 },
[REG_ATTR_VAL] = { .type = NLA_U32 },
};

568
user_space/sdrctl_src/sdrctl.c Normal file
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@ -0,0 +1,568 @@
/*
* nl80211 userspace tool
*
* Copyright 2007, 2008 Johannes Berg <johannes@sipsolutions.net>
* Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
*/
#include <errno.h>
#include <stdio.h>
#include <string.h>
#include <net/if.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#include <stdbool.h>
#include <netlink/genl/genl.h>
#include <netlink/genl/family.h>
#include <netlink/genl/ctrl.h>
#include <netlink/msg.h>
#include <netlink/attr.h>
#include "nl80211.h"
#include "sdrctl.h"
/* libnl 1.x compatibility code */
#if !defined(CONFIG_LIBNL20) && !defined(CONFIG_LIBNL30)
static inline struct nl_handle *nl_socket_alloc(void)
{
return nl_handle_alloc();
}
static inline void nl_socket_free(struct nl_sock *h)
{
nl_handle_destroy(h);
}
static inline int nl_socket_set_buffer_size(struct nl_sock *sk,
int rxbuf, int txbuf)
{
return nl_set_buffer_size(sk, rxbuf, txbuf);
}
#endif /* CONFIG_LIBNL20 && CONFIG_LIBNL30 */
int iw_debug = 0;
static int nl80211_init(struct nl80211_state *state)
{
int err;
state->nl_sock = nl_socket_alloc();
if (!state->nl_sock) {
fprintf(stderr, "Failed to allocate netlink socket.\n");
return -ENOMEM;
}
nl_socket_set_buffer_size(state->nl_sock, 8192, 8192);
if (genl_connect(state->nl_sock)) {
fprintf(stderr, "Failed to connect to generic netlink.\n");
err = -ENOLINK;
goto out_handle_destroy;
}
state->nl80211_id = genl_ctrl_resolve(state->nl_sock, "nl80211");
if (state->nl80211_id < 0) {
fprintf(stderr, "nl80211 not found.\n");
err = -ENOENT;
goto out_handle_destroy;
}
return 0;
out_handle_destroy:
nl_socket_free(state->nl_sock);
return err;
}
static void nl80211_cleanup(struct nl80211_state *state)
{
nl_socket_free(state->nl_sock);
}
static int cmd_size;
extern struct cmd __start___cmd;
extern struct cmd __stop___cmd;
#define for_each_cmd(_cmd) \
for (_cmd = &__start___cmd; _cmd < &__stop___cmd; \
_cmd = (const struct cmd *)((char *)_cmd + cmd_size))
static void __usage_cmd(const struct cmd *cmd, char *indent, bool full)
{
const char *start, *lend, *end;
printf("%s", indent);
switch (cmd->idby) {
case CIB_NONE:
break;
case CIB_PHY:
printf("phy <phyname> ");
break;
case CIB_NETDEV:
printf("dev <devname> ");
break;
case CIB_WDEV:
printf("wdev <idx> ");
break;
}
if (cmd->parent && cmd->parent->name)
printf("%s ", cmd->parent->name);
printf("%s", cmd->name);
if (cmd->args) {
/* print line by line */
start = cmd->args;
end = strchr(start, '\0');
printf(" ");
do {
lend = strchr(start, '\n');
if (!lend)
lend = end;
if (start != cmd->args) {
printf("\t");
switch (cmd->idby) {
case CIB_NONE:
break;
case CIB_PHY:
printf("phy <phyname> ");
break;
case CIB_NETDEV:
printf("dev <devname> ");
break;
case CIB_WDEV:
printf("wdev <idx> ");
break;
}
if (cmd->parent && cmd->parent->name)
printf("%s ", cmd->parent->name);
printf("%s ", cmd->name);
}
printf("%.*s\n", (int)(lend - start), start);
start = lend + 1;
} while (end != lend);
} else
printf("\n");
if (!full || !cmd->help)
return;
/* hack */
if (strlen(indent))
indent = "\t\t";
else
printf("\n");
/* print line by line */
start = cmd->help;
end = strchr(start, '\0');
do {
lend = strchr(start, '\n');
if (!lend)
lend = end;
printf("%s", indent);
printf("%.*s\n", (int)(lend - start), start);
start = lend + 1;
} while (end != lend);
printf("\n");
}
static void usage_options(void)
{
printf("Options:\n");
printf("\t--debug\t\tenable netlink debugging\n");
}
static const char *argv0;
static void usage(int argc, char **argv)
{
const struct cmd *section, *cmd;
bool full = argc >= 0;
const char *sect_filt = NULL;
const char *cmd_filt = NULL;
if (argc > 0)
sect_filt = argv[0];
if (argc > 1)
cmd_filt = argv[1];
printf("Usage:\t%s [options] command\n", argv0);
usage_options();
printf("\t--version\tshow version (%s)\n", sdrctl_version);
printf("Commands:\n");
for_each_cmd(section) {
if (section->parent)
continue;
if (sect_filt && strcmp(section->name, sect_filt))
continue;
if (section->handler && !section->hidden)
__usage_cmd(section, "\t", full);
for_each_cmd(cmd) {
if (section != cmd->parent)
continue;
if (!cmd->handler || cmd->hidden)
continue;
if (cmd_filt && strcmp(cmd->name, cmd_filt))
continue;
__usage_cmd(cmd, "\t", full);
}
}
printf("\nCommands that use the netdev ('dev') can also be given the\n"
"'wdev' instead to identify the device.\n");
printf("\nYou can omit the 'phy' or 'dev' if "
"the identification is unique,\n"
"e.g. \"./sdrctl sdr0 get rssi_th\" or \"./sdrctl sdr0 get gap\". "
"(Don't when scripting.)\n\n"
"Do NOT screenscrape this tool, we don't "
"consider its output stable.\n\n");
}
static int print_help(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id)
{
exit(3);
}
TOPLEVEL(help, "[command]", 0, 0, CIB_NONE, print_help,
"Print usage for all or a specific command, e.g.\n"
"\"help wowlan\" or \"help wowlan enable\".");
static void usage_cmd(const struct cmd *cmd)
{
printf("Usage:\t%s [options] ", argv0);
__usage_cmd(cmd, "", true);
usage_options();
}
static void version(void)
{
printf("iw version %s\n", sdrctl_version);
}
static int phy_lookup(char *name)
{
char buf[200];
int fd, pos;
snprintf(buf, sizeof(buf), "/sys/class/ieee80211/%s/index", name);
fd = open(buf, O_RDONLY);
if (fd < 0)
return -1;
pos = read(fd, buf, sizeof(buf) - 1);
if (pos < 0) {
close(fd);
return -1;
}
buf[pos] = '\0';
close(fd);
return atoi(buf);
}
static int error_handler(struct sockaddr_nl *nla, struct nlmsgerr *err,
void *arg)
{
int *ret = arg;
*ret = err->error;
return NL_STOP;
}
static int finish_handler(struct nl_msg *msg, void *arg)
{
int *ret = arg;
*ret = 0;
return NL_SKIP;
}
static int ack_handler(struct nl_msg *msg, void *arg)
{
int *ret = arg;
*ret = 0;
return NL_STOP;
}
static int __handle_cmd(struct nl80211_state *state, enum id_input idby,
int argc, char **argv, const struct cmd **cmdout)
{
const struct cmd *cmd, *match = NULL, *sectcmd;
struct nl_cb *cb;
struct nl_cb *s_cb;
struct nl_msg *msg;
signed long long devidx = 0;
int err, o_argc;
const char *command, *section;
char *tmp, **o_argv;
enum command_identify_by command_idby = CIB_NONE;
if (argc <= 1 && idby != II_NONE)
return 1;
o_argc = argc;
o_argv = argv;
switch (idby) {
case II_PHY_IDX:
command_idby = CIB_PHY;
devidx = strtoul(*argv + 4, &tmp, 0);
if (*tmp != '\0')
return 1;
argc--;
argv++;
break;
case II_PHY_NAME:
command_idby = CIB_PHY;
devidx = phy_lookup(*argv);
argc--;
argv++;
break;
case II_NETDEV:
command_idby = CIB_NETDEV;
devidx = if_nametoindex(*argv);
if (devidx == 0)
devidx = -1;
argc--;
argv++;
break;
case II_WDEV:
command_idby = CIB_WDEV;
devidx = strtoll(*argv, &tmp, 0);
if (*tmp != '\0')
return 1;
argc--;
argv++;
default:
break;
}
if (devidx < 0)
return -errno;
section = *argv;
argc--;
argv++;
for_each_cmd(sectcmd) {
if (sectcmd->parent)
continue;
/* ok ... bit of a hack for the dupe 'info' section */
if (match && sectcmd->idby != command_idby)
continue;
if (strcmp(sectcmd->name, section) == 0)
match = sectcmd;
}
sectcmd = match;
match = NULL;
if (!sectcmd)
return 1;
if (argc > 0) {
command = *argv;
for_each_cmd(cmd) {
if (!cmd->handler)
continue;
if (cmd->parent != sectcmd)
continue;
/*
* ignore mismatch id by, but allow WDEV
* in place of NETDEV
*/
if (cmd->idby != command_idby &&
!(cmd->idby == CIB_NETDEV &&
command_idby == CIB_WDEV))
continue;
if (strcmp(cmd->name, command))
continue;
if (argc > 1 && !cmd->args)
continue;
match = cmd;
break;
}
if (match) {
argc--;
argv++;
}
}
if (match)
cmd = match;
else {
/* Use the section itself, if possible. */
cmd = sectcmd;
if (argc && !cmd->args)
return 1;
if (cmd->idby != command_idby &&
!(cmd->idby == CIB_NETDEV && command_idby == CIB_WDEV))
return 1;
if (!cmd->handler)
return 1;
}
if (cmd->selector) {
cmd = cmd->selector(argc, argv);
if (!cmd)
return 1;
}
if (cmdout)
*cmdout = cmd;
if (!cmd->cmd) {
argc = o_argc;
argv = o_argv;
return cmd->handler(state, NULL, NULL, argc, argv, idby);
}
msg = nlmsg_alloc();
if (!msg) {
fprintf(stderr, "failed to allocate netlink message\n");
return 2;
}
cb = nl_cb_alloc(iw_debug ? NL_CB_DEBUG : NL_CB_DEFAULT);
s_cb = nl_cb_alloc(iw_debug ? NL_CB_DEBUG : NL_CB_DEFAULT);
if (!cb || !s_cb) {
fprintf(stderr, "failed to allocate netlink callbacks\n");
err = 2;
goto out_free_msg;
}
genlmsg_put(msg, 0, 0, state->nl80211_id, 0,
cmd->nl_msg_flags, cmd->cmd, 0);
switch (command_idby) {
case CIB_PHY:
NLA_PUT_U32(msg, NL80211_ATTR_WIPHY, devidx);
break;
case CIB_NETDEV:
NLA_PUT_U32(msg, NL80211_ATTR_IFINDEX, devidx);
break;
case CIB_WDEV:
NLA_PUT_U64(msg, NL80211_ATTR_WDEV, devidx);
break;
default:
break;
}
err = cmd->handler(state, cb, msg, argc, argv, idby);
if (err)
goto out;
nl_socket_set_cb(state->nl_sock, s_cb);
err = nl_send_auto_complete(state->nl_sock, msg);
if (err < 0)
goto out;
err = 1;
nl_cb_err(cb, NL_CB_CUSTOM, error_handler, &err);
nl_cb_set(cb, NL_CB_FINISH, NL_CB_CUSTOM, finish_handler, &err);
nl_cb_set(cb, NL_CB_ACK, NL_CB_CUSTOM, ack_handler, &err);
while (err > 0)
nl_recvmsgs(state->nl_sock, cb);
out:
nl_cb_put(cb);
out_free_msg:
nlmsg_free(msg);
return err;
nla_put_failure:
fprintf(stderr, "building message failed\n");
return 2;
}
int handle_cmd(struct nl80211_state *state, enum id_input idby,
int argc, char **argv)
{
return __handle_cmd(state, idby, argc, argv, NULL);
}
int main(int argc, char **argv)
{
struct nl80211_state nlstate;
int err;
const struct cmd *cmd = NULL;
/* calculate command size including padding */
cmd_size = abs((long)&__section_set - (long)&__section_get);
/* strip off self */
argc--;
argv0 = *argv++;
if (argc > 0 && strcmp(*argv, "--debug") == 0) {
iw_debug = 1;
argc--;
argv++;
}
if (argc > 0 && strcmp(*argv, "--version") == 0) {
version();
return 0;
}
/* need to treat "help" command specially so it works w/o nl80211 */
if (argc == 0 || strcmp(*argv, "help") == 0) {
usage(argc - 1, argv + 1);
return 0;
}
err = nl80211_init(&nlstate);
if (err)
return 1;
if (strcmp(*argv, "dev") == 0 && argc > 1) {
argc--;
argv++;
err = __handle_cmd(&nlstate, II_NETDEV, argc, argv, &cmd);
} else if (strncmp(*argv, "phy", 3) == 0 && argc > 1) {
if (strlen(*argv) == 3) {
argc--;
argv++;
err = __handle_cmd(&nlstate, II_PHY_NAME, argc, argv, &cmd);
} else if (*(*argv + 3) == '#')
err = __handle_cmd(&nlstate, II_PHY_IDX, argc, argv, &cmd);
else
goto detect;
} else if (strcmp(*argv, "wdev") == 0 && argc > 1) {
argc--;
argv++;
err = __handle_cmd(&nlstate, II_WDEV, argc, argv, &cmd);
} else {
int idx;
enum id_input idby = II_NONE;
detect:
if ((idx = if_nametoindex(argv[0])) != 0)
idby = II_NETDEV;
else if ((idx = phy_lookup(argv[0])) >= 0)
idby = II_PHY_NAME;
err = __handle_cmd(&nlstate, idby, argc, argv, &cmd);
}
if (err == 1) {
if (cmd)
usage_cmd(cmd);
else
usage(0, NULL);
} else if (err < 0)
fprintf(stderr, "command failed: %s (%d)\n", strerror(-err), err);
nl80211_cleanup(&nlstate);
return err;
}

179
user_space/sdrctl_src/sdrctl.h Normal file
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#ifndef __IW_H
#define __IW_H
#include <stdbool.h>
#include <netlink/netlink.h>
#include <netlink/genl/genl.h>
#include <netlink/genl/family.h>
#include <netlink/genl/ctrl.h>
#include <endian.h>
#include "nl80211.h"
#include "ieee80211.h"
#define ETH_ALEN 6
/* libnl 1.x compatibility code */
#if !defined(CONFIG_LIBNL20) && !defined(CONFIG_LIBNL30)
# define nl_sock nl_handle
#endif
struct nl80211_state {
struct nl_sock *nl_sock;
int nl80211_id;
};
enum command_identify_by {
CIB_NONE,
CIB_PHY,
CIB_NETDEV,
CIB_WDEV,
};
enum id_input {
II_NONE,
II_NETDEV,
II_PHY_NAME,
II_PHY_IDX,
II_WDEV,
};
struct cmd {
const char *name;
const char *args;
const char *help;
const enum nl80211_commands cmd;
int nl_msg_flags;
int hidden;
const enum command_identify_by idby;
/*
* The handler should return a negative error code,
* zero on success, 1 if the arguments were wrong
* and the usage message should and 2 otherwise.
*/
int (*handler)(struct nl80211_state *state,
struct nl_cb *cb,
struct nl_msg *msg,
int argc, char **argv,
enum id_input id);
const struct cmd *(*selector)(int argc, char **argv);
const struct cmd *parent;
};
#define ARRAY_SIZE(ar) (sizeof(ar)/sizeof(ar[0]))
#define DIV_ROUND_UP(x, y) (((x) + (y - 1)) / (y))
#define __COMMAND(_section, _symname, _name, _args, _nlcmd, _flags, _hidden, _idby, _handler, _help, _sel)\
static struct cmd \
__cmd ## _ ## _symname ## _ ## _handler ## _ ## _nlcmd ## _ ## _idby ## _ ## _hidden\
__attribute__((used)) __attribute__((section("__cmd"))) = { \
.name = (_name), \
.args = (_args), \
.cmd = (_nlcmd), \
.nl_msg_flags = (_flags), \
.hidden = (_hidden), \
.idby = (_idby), \
.handler = (_handler), \
.help = (_help), \
.parent = _section, \
.selector = (_sel), \
}
#define __ACMD(_section, _symname, _name, _args, _nlcmd, _flags, _hidden, _idby, _handler, _help, _sel, _alias)\
__COMMAND(_section, _symname, _name, _args, _nlcmd, _flags, _hidden, _idby, _handler, _help, _sel);\
static const struct cmd *_alias = &__cmd ## _ ## _symname ## _ ## _handler ## _ ## _nlcmd ## _ ## _idby ## _ ## _hidden
#define COMMAND(section, name, args, cmd, flags, idby, handler, help) \
__COMMAND(&(__section ## _ ## section), name, #name, args, cmd, flags, 0, idby, handler, help, NULL)
#define COMMAND_ALIAS(section, name, args, cmd, flags, idby, handler, help, selector, alias)\
__ACMD(&(__section ## _ ## section), name, #name, args, cmd, flags, 0, idby, handler, help, selector, alias)
#define HIDDEN(section, name, args, cmd, flags, idby, handler) \
__COMMAND(&(__section ## _ ## section), name, #name, args, cmd, flags, 1, idby, handler, NULL, NULL)
#define TOPLEVEL(_name, _args, _nlcmd, _flags, _idby, _handler, _help) \
struct cmd \
__section ## _ ## _name \
__attribute__((used)) __attribute__((section("__cmd"))) = { \
.name = (#_name), \
.args = (_args), \
.cmd = (_nlcmd), \
.nl_msg_flags = (_flags), \
.idby = (_idby), \
.handler = (_handler), \
.help = (_help), \
}
#define SECTION(_name) \
struct cmd __section ## _ ## _name \
__attribute__((used)) __attribute__((section("__cmd"))) = { \
.name = (#_name), \
.hidden = 1, \
}
#define DECLARE_SECTION(_name) \
extern struct cmd __section ## _ ## _name;
extern const char sdrctl_version[];
extern int iw_debug;
int handle_cmd(struct nl80211_state *state, enum id_input idby,
int argc, char **argv);
struct print_event_args {
struct timeval ts; /* internal */
bool have_ts; /* must be set false */
bool frame, time, reltime;
};
__u32 listen_events(struct nl80211_state *state,
const int n_waits, const __u32 *waits);
int __prepare_listen_events(struct nl80211_state *state);
__u32 __do_listen_events(struct nl80211_state *state,
const int n_waits, const __u32 *waits,
struct print_event_args *args);
int mac_addr_a2n(unsigned char *mac_addr, char *arg);
void mac_addr_n2a(char *mac_addr, unsigned char *arg);
int parse_hex_mask(char *hexmask, unsigned char **result, size_t *result_len,
unsigned char **mask);
unsigned char *parse_hex(char *hex, size_t *outlen);
int parse_keys(struct nl_msg *msg, char **argv, int argc);
void print_ht_mcs(const __u8 *mcs);
void print_ampdu_length(__u8 exponent);
void print_ampdu_spacing(__u8 spacing);
void print_ht_capability(__u16 cap);
void print_vht_info(__u32 capa, const __u8 *mcs);
char *channel_width_name(enum nl80211_chan_width width);
const char *iftype_name(enum nl80211_iftype iftype);
const char *command_name(enum nl80211_commands cmd);
int ieee80211_channel_to_frequency(int chan, enum nl80211_band band);
int ieee80211_frequency_to_channel(int freq);
void print_ssid_escaped(const uint8_t len, const uint8_t *data);
int nl_get_multicast_id(struct nl_sock *sock, const char *family, const char *group);
char *reg_initiator_to_string(__u8 initiator);
const char *get_reason_str(uint16_t reason);
const char *get_status_str(uint16_t status);
enum print_ie_type {
PRINT_SCAN,
PRINT_LINK,
};
#define BIT(x) (1ULL<<(x))
void print_ies(unsigned char *ie, int ielen, bool unknown,
enum print_ie_type ptype);
void parse_bitrate(struct nlattr *bitrate_attr, char *buf, int buflen);
void iw_hexdump(const char *prefix, const __u8 *data, size_t len);
DECLARE_SECTION(set);
DECLARE_SECTION(get);
#endif /* __IW_H */

4
user_space/sdrctl_src/sections.c Normal file
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@ -0,0 +1,4 @@
#include "sdrctl.h"
SECTION(get);
SECTION(set);

23
user_space/sdrctl_src/version.sh Executable file
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@ -0,0 +1,23 @@
#!/bin/sh
VERSION="3.17"
OUT="$1"
if [ -d .git ] && head=`git rev-parse --verify HEAD 2>/dev/null`; then
git update-index --refresh --unmerged > /dev/null
descr=$(git describe)
# on git builds check that the version number above
# is correct...
[ "${descr%%-*}" = "v$VERSION" ] || exit 2
v="${descr#v}"
if git diff-index --name-only HEAD | read dummy ; then
v="$v"-dirty
fi
else
v="$VERSION"
fi
echo '#include "sdrctl.h"' > "$OUT"
echo "const char sdrctl_version[] = \"$v\";" >> "$OUT"

37
user_space/set_ant.sh Executable file
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@ -0,0 +1,37 @@
#!/bin/sh
if [ "$#" -ne 2 ]; then
echo "Need 2 arguments. The 1st select rx antenna. The 2nd for tx antenna."
echo "Eg, "
echo "./set_ant rx2 tx2"
echo "./set_ant rx1 tx1"
echo "./set_ant rx2 tx1"
echo "./set_ant rx1 tx2"
exit 1
fi
set -x
if [ $1 = "rx2" ]
then
./sdrctl dev sdr0 set reg drv_rx 1 1
elif [ $1 = "rx1" ]
then
./sdrctl dev sdr0 set reg drv_rx 1 0
else
echo "The 1st argument must be rx2 or rx1!"
exit 1
fi
if [ $2 = "tx2" ]
then
./sdrctl dev sdr0 set reg drv_tx 1 1
elif [ $2 = "tx1" ]
then
./sdrctl dev sdr0 set reg drv_tx 1 0
else
echo "The 2nd argument must be tx2 or tx1!"
exit 1
fi
ifconfig sdr0 down
ifconfig sdr0 up

6
user_space/set_csma_high.sh Normal file
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@ -0,0 +1,6 @@
#!/bin/bash
./sdrctl dev sdr0 get reg xpu 19
./sdrctl dev sdr0 set reg xpu 19 3758096384

6
user_space/set_csma_normal.sh Normal file
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@ -0,0 +1,6 @@
#!/bin/bash
./sdrctl dev sdr0 get reg xpu 19
./sdrctl dev sdr0 set reg xpu 19 0

26
user_space/slice_cfg.sh Normal file
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#!/bin/bash
if [ $# -ne 5 ]
then
echo "Please input slice_idx mac_addr cycle_period(us) start_time(us) end_time(us) as input parameter!"
exit
fi
set -x #echo on
slice_idx=$1
mac_addr=$2
cycle_period=$3
start_time=$4
end_time=$5
echo $slice_idx
echo $mac_addr
echo $cycle_period
echo $start_time
echo $end_time
./sdrctl dev sdr0 set addr$slice_idx $mac_addr
./sdrctl dev sdr0 set slice_total$slice_idx $cycle_period
./sdrctl dev sdr0 set slice_start$slice_idx $start_time
./sdrctl dev sdr0 set slice_end$slice_idx $end_time

219
user_space/wgd.sh Executable file
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#!/bin/bash
checkModule () {
MODULE="$1"
if lsmod | grep "$MODULE" &> /dev/null ; then
echo "$MODULE is loaded!"
return 0
else
echo "$MODULE is not loaded!"
return 1
fi
}
num_arg=$#
echo "num_arg " $num_arg
for input_var in "$@"
do
last_input=$input_var
# echo $last_input
done
if [ -z $last_input ]
then
last_input="xxxxxxxxx"
test_mode=0
else
if [ $1 -eq 1 ]
then
test_mode=1
else
test_mode=0
fi
fi
echo last_input $last_input
echo test_mode $test_mode
modprobe mac80211
# dmesg -c
PROG=sdr
rmmod $PROG
SUBMODULE=xilinx_dma
if [ $last_input == "remote" ]
then
rm $SUBMODULE.ko
sync
wget ftp://192.168.10.1/driver/$SUBMODULE/$SUBMODULE.ko
sync
fi
rmmod $SUBMODULE
insmod $SUBMODULE.ko
#sleep 1
echo check $SUBMODULE module is loaded or not
checkModule $SUBMODULE
if [ $? -eq 1 ]
then
return
fi
# before drive ad9361, let's bring up duc and make sure dac is connected to ad9361 dma
SUBMODULE=tx_intf
if [ $last_input == "remote" ]
then
rm $SUBMODULE.ko
sync
wget ftp://192.168.10.1/driver/$SUBMODULE/$SUBMODULE.ko
sync
fi
rmmod $SUBMODULE
insmod $SUBMODULE.ko
echo check $SUBMODULE module is loaded or not
checkModule $SUBMODULE
if [ $? -eq 1 ]
then
return
fi
sleep 0.5
SUBMODULE=ad9361_drv
if [ $last_input == "remote" ]
then
rm $SUBMODULE.ko
sync
wget ftp://192.168.10.1/driver/ad9361/$SUBMODULE.ko
sync
fi
rmmod $SUBMODULE
insmod $SUBMODULE.ko
echo check $SUBMODULE module is loaded or not
checkModule $SUBMODULE
if [ $? -eq 1 ]
then
return
fi
sleep 1
echo "set RF frontend: ant0 rx, ant1 tx"
if [ $last_input == "remote" ]
then
rm rf_init.sh
sync
wget ftp://192.168.10.1/user_space/rf_init.sh
sync
chmod +x rf_init.sh
sync
fi
./rf_init.sh
#sleep 1
SUBMODULE=rx_intf
if [ $last_input == "remote" ]
then
rm $SUBMODULE.ko
sync
wget ftp://192.168.10.1/driver/$SUBMODULE/$SUBMODULE.ko
sync
fi
rmmod $SUBMODULE
insmod $SUBMODULE.ko
echo check $SUBMODULE module is loaded or not
checkModule $SUBMODULE
if [ $? -eq 1 ]
then
return
fi
SUBMODULE=openofdm_tx
if [ $last_input == "remote" ]
then
rm $SUBMODULE.ko
sync
wget ftp://192.168.10.1/driver/$SUBMODULE/$SUBMODULE.ko
sync
fi
rmmod $SUBMODULE
insmod $SUBMODULE.ko
echo check $SUBMODULE module is loaded or not
checkModule $SUBMODULE
if [ $? -eq 1 ]
then
return
fi
SUBMODULE=openofdm_rx
if [ $last_input == "remote" ]
then
rm $SUBMODULE.ko
sync
wget ftp://192.168.10.1/driver/$SUBMODULE/$SUBMODULE.ko
sync
fi
rmmod $SUBMODULE
insmod $SUBMODULE.ko
echo check $SUBMODULE module is loaded or not
checkModule $SUBMODULE
if [ $? -eq 1 ]
then
return
fi
SUBMODULE=xpu
if [ $last_input == "remote" ]
then
rm $SUBMODULE.ko
sync
wget ftp://192.168.10.1/driver/$SUBMODULE/$SUBMODULE.ko
sync
fi
rmmod $SUBMODULE
insmod $SUBMODULE.ko
echo check $SUBMODULE module is loaded or not
checkModule $SUBMODULE
if [ $? -eq 1 ]
then
return
fi
sleep 0.5
PROG=sdr
if [ $last_input == "remote" ]
then
rm $PROG.ko
sync
wget ftp://192.168.10.1/driver/$PROG.ko
sync
fi
rmmod $PROG
echo insert $PROG.ko test_mode=$test_mode
insmod $PROG.ko test_mode=$test_mode
echo check $PROG module is loaded or not
checkModule $PROG
if [ $? -eq 1 ]
then
return
fi
echo the end
dmesg
# dmesg -c
# sleep 0.1
# ifconfig sdr0 up

4
user_space/wpa-connect.conf Normal file
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network={
ssid="ssid"
psk="password"
}