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361 lines
10 KiB
C
361 lines
10 KiB
C
/*
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* ADI-AIM ADI ADC Interface Module
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*
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* Copyright 2012-2017 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*
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* http://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467
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*
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* Modified by Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
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*
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*/
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#ifndef ADI_AXI_ADC_H_
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#define ADI_AXI_ADC_H_
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#define ADI_REG_VERSION 0x0000 /*Version and Scratch Registers */
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#define ADI_VERSION(x) (((x) & 0xffffffff) << 0) /* RO, Version number. */
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#define VERSION_IS(x,y,z) ((x) << 16 | (y) << 8 | (z))
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#define ADI_REG_ID 0x0004 /*Version and Scratch Registers */
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#define ADI_ID(x) (((x) & 0xffffffff) << 0) /* RO, Instance identifier number. */
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#define ADI_REG_SCRATCH 0x0008 /*Version and Scratch Registers */
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#define ADI_SCRATCH(x) (((x) & 0xffffffff) << 0) /* RW, Scratch register. */
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#define PCORE_VERSION(major, minor, letter) ((major << 16) | (minor << 8) | letter)
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#define PCORE_VERSION_MAJOR(version) (version >> 16)
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#define PCORE_VERSION_MINOR(version) ((version >> 8) & 0xff)
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#define PCORE_VERSION_LETTER(version) (version & 0xff)
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/* ADC COMMON */
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#define ADI_REG_CONFIG 0x000C
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#define ADI_IQCORRECTION_DISABLE (1 << 0)
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#define ADI_DCFILTER_DISABLE (1 << 1)
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#define ADI_DATAFORMAT_DISABLE (1 << 2)
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#define ADI_USERPORTS_DISABLE (1 << 3)
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#define ADI_MODE_1R1T (1 << 4)
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#define ADI_SCALECORRECTION_ONLY (1 << 5)
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#define ADI_CMOS_OR_LVDS_N (1 << 7)
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#define ADI_PPS_RECEIVER_ENABLE (1 << 8)
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#define ADI_REG_RSTN 0x0040
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#define ADI_RSTN (1 << 0)
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#define ADI_MMCM_RSTN (1 << 1)
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#define ADI_REG_CNTRL 0x0044
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#define ADI_R1_MODE (1 << 2)
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#define ADI_DDR_EDGESEL (1 << 1)
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#define ADI_PIN_MODE (1 << 0)
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#define ADI_REG_CLK_FREQ 0x0054
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#define ADI_CLK_FREQ(x) (((x) & 0xFFFFFFFF) << 0)
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#define ADI_TO_CLK_FREQ(x) (((x) >> 0) & 0xFFFFFFFF)
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#define ADI_REG_CLK_RATIO 0x0058
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#define ADI_CLK_RATIO(x) (((x) & 0xFFFFFFFF) << 0)
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#define ADI_TO_CLK_RATIO(x) (((x) >> 0) & 0xFFFFFFFF)
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#define ADI_REG_STATUS 0x005C
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#define ADI_MUX_PN_ERR (1 << 3)
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#define ADI_MUX_PN_OOS (1 << 2)
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#define ADI_MUX_OVER_RANGE (1 << 1)
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#define ADI_STATUS (1 << 0)
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#define ADI_REG_DELAY_CNTRL 0x0060 /* <= v8.0 */
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#define ADI_DELAY_SEL (1 << 17)
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#define ADI_DELAY_RWN (1 << 16)
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#define ADI_DELAY_ADDRESS(x) (((x) & 0xFF) << 8)
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#define ADI_TO_DELAY_ADDRESS(x) (((x) >> 8) & 0xFF)
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#define ADI_DELAY_WDATA(x) (((x) & 0x1F) << 0)
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#define ADI_TO_DELAY_WDATA(x) (((x) >> 0) & 0x1F)
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#define ADI_REG_DELAY_STATUS 0x0064 /* <= v8.0 */
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#define ADI_DELAY_LOCKED (1 << 9)
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#define ADI_DELAY_STATUS (1 << 8)
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#define ADI_DELAY_RDATA(x) (((x) & 0x1F) << 0)
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#define ADI_TO_DELAY_RDATA(x) (((x) >> 0) & 0x1F)
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#define ADI_REG_DRP_CNTRL 0x0070
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#define ADI_DRP_SEL (1 << 29)
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#define ADI_DRP_RWN (1 << 28)
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#define ADI_DRP_ADDRESS(x) (((x) & 0xFFF) << 16)
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#define ADI_TO_DRP_ADDRESS(x) (((x) >> 16) & 0xFFF)
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#define ADI_DRP_WDATA(x) (((x) & 0xFFFF) << 0)
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#define ADI_TO_DRP_WDATA(x) (((x) >> 0) & 0xFFFF)
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#define ADI_REG_DRP_STATUS 0x0074
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#define ADI_DRP_STATUS (1 << 16)
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#define ADI_DRP_RDATA(x) (((x) & 0xFFFF) << 0)
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#define ADI_TO_DRP_RDATA(x) (((x) >> 0) & 0xFFFF)
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#define ADI_REG_DMA_STATUS 0x0088
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#define ADI_DMA_OVF (1 << 2)
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#define ADI_DMA_UNF (1 << 1)
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#define ADI_DMA_STATUS (1 << 0)
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#define ADI_REG_DMA_BUSWIDTH 0x008C
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#define ADI_DMA_BUSWIDTH(x) (((x) & 0xFFFFFFFF) << 0)
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#define ADI_TO_DMA_BUSWIDTH(x) (((x) >> 0) & 0xFFFFFFFF)
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#define ADI_REG_USR_CNTRL_1 0x00A0
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#define ADI_USR_CHANMAX(x) (((x) & 0xFF) << 0)
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#define ADI_TO_USR_CHANMAX(x) (((x) >> 0) & 0xFF)
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#define ADI_REG_GP_CONTROL 0x00BC
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#define ADI_REG_CLOCKS_PER_PPS 0x00C0
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#define ADI_REG_CLOCKS_PER_PPS_STATUS 0x00C4
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#define ADI_CLOCKS_PER_PPS_STAT_INVAL (1 << 0)
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/* ADC CHANNEL */
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#define ADI_REG_CHAN_CNTRL(c) (0x0400 + (c) * 0x40)
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#define ADI_PN_SEL (1 << 10) /* !v8.0 */
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#define ADI_IQCOR_ENB (1 << 9)
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#define ADI_DCFILT_ENB (1 << 8)
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#define ADI_FORMAT_SIGNEXT (1 << 6)
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#define ADI_FORMAT_TYPE (1 << 5)
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#define ADI_FORMAT_ENABLE (1 << 4)
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#define ADI_PN23_TYPE (1 << 1) /* !v8.0 */
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#define ADI_ENABLE (1 << 0)
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#define ADI_REG_CHAN_STATUS(c) (0x0404 + (c) * 0x40)
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#define ADI_PN_ERR (1 << 2)
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#define ADI_PN_OOS (1 << 1)
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#define ADI_OVER_RANGE (1 << 0)
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#define ADI_REG_CHAN_CNTRL_1(c) (0x0410 + (c) * 0x40)
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#define ADI_DCFILT_OFFSET(x) (((x) & 0xFFFF) << 16)
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#define ADI_TO_DCFILT_OFFSET(x) (((x) >> 16) & 0xFFFF)
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#define ADI_DCFILT_COEFF(x) (((x) & 0xFFFF) << 0)
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#define ADI_TO_DCFILT_COEFF(x) (((x) >> 0) & 0xFFFF)
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#define ADI_REG_CHAN_CNTRL_2(c) (0x0414 + (c) * 0x40)
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#define ADI_IQCOR_COEFF_1(x) (((x) & 0xFFFF) << 16)
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#define ADI_TO_IQCOR_COEFF_1(x) (((x) >> 16) & 0xFFFF)
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#define ADI_IQCOR_COEFF_2(x) (((x) & 0xFFFF) << 0)
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#define ADI_TO_IQCOR_COEFF_2(x) (((x) >> 0) & 0xFFFF)
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#define ADI_REG_CHAN_CNTRL_3(c) (0x0418 + (c) * 0x40) /* v8.0 */
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#define ADI_ADC_PN_SEL(x) (((x) & 0xF) << 16)
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#define ADI_TO_ADC_PN_SEL(x) (((x) >> 16) & 0xF)
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#define ADI_ADC_DATA_SEL(x) (((x) & 0xF) << 0)
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#define ADI_TO_ADC_DATA_SEL(x) (((x) >> 0) & 0xF)
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enum adc_pn_sel {
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ADC_PN9 = 0,
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ADC_PN23A = 1,
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ADC_PN7 = 4,
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ADC_PN15 = 5,
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ADC_PN23 = 6,
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ADC_PN31 = 7,
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ADC_PN_CUSTOM = 9,
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ADC_PN_OFF = 10,
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};
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enum adc_data_sel {
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ADC_DATA_SEL_NORM,
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ADC_DATA_SEL_LB, /* DAC loopback */
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ADC_DATA_SEL_RAMP, /* TBD */
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};
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#define ADI_REG_CHAN_USR_CNTRL_1(c) (0x0420 + (c) * 0x40)
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#define ADI_USR_DATATYPE_BE (1 << 25)
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#define ADI_USR_DATATYPE_SIGNED (1 << 24)
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#define ADI_USR_DATATYPE_SHIFT(x) (((x) & 0xFF) << 16)
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#define ADI_TO_USR_DATATYPE_SHIFT(x) (((x) >> 16) & 0xFF)
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#define ADI_USR_DATATYPE_TOTAL_BITS(x) (((x) & 0xFF) << 8)
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#define ADI_TO_USR_DATATYPE_TOTAL_BITS(x) (((x) >> 8) & 0xFF)
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#define ADI_USR_DATATYPE_BITS(x) (((x) & 0xFF) << 0)
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#define ADI_TO_USR_DATATYPE_BITS(x) (((x) >> 0) & 0xFF)
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#define ADI_REG_CHAN_USR_CNTRL_2(c) (0x0424 + (c) * 0x40)
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#define ADI_USR_DECIMATION_M(x) (((x) & 0xFFFF) << 16)
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#define ADI_TO_USR_DECIMATION_M(x) (((x) >> 16) & 0xFFFF)
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#define ADI_USR_DECIMATION_N(x) (((x) & 0xFFFF) << 0)
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#define ADI_TO_USR_DECIMATION_N(x) (((x) >> 0) & 0xFFFF)
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#define ADI_REG_ADC_DP_DISABLE 0x00C0
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/* PCORE Version > 8.00 */
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#define ADI_REG_DELAY(l) (0x0800 + (l) * 0x4)
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/* debugfs direct register access */
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#define DEBUGFS_DRA_PCORE_REG_MAGIC 0x80000000
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#define AXIADC_MAX_CHANNEL 16
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#include <linux/spi/spi.h>
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#include <linux/clk/clkscale.h>
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struct axiadc_chip_info {
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char *name;
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unsigned num_channels;
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unsigned num_shadow_slave_channels;
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const unsigned long *scan_masks;
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const int (*scale_table)[2];
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int num_scales;
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int max_testmode;
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unsigned long max_rate;
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struct iio_chan_spec channel[AXIADC_MAX_CHANNEL];
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};
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struct axiadc_state {
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struct device *dev_spi;
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struct iio_info iio_info;
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struct clk *clk;
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size_t regs_size;
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void __iomem *regs;
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void __iomem *slave_regs;
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unsigned max_usr_channel;
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unsigned adc_def_output_mode;
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unsigned max_count;
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unsigned id;
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unsigned pcore_version;
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unsigned decimation_factor;
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bool dp_disable;
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unsigned long long adc_clk;
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unsigned have_slave_channels;
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struct iio_hw_consumer *frontend;
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struct iio_chan_spec channels[AXIADC_MAX_CHANNEL];
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};
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struct axiadc_converter {
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struct spi_device *spi;
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struct clk *clk;
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struct clock_scale adc_clkscale;
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struct clk *lane_clk;
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struct clk *sysref_clk;
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void *phy;
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struct gpio_desc *pwrdown_gpio;
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struct gpio_desc *reset_gpio;
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unsigned id;
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unsigned adc_output_mode;
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unsigned testmode[AXIADC_MAX_CHANNEL];
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unsigned scratch_reg[AXIADC_MAX_CHANNEL];
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unsigned long adc_clk;
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const struct axiadc_chip_info *chip_info;
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bool sample_rate_read_only;
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int (*reg_access)(struct iio_dev *indio_dev, unsigned int reg,
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unsigned int writeval, unsigned int *readval);
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int (*setup)(struct spi_device *spi, unsigned mode);
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struct iio_chan_spec const *channels;
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int num_channels;
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const struct attribute_group *attrs;
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struct iio_dev *indio_dev;
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int (*read_raw)(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long mask);
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int (*write_raw)(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val,
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int val2,
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long mask);
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int (*read_event_value)(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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enum iio_event_type type,
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enum iio_event_direction dir,
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enum iio_event_info info,
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int *val,
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int *val2);
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int (*write_event_value)(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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enum iio_event_type type,
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enum iio_event_direction dir,
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enum iio_event_info info,
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int val,
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int val2);
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int (*read_event_config)(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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enum iio_event_type type,
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enum iio_event_direction dir);
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int (*write_event_config)(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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enum iio_event_type type,
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enum iio_event_direction dir,
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int state);
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int (*post_setup)(struct iio_dev *indio_dev);
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int (*set_pnsel)(struct iio_dev *indio_dev, unsigned chan,
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enum adc_pn_sel sel);
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};
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static inline struct axiadc_converter *to_converter(struct device *dev)
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{
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struct axiadc_converter *conv = spi_get_drvdata(to_spi_device(dev));
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if (conv)
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return conv;
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return ERR_PTR(-ENODEV);
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};
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struct axiadc_spidev {
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struct device_node *of_nspi;
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struct device *dev_spi;
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};
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/*
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* IO accessors
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*/
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static inline void axiadc_write(struct axiadc_state *st, unsigned reg, unsigned val)
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{
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iowrite32(val, st->regs + reg);
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}
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static inline unsigned int axiadc_read(struct axiadc_state *st, unsigned reg)
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{
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return ioread32(st->regs + reg);
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}
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static inline void axiadc_slave_write(struct axiadc_state *st, unsigned reg, unsigned val)
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{
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iowrite32(val, st->slave_regs + reg);
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}
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static inline unsigned int axiadc_slave_read(struct axiadc_state *st, unsigned reg)
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{
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return ioread32(st->slave_regs + reg);
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}
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static inline void axiadc_idelay_set(struct axiadc_state *st,
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unsigned lane, unsigned val)
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{
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if (PCORE_VERSION_MAJOR(st->pcore_version) > 8) {
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axiadc_write(st, ADI_REG_DELAY(lane), val);
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} else {
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axiadc_write(st, ADI_REG_DELAY_CNTRL, 0);
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axiadc_write(st, ADI_REG_DELAY_CNTRL,
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ADI_DELAY_ADDRESS(lane)
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| ADI_DELAY_WDATA(val)
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| ADI_DELAY_SEL);
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}
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}
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int axiadc_set_pnsel(struct axiadc_state *st, int channel, enum adc_pn_sel sel);
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enum adc_pn_sel axiadc_get_pnsel(struct axiadc_state *st,
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int channel, const char **name);
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int axiadc_configure_ring_stream(struct iio_dev *indio_dev,
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const char *dma_name);
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void axiadc_unconfigure_ring_stream(struct iio_dev *indio_dev);
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#endif /* ADI_AXI_ADC_H_ */
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