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1. If strong DC or low frequency sing wave like signal (suspect it is generated by ad9361 during some self-calibration like operation), put the receiver into reset 2. If the signal/header is valid, but the packet length is abnormal (signal_len<14 || signal_len>max_signal_len_th), reset the receiver
69 lines
2.1 KiB
Verilog
69 lines
2.1 KiB
Verilog
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
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module signal_watchdog
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#(
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parameter integer IQ_DATA_WIDTH = 16,
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parameter LOG2_SUM_LEN = 6
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)
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(
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input clk,
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input rstn,
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input enable,
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input signed [(IQ_DATA_WIDTH-1):0] i_data,
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input signed [(IQ_DATA_WIDTH-1):0] q_data,
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input iq_valid,
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input [15:0] signal_len,
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input sig_valid,
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input [15:0] max_signal_len_th,
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input signed [(LOG2_SUM_LEN+2-1):0] dc_running_sum_th,
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output receiver_rst
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);
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wire signed [1:0] i_sign;
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wire signed [1:0] q_sign;
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wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i;
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wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q;
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wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i_abs;
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wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q_abs;
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wire receiver_rst_internal;
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reg receiver_rst_reg;
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wire receiver_rst_pulse;
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assign i_sign = (i_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
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assign q_sign = (q_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
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assign running_sum_result_i_abs = (running_sum_result_i[LOG2_SUM_LEN+2-1]?(-running_sum_result_i):running_sum_result_i);
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assign running_sum_result_q_abs = (running_sum_result_q[LOG2_SUM_LEN+2-1]?(-running_sum_result_q):running_sum_result_q);
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assign receiver_rst_internal = (enable&(running_sum_result_i_abs>=dc_running_sum_th || running_sum_result_q_abs>=dc_running_sum_th));
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assign receiver_rst_pulse = (receiver_rst_internal&&(~receiver_rst_reg));
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assign receiver_rst = ( receiver_rst_reg | (sig_valid && (signal_len<14 || signal_len>max_signal_len_th)) );
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always @(posedge clk) begin
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if (~rstn) begin
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receiver_rst_reg <= 0;
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end else begin
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receiver_rst_reg <= receiver_rst_internal;
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end
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end
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running_sum_dual_ch #(.DATA_WIDTH0(2), .DATA_WIDTH1(2), .LOG2_SUM_LEN(LOG2_SUM_LEN)) signal_watchdog_running_sum_inst (
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.clk(clk),
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.rstn(rstn),
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.data_in0(i_sign),
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.data_in1(q_sign),
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.data_in_valid(iq_valid),
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.running_sum_result0(running_sum_result_i),
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.running_sum_result1(running_sum_result_q),
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.data_out_valid()
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);
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endmodule
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