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1. If strong DC or low frequency sing wave like signal (suspect it is generated by ad9361 during some self-calibration like operation), put the receiver into reset 2. If the signal/header is valid, but the packet length is abnormal (signal_len<14 || signal_len>max_signal_len_th), reset the receiver
94 lines
2.6 KiB
Verilog
94 lines
2.6 KiB
Verilog
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
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module running_sum
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#(
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parameter DATA_WIDTH = 16,
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parameter LOG2_SUM_LEN = 6
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)
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(
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input clk,
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input rstn,
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input signed [DATA_WIDTH-1:0] data_in,
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input data_in_valid,
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output reg signed [(DATA_WIDTH + LOG2_SUM_LEN-1):0] running_sum_result,
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output reg data_out_valid
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);
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localparam FIFO_SIZE = 1<<LOG2_SUM_LEN;
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localparam TOTAL_WIDTH = DATA_WIDTH + LOG2_SUM_LEN;
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wire signed [DATA_WIDTH-1:0] data_in_old;
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wire signed [TOTAL_WIDTH-1:0] ext_data_in_old = {{LOG2_SUM_LEN{data_in_old[DATA_WIDTH-1]}}, data_in_old};
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wire signed [TOTAL_WIDTH-1:0] ext_data_in = {{LOG2_SUM_LEN{data_in[DATA_WIDTH-1]}}, data_in };
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reg data_in_valid_reg;
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reg rd_en, rd_en_start;
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wire [LOG2_SUM_LEN:0] wr_data_count;
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xpm_fifo_sync #(
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.DOUT_RESET_VALUE("0"), // String
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.ECC_MODE("no_ecc"), // String
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.FIFO_MEMORY_TYPE("auto"), // String
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.FIFO_READ_LATENCY(0), // DECIMAL
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.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL
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.FULL_RESET_VALUE(0), // DECIMAL
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.PROG_EMPTY_THRESH(10), // DECIMAL
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.PROG_FULL_THRESH(10), // DECIMAL
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.RD_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1), // DECIMAL
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.READ_DATA_WIDTH(DATA_WIDTH), // DECIMAL
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.READ_MODE("fwft"), // String
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.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
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.WAKEUP_TIME(0), // DECIMAL
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.WRITE_DATA_WIDTH(DATA_WIDTH), // DECIMAL
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.WR_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1) // DECIMAL
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) fifo_1clk_for_mv_avg_i (
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.almost_empty(),
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.almost_full(),
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.data_valid(),
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.dbiterr(),
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.dout(data_in_old),
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.empty(empty),
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.full(full),
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.overflow(),
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.prog_empty(),
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.prog_full(),
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.rd_data_count(),
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.rd_rst_busy(),
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.sbiterr(),
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.underflow(),
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.wr_ack(),
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.wr_data_count(wr_data_count),
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.wr_rst_busy(),
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.din(data_in),
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.injectdbiterr(),
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.injectsbiterr(),
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.rd_en(rd_en),
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.rst(~rstn),
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.sleep(),
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.wr_clk(clk),
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.wr_en(data_in_valid)
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);
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always @(posedge clk) begin
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if (~rstn) begin
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data_in_valid_reg <= 0;
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running_sum_result <= 0;
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data_out_valid <= 0;
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rd_en <= 0;
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rd_en_start <= 0;
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end else begin
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data_in_valid_reg <= data_in_valid;
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data_out_valid <= data_in_valid_reg;
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rd_en_start <= ((wr_data_count == FIFO_SIZE)?1:rd_en_start);
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rd_en <= (rd_en_start?data_in_valid:rd_en);
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if (data_in_valid) begin
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running_sum_result <= running_sum_result + ext_data_in - (rd_en_start?ext_data_in_old:0);
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end
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end
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end
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endmodule
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