mirror of
https://github.com/jhshi/openofdm.git
synced 2024-12-20 06:08:11 +00:00
314 lines
9.2 KiB
Verilog
314 lines
9.2 KiB
Verilog
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
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`include "openofdm_rx_pre_def.v"
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`timescale 1 ns / 1 ps
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`include "openofdm_rx_git_rev.v"
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module openofdm_rx #
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(
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parameter integer IQ_DATA_WIDTH = 16,
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parameter integer RSSI_HALF_DB_WIDTH = 11,
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parameter integer C_S00_AXI_DATA_WIDTH = 32,
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parameter integer C_S00_AXI_ADDR_WIDTH = 7
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)
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(
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// intf to dot11
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//input wire openofdm_core_rst,
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input wire signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db,
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input wire [(2*IQ_DATA_WIDTH-1):0] sample_in,
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input wire sample_in_strobe,
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output wire demod_is_ongoing, // this needs to be corrected further to indicate actual RF on going regardless the latency
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// output wire pkt_ht,
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output wire short_preamble_detected,
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output wire long_preamble_detected,
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output wire pkt_header_valid,
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output wire pkt_header_valid_strobe,
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output wire ht_unsupport,
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output wire [7:0] pkt_rate,
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output wire [15:0] pkt_len,
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output ht_aggr,
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output ht_aggr_last,
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output wire ht_sgi,
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// output wire [15:0] pkt_len_total, // for interface to byte_to_word.v in rx_intf.v
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output wire byte_out_strobe,
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output wire [7:0] byte_out,
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// output wire [15:0] byte_count_total, // for interface to byte_to_word.v in rx_intf.v
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output wire [15:0] byte_count,
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output wire fcs_out_strobe,
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output wire fcs_ok,
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// for side channel
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output wire [31:0] csi,
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output wire csi_valid,
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output wire signed [31:0] phase_offset_taken,
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output wire [31:0] equalizer,
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output wire equalizer_valid,
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output wire ofdm_symbol_eq_out_pulse,
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// phy len info
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output [14:0] n_ofdm_sym,//max 20166 = (22+65535*8)/26 (max ht len 65535 in sig, min ndbps 26 for mcs0)
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output [9:0] n_bit_in_last_sym,//max ht ndbps 260 (ht mcs7)
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output phy_len_valid,
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// axi lite based register configuration interface
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input wire s00_axi_aclk,
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input wire s00_axi_aresetn,
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input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
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input wire [2 : 0] s00_axi_awprot,
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input wire s00_axi_awvalid,
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output wire s00_axi_awready,
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input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
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input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
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input wire s00_axi_wvalid,
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output wire s00_axi_wready,
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output wire [1 : 0] s00_axi_bresp,
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output wire s00_axi_bvalid,
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input wire s00_axi_bready,
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input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
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input wire [2 : 0] s00_axi_arprot,
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input wire s00_axi_arvalid,
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output wire s00_axi_arready,
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output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
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output wire [1 : 0] s00_axi_rresp,
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output wire s00_axi_rvalid,
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input wire s00_axi_rready
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);
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// reg0~19 for config write; from reg20 for reading status
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg0;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg1; //
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg2;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg3; //
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg4; //
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/*
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg5; //
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg6; //
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg7; //
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg8;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg9; //
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg10;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg11;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg12;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg13;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg14;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg15;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg16;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg17;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg18;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg19; */
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg20; // read openofdm rx core internal state
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/*
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg21;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg22;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg23;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg24;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg25;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg26;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg27;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg28;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg29;
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg30;
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*/
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wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31;
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assign slv_reg31 = `OPENOFDM_RX_GIT_REV;
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wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
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wire receiver_rst;
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signal_watchdog signal_watchdog_inst (
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.clk(s00_axi_aclk),
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.rstn(s00_axi_aresetn),
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.enable(~demod_is_ongoing),
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.i_data(sample_in[31:16]),
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.q_data(sample_in[15:0]),
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.iq_valid(sample_in_strobe),
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.signal_len(pkt_len),
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.sig_valid(sig_valid),
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.max_signal_len_th(slv_reg4[31:16]),
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.dc_running_sum_th(slv_reg2[23:16]),
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.receiver_rst(receiver_rst)
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);
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dot11 # (
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) dot11_i (
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.clock(s00_axi_aclk),
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.enable( 1 ),
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//.reset ( (~s00_axi_aresetn)|slv_reg0[0]|openofdm_core_rst ),
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.reset ( (~s00_axi_aresetn)|slv_reg0[0]|receiver_rst ),
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.power_thres(slv_reg2[10:0]),
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.min_plateau(slv_reg3),
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.threshold_scale(slv_reg1[8]),
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.rssi_half_db(rssi_half_db),
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.sample_in(sample_in),
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.sample_in_strobe(sample_in_strobe),
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.soft_decoding(slv_reg4[0]),
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.force_ht_smoothing(slv_reg1[0]),
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.disable_all_smoothing(slv_reg1[4]),
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// OUTPUT: bytes and FCS status
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.demod_is_ongoing(demod_is_ongoing),
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// .pkt_begin(),
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// .pkt_ht(),
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.pkt_header_valid(pkt_header_valid),
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.pkt_header_valid_strobe(pkt_header_valid_strobe),
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.ht_unsupport(ht_unsupport),
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.pkt_rate(pkt_rate),
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.pkt_len(pkt_len),
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// .pkt_len_total(pkt_len_total),
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.byte_out_strobe(byte_out_strobe),
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.byte_out(byte_out),
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// .byte_count_total(byte_count_total),
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.byte_count(byte_count),
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.fcs_out_strobe(fcs_out_strobe),
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.fcs_ok(fcs_ok),
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.n_ofdm_sym(n_ofdm_sym),//max 20166 = (22+65535*8)/26 (max ht len 65535 in sig, min ndbps 26 for mcs0)
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.n_bit_in_last_sym(n_bit_in_last_sym),//max ht ndbps 260 (ht mcs7)
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.phy_len_valid(phy_len_valid),
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/////////////////////////////////////////////////////////
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// DEBUG PORTS
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/////////////////////////////////////////////////////////
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// decode status
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.state(state),
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.status_code(),
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.state_changed(state_changed),
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.state_history(slv_reg20),
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// power trigger
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.power_trigger(),
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// sync short
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.short_preamble_detected(short_preamble_detected),
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.phase_offset(),
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// sync long
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.sync_long_metric(),
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.sync_long_metric_stb(),
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.long_preamble_detected(long_preamble_detected),
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.sync_long_out(),
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.sync_long_out_strobe(),
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.phase_offset_taken(phase_offset_taken),
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.sync_long_state(),
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// equalizer
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.equalizer_out(equalizer),
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.equalizer_out_strobe(equalizer_valid),
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.equalizer_state(equalizer_state),
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.ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse),
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// legacy signal info
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.legacy_sig_stb(),
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.legacy_rate(),
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.legacy_sig_rsvd(),
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.legacy_len(),
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.legacy_sig_parity(),
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.legacy_sig_parity_ok(),
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.legacy_sig_tail(),
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// ht signal info
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.ht_sig_stb(),
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.ht_mcs(),
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.ht_cbw(),
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.ht_len(),
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.ht_smoothing(),
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.ht_not_sounding(),
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.ht_aggr(ht_aggr),
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.ht_aggr_last(ht_aggr_last),
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.ht_stbc(),
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.ht_fec_coding(),
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.ht_sgi(ht_sgi),
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.ht_num_ext(),
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.ht_sig_crc_ok(),
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// decoding pipeline
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.demod_out(),
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.demod_soft_bits(),
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.demod_soft_bits_pos(),
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.demod_out_strobe(),
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.deinterleave_erase_out(),
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.deinterleave_erase_out_strobe(),
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.conv_decoder_out(),
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.conv_decoder_out_stb(),
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.descramble_out(),
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.descramble_out_strobe(),
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// for side channel
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.csi(csi),
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.csi_valid(csi_valid)
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);
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openofdm_rx_s_axi # (
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.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
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.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
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) openofdm_rx_s_axi_i (
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.S_AXI_ACLK(s00_axi_aclk),
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.S_AXI_ARESETN(s00_axi_aresetn),
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.S_AXI_AWADDR(s00_axi_awaddr),
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.S_AXI_AWPROT(s00_axi_awprot),
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.S_AXI_AWVALID(s00_axi_awvalid),
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.S_AXI_AWREADY(s00_axi_awready),
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.S_AXI_WDATA(s00_axi_wdata),
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.S_AXI_WSTRB(s00_axi_wstrb),
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.S_AXI_WVALID(s00_axi_wvalid),
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.S_AXI_WREADY(s00_axi_wready),
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.S_AXI_BRESP(s00_axi_bresp),
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.S_AXI_BVALID(s00_axi_bvalid),
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.S_AXI_BREADY(s00_axi_bready),
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.S_AXI_ARADDR(s00_axi_araddr),
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.S_AXI_ARPROT(s00_axi_arprot),
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.S_AXI_ARVALID(s00_axi_arvalid),
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.S_AXI_ARREADY(s00_axi_arready),
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.S_AXI_RDATA(s00_axi_rdata),
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.S_AXI_RRESP(s00_axi_rresp),
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.S_AXI_RVALID(s00_axi_rvalid),
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.S_AXI_RREADY(s00_axi_rready),
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.SLV_REG0(slv_reg0),
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.SLV_REG1(slv_reg1),
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.SLV_REG2(slv_reg2),
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.SLV_REG3(slv_reg3),
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.SLV_REG4(slv_reg4), /*,
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.SLV_REG5(slv_reg5),
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.SLV_REG6(slv_reg6),
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.SLV_REG7(slv_reg7),
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.SLV_REG8(slv_reg8),
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.SLV_REG9(slv_reg9),
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.SLV_REG10(slv_reg10),
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.SLV_REG11(slv_reg11),
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.SLV_REG12(slv_reg12),
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.SLV_REG13(slv_reg13),
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.SLV_REG14(slv_reg14),
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.SLV_REG15(slv_reg15),
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.SLV_REG16(slv_reg16),
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.SLV_REG17(slv_reg17),
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.SLV_REG18(slv_reg18),
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.SLV_REG19(slv_reg19),*/
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.SLV_REG20(slv_reg20),/*
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.SLV_REG21(slv_reg21),
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.SLV_REG22(slv_reg22),
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.SLV_REG23(slv_reg23),
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.SLV_REG24(slv_reg24),
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.SLV_REG25(slv_reg25),
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.SLV_REG26(slv_reg26),
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.SLV_REG27(slv_reg27),
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.SLV_REG28(slv_reg28),
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.SLV_REG29(slv_reg29),
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.SLV_REG30(slv_reg30),*/
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.SLV_REG31(slv_reg31)
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);
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endmodule
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