openofdm/docs/source/verilog.rst

Verilog Hacks

Because of the limited capability of FPGA computation, compromises often need to made in the actual Verilog implementation. The most used techniques include quantization and look up table. In , these approximations are used.

Magnitude Estimation

Module: complex_to_mag.v

In the sync_short module, we need to calculate the magnitude of the prod_avg, whose real and imagine part are both 32-bits. To avoid 32-bit multiplication, we use the Magnitude Estimator Trick from DSP Guru. In particular, the magnitude of complex number ⟨I, Q⟩ is estimated as:

M ≈ α * max(|I|,|Q|) + β * min(|I|,|Q|)

And we set α = 1 and β = 0.25 so that only simple bit-shift is needed.

Waveform of complex_to_mag Module

fig_complex_to_mag_wave shows the waveform of the complex_to_mag module. In the first clock cycle, we calculate abs_i and abs_q. In the second cycle, max and min are determined. In the final cycle, the magnitude is calculated.

Phase Estimation

Module:: phase.v

When correcting the frequency offset, we need to estimate the phase of a complex number. The right way of doing this is probably using the CORDIC algorithm. In , we use look up table.

More specifically, we calculate the phase using the arctan function.

$$\theta = \angle(\langle I, Q\rangle) = arctan(\frac{Q}{I})$$

The overall steps are:

1. Project the complex number to the [0, π/4] range, so that the tan(θ) range is [0, 1].
2. Calculate arctan (division required)
3. Looking up the quantized arctan table
4. Project the phase back to the [ − π, π) range

Here we use both quantization and look up table techniques.

Step 1 can be achieved by this transformation:

⟨I, Q⟩ → ⟨max(|I|,|Q|), min(|I|,|Q|)⟩

In the lookup table used in step 3, we use int(tan(θ) * 256) as the key, which effectively maps the [0.0, 1.0] range of tan function to the integer range of [0, 256]. In other words, we quantize the [0, π/4] quadrant into 256 slices.

This arctan look up table is generated using the scripts/gen_atan_lut.py script. The core logic is as follows:

SIZE = 2**8
SCALE = SIZE*2
data = []
for i in range(SIZE):
    key = float(i)/SIZE
    val = int(round(math.atan(key)*SCALE))
    data.append(val)

Note that we also scale up the arctan values to distinguish adjacent values. This also systematically scale up π in . In fact, π is defined as 1608 = int(π * 512) in verilog/common_params.v.

The generated lookup table is stored in the verilog/atan_lut.coe file (see COE File Syntax). Refer to this guide on how to create a look up table in Xilinx ISE. The generated module is stored in verilog/coregen/atan_lut.v.