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103 lines
4.3 KiB
VHDL
103 lines
4.3 KiB
VHDL
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-- This file is owned and controlled by Xilinx and must be used --
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-- solely for design, simulation, implementation and creation of --
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-- design files limited to Xilinx devices or technologies. Use --
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-- with non-Xilinx devices or technologies is expressly prohibited --
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-- and immediately terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
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-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
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-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
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-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
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-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
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-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
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-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
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-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
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-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support --
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-- appliances, devices, or systems. Use in such applications are --
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-- expressly prohibited. --
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-- --
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-- (c) Copyright 1995-2009 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file complex_multiplier.vhd when simulating
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-- the core, complex_multiplier. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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Library XilinxCoreLib;
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-- synthesis translate_on
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ENTITY complex_multiplier IS
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port (
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ar: IN std_logic_VECTOR(15 downto 0);
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ai: IN std_logic_VECTOR(15 downto 0);
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br: IN std_logic_VECTOR(15 downto 0);
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bi: IN std_logic_VECTOR(15 downto 0);
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clk: IN std_logic;
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pr: OUT std_logic_VECTOR(31 downto 0);
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pi: OUT std_logic_VECTOR(31 downto 0));
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END complex_multiplier;
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ARCHITECTURE complex_multiplier_a OF complex_multiplier IS
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-- synthesis translate_off
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component wrapped_complex_multiplier
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port (
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ar: IN std_logic_VECTOR(15 downto 0);
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ai: IN std_logic_VECTOR(15 downto 0);
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br: IN std_logic_VECTOR(15 downto 0);
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bi: IN std_logic_VECTOR(15 downto 0);
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clk: IN std_logic;
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pr: OUT std_logic_VECTOR(31 downto 0);
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pi: OUT std_logic_VECTOR(31 downto 0));
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end component;
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-- Configuration specification
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for all : wrapped_complex_multiplier use entity XilinxCoreLib.cmpy_v3_1(behavioral)
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generic map(
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c_a_width => 16,
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c_ce_overrides_sclr => 0,
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has_negate => 0,
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c_has_sclr => 0,
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c_out_high => 31,
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c_verbosity => 0,
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c_mult_type => 1,
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c_latency => 3,
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c_xdevice => "xc3sd3400a",
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c_has_ce => 0,
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single_output => 0,
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round => 0,
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use_dsp_cascades => 1,
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c_optimize_goal => 0,
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c_xdevicefamily => "spartan3adsp",
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c_out_low => 0,
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c_b_width => 16);
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_complex_multiplier
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port map (
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ar => ar,
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ai => ai,
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br => br,
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bi => bi,
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clk => clk,
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pr => pr,
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pi => pi);
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-- synthesis translate_on
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END complex_multiplier_a;
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