mirror of
https://github.com/jhshi/openofdm.git
synced 2024-12-29 18:19:12 +00:00
570 lines
17 KiB
Verilog
570 lines
17 KiB
Verilog
module sync_long (
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input clock,
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input reset,
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input enable,
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input [31:0] sample_in,
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input sample_in_strobe,
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input signed [15:0] phase_offset,
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input short_gi,
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output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
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input [31:0] rot_data,
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output [31:0] metric,
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output metric_stb,
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output reg long_preamble_detected,
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output reg [31:0] sample_out,
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output reg sample_out_strobe,
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output reg [15:0] num_ofdm_symbol,
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output reg signed [31:0] phase_offset_taken,
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output reg [1:0] state
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);
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`include "common_params.v"
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localparam IN_BUF_LEN_SHIFT = 8;
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localparam NUM_STS_TAIL = 32;
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reg [15:0] in_offset;
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reg [IN_BUF_LEN_SHIFT-1:0] in_waddr;
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reg [IN_BUF_LEN_SHIFT-1:0] in_raddr;
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wire [IN_BUF_LEN_SHIFT-1:0] gi_skip = short_gi? 9: 17;
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reg signed [31:0] num_input_produced;
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reg signed [31:0] num_input_consumed;
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reg signed [31:0] num_input_avail;
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reg [2:0] mult_stage;
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reg [1:0] sum_stage;
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reg mult_strobe;
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wire signed [31:0] stage_sum_i;
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wire signed [31:0] stage_sum_q;
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wire stage_sum_stb;
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reg signed [31:0] sum_i;
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reg signed [31:0] sum_q;
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reg sum_stb;
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reg signed [31:0] phase_correction;
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reg signed [31:0] next_phase_correction;
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reg reset_delay ; // add reset signal for fft, somehow all kinds of event flag raises when feeding real rf signal, maybe reset will help
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wire fft_resetn ;
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always @(posedge clock) begin
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reset_delay = reset ;
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end
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assign fft_resetn = (~reset) & (~reset_delay); // make sure resetn is at least 2 clock cycles low
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complex_to_mag #(.DATA_WIDTH(32)) sum_mag_inst (
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.clock(clock),
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.enable(enable),
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.reset(reset),
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.i(sum_i),
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.q(sum_q),
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.input_strobe(sum_stb),
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.mag(metric),
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.mag_stb(metric_stb)
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);
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reg [31:0] metric_max1;
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reg [(IN_BUF_LEN_SHIFT-1):0] addr1;
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reg [31:0] cross_corr_buf[0:31];
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reg [31:0] stage_X0;
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reg [31:0] stage_X1;
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reg [31:0] stage_X2;
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reg [31:0] stage_X3;
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reg [31:0] stage_X4;
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reg [31:0] stage_X5;
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reg [31:0] stage_X6;
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reg [31:0] stage_X7;
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reg [31:0] stage_Y0;
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reg [31:0] stage_Y1;
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reg [31:0] stage_Y2;
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reg [31:0] stage_Y3;
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reg [31:0] stage_Y4;
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reg [31:0] stage_Y5;
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reg [31:0] stage_Y6;
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reg [31:0] stage_Y7;
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stage_mult stage_mult_inst (
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.clock(clock),
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.enable(enable),
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.reset(reset),
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.X0(stage_X0),
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.X1(stage_X1),
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.X2(stage_X2),
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.X3(stage_X3),
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.X4(stage_X4),
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.X5(stage_X5),
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.X6(stage_X6),
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.X7(stage_X7),
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.Y0(stage_Y0),
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.Y1(stage_Y1),
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.Y2(stage_Y2),
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.Y3(stage_Y3),
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.Y4(stage_Y4),
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.Y5(stage_Y5),
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.Y6(stage_Y6),
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.Y7(stage_Y7),
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.input_strobe(mult_strobe),
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.sum({stage_sum_i, stage_sum_q}),
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.output_strobe(stage_sum_stb)
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);
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localparam S_SKIPPING = 0;
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localparam S_WAIT_FOR_FIRST_PEAK = 1;
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localparam S_IDLE = 2;
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localparam S_FFT = 3;
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reg fft_start;
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//wire fft_start_delayed;
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wire fft_in_stb;
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reg fft_loading;
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wire signed [15:0] fft_in_re;
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wire signed [15:0] fft_in_im;
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wire [22:0] fft_out_re;
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wire [22:0] fft_out_im;
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wire fft_ready;
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wire fft_done;
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wire fft_busy;
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wire fft_valid;
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wire [31:0] fft_out = {fft_out_re[22:7], fft_out_im[22:7]};
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wire signed [15:0] raw_i;
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wire signed [15:0] raw_q;
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reg raw_stb;
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wire idle_line1, idle_line2 ;
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reg fft_din_data_tlast ;
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wire fft_din_data_tlast_delayed ;
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wire event_frame_started;
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wire event_tlast_unexpected;
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wire event_tlast_missing;
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wire event_status_channel_halt;
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wire event_data_in_channel_halt;
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wire event_data_out_channel_halt;
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wire s_axis_config_tready;
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wire m_axis_data_tlast;
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ram_2port #(.DWIDTH(32), .AWIDTH(IN_BUF_LEN_SHIFT)) in_buf (
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.clka(clock),
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.ena(1),
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.wea(sample_in_strobe),
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.addra(in_waddr),
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.dia(sample_in),
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.doa(),
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.clkb(clock),
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.enb(fft_start | fft_loading),
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.web(1'b0),
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.addrb(in_raddr),
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.dib(32'hFFFF),
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.dob({raw_i, raw_q})
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);
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rotate rotate_inst (
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.clock(clock),
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.enable(enable),
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.reset(reset),
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.in_i(raw_i),
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.in_q(raw_q),
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.phase(phase_correction),
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.input_strobe(raw_stb),
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.rot_addr(rot_addr),
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.rot_data(rot_data),
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.out_i(fft_in_re),
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.out_q(fft_in_im),
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.output_strobe(fft_in_stb)
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);
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delayT #(.DATA_WIDTH(1), .DELAY(10)) fft_delay_inst (
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.clock(clock),
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.reset(reset),
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.data_in(fft_din_data_tlast),
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.data_out(fft_din_data_tlast_delayed)
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);
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///the fft7_1 isntance is commented out, as it is upgraded to fft9 version
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/*xfft_v7_1 dft_inst (
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.clk(clock),
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.fwd_inv(1),
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.start(fft_start_delayed),
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.fwd_inv_we(1),
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.xn_re(fft_in_re),
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.xn_im(fft_in_im),
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.xk_re(fft_out_re),
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.xk_im(fft_out_im),
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.rfd(fft_ready),
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.done(fft_done),
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.busy(fft_busy),
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.dv(fft_valid)
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);*/
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xfft_v9 dft_inst (
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.aclk(clock), // input wire aclk
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.aresetn(fft_resetn),
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.s_axis_config_tdata({7'b0, 1'b1}), // input wire [7 : 0] s_axis_config_tdata, use LSB to indicate it is forward transform, the rest should be ignored
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.s_axis_config_tvalid(1'b1), // input wire s_axis_config_tvalid
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.s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready
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.s_axis_data_tdata({fft_in_im, fft_in_re}), // input wire [31 : 0] s_axis_data_tdata
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.s_axis_data_tvalid(fft_in_stb), // input wire s_axis_data_tvalid
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.s_axis_data_tready(fft_ready), // output wire s_axis_data_tready
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.s_axis_data_tlast(fft_din_data_tlast_delayed), // input wire s_axis_data_tlast
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.m_axis_data_tdata({idle_line1,fft_out_im, idle_line2, fft_out_re}), // output wire [47 : 0] m_axis_data_tdata
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.m_axis_data_tvalid(fft_valid), // output wire m_axis_data_tvalid
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.m_axis_data_tready(1'b1), // input wire m_axis_data_tready
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.m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast
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.event_frame_started(event_frame_started), // output wire event_frame_started
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.event_tlast_unexpected(event_tlast_unexpected), // output wire event_tlast_unexpected
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.event_tlast_missing(event_tlast_missing), // output wire event_tlast_missing
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.event_status_channel_halt(event_status_channel_halt), // output wire event_status_channel_halt
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.event_data_in_channel_halt(event_data_in_channel_halt), // output wire event_data_in_channel_halt
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.event_data_out_channel_halt(event_data_out_channel_halt) // output wire event_data_out_channel_halt
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);
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reg [15:0] num_sample;
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integer i;
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integer j;
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always @(posedge clock) begin
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if (reset) begin
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for (j = 0; j < 32; j= j+1) begin
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cross_corr_buf[j] <= 0;
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end
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do_clear();
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state <= S_SKIPPING;
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fft_din_data_tlast <= 1'b0;
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end else if (enable) begin
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if (sample_in_strobe && state != S_SKIPPING) begin
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in_waddr <= in_waddr + 1;
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num_input_produced <= num_input_produced + 1;
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end
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num_input_avail <= num_input_produced - num_input_consumed;
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case(state)
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S_SKIPPING: begin
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// skip the tail of short preamble
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if (num_sample >= NUM_STS_TAIL) begin
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num_sample <= 0;
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state <= S_WAIT_FOR_FIRST_PEAK;
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end else if (sample_in_strobe) begin
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num_sample <= num_sample + 1;
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end
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end
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S_WAIT_FOR_FIRST_PEAK: begin
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do_mult();
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if (metric_stb && (metric > metric_max1)) begin
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metric_max1 <= metric;
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addr1 <= in_raddr - 1;
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end
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if (num_sample >= 88) begin
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long_preamble_detected <= 1;
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num_sample <= 0;
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mult_strobe <= 0;
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sum_stb <= 0;
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// offset it by the length of cross correlation buffer
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// size
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in_raddr <= addr1 - 32;
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num_input_consumed <= addr1 - 32;
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in_offset <= 0;
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num_ofdm_symbol <= 0;
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phase_correction <= 0;
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next_phase_correction <= phase_offset;
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phase_offset_taken <= phase_offset;
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state <= S_FFT;
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end else if (metric_stb) begin
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num_sample <= num_sample + 1;
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end
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end
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S_FFT: begin
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if (long_preamble_detected) begin
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`ifdef DEBUG_PRINT
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$display("Long preamble detected");
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`endif
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long_preamble_detected <= 0;
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end
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if (~fft_loading && num_input_avail > 88) begin
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fft_start <= 1;
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in_offset <= 0;
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end
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if (fft_start) begin
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fft_start <= 0;
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fft_loading <= 1;
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end
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raw_stb <= fft_start | fft_loading;
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if (raw_stb) begin
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if (phase_offset > 0) begin
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if (next_phase_correction > PI) begin
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phase_correction <= next_phase_correction - DOUBLE_PI;
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if(in_offset == 63 && num_ofdm_symbol > 0)
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next_phase_correction <= next_phase_correction - DOUBLE_PI + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
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else
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next_phase_correction <= next_phase_correction - DOUBLE_PI + phase_offset;
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end else begin
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phase_correction <= next_phase_correction;
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if(in_offset == 63 && num_ofdm_symbol > 0)
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next_phase_correction <= next_phase_correction + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
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else
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next_phase_correction <= next_phase_correction + phase_offset;
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end
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end else begin
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if (next_phase_correction < -PI) begin
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phase_correction <= next_phase_correction + DOUBLE_PI;
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if(in_offset == 63 && num_ofdm_symbol > 0)
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next_phase_correction <= next_phase_correction + DOUBLE_PI + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
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else
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next_phase_correction <= next_phase_correction + DOUBLE_PI + phase_offset;
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end else begin
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phase_correction <= next_phase_correction;
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if(in_offset == 63 && num_ofdm_symbol > 0)
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next_phase_correction <= next_phase_correction + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
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else
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next_phase_correction <= next_phase_correction + phase_offset;
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end
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end
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end
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if (fft_start | fft_loading) begin
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in_offset <= in_offset + 1;
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if( in_offset == 62) begin
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fft_din_data_tlast <= 1'b1;
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end
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if (in_offset == 63) begin
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fft_din_data_tlast <= 1'b0;
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fft_loading <= 0;
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num_ofdm_symbol <= num_ofdm_symbol + 1;
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if (num_ofdm_symbol > 0) begin
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// skip the Guard Interval for data symbols
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in_raddr <= in_raddr + gi_skip;
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num_input_consumed <= num_input_consumed + gi_skip;
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end else begin
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in_raddr <= in_raddr + 1;
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num_input_consumed <= num_input_consumed + 1;
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end
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end else begin
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in_raddr <= in_raddr + 1;
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num_input_consumed <= num_input_consumed + 1;
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end
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end
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sample_out_strobe <= fft_valid;
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sample_out <= fft_out;
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end
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S_IDLE: begin
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end
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default: begin
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state <= S_WAIT_FOR_FIRST_PEAK;
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end
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endcase
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end else begin
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sample_out_strobe <= 0;
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end
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end
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integer do_mult_i;
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task do_mult; begin
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// cross correlation of the first 16 samples of LTS
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if (sample_in_strobe) begin
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cross_corr_buf[31] <= sample_in;
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for (do_mult_i = 0; do_mult_i < 31; do_mult_i = do_mult_i+1) begin
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cross_corr_buf[do_mult_i] <= cross_corr_buf[do_mult_i+1];
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end
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sum_stage <= 0;
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sum_i <= 0;
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sum_q <= 0;
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sum_stb <= 0;
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stage_X0 <= cross_corr_buf[1];
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stage_X1 <= cross_corr_buf[2];
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stage_X2 <= cross_corr_buf[3];
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stage_X3 <= cross_corr_buf[4];
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stage_X4 <= cross_corr_buf[5];
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stage_X5 <= cross_corr_buf[6];
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stage_X6 <= cross_corr_buf[7];
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stage_X7 <= cross_corr_buf[8];
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stage_Y0 <= { 16'd156, 16'd0};
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stage_Y1 <= {-16'd5, 16'd120};
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stage_Y2 <= { 16'd40, 16'd111};
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stage_Y3 <= { 16'd97, -16'd83};
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stage_Y4 <= { 16'd21, -16'd28};
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stage_Y5 <= { 16'd60, 16'd88};
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stage_Y6 <= {-16'd115, 16'd55};
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stage_Y7 <= {-16'd38, 16'd106};
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mult_strobe <= 1;
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mult_stage <= 1;
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end
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if (mult_stage == 1) begin
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stage_X0 <= cross_corr_buf[8];
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stage_X1 <= cross_corr_buf[9];
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stage_X2 <= cross_corr_buf[10];
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stage_X3 <= cross_corr_buf[11];
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stage_X4 <= cross_corr_buf[12];
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stage_X5 <= cross_corr_buf[13];
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stage_X6 <= cross_corr_buf[14];
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stage_X7 <= cross_corr_buf[15];
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stage_Y0 <= { 16'd98, 16'd26};
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stage_Y1 <= { 16'd53, -16'd4};
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stage_Y2 <= { 16'd1, 16'd115};
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stage_Y3 <= {-16'd137, 16'd47};
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stage_Y4 <= { 16'd24, 16'd59};
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stage_Y5 <= { 16'd59, 16'd15};
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stage_Y6 <= {-16'd22, -16'd161};
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stage_Y7 <= { 16'd119, 16'd4};
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mult_stage <= 2;
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end else if (mult_stage == 2) begin
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stage_X0 <= cross_corr_buf[16];
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stage_X1 <= cross_corr_buf[17];
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stage_X2 <= cross_corr_buf[18];
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stage_X3 <= cross_corr_buf[19];
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stage_X4 <= cross_corr_buf[20];
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stage_X5 <= cross_corr_buf[21];
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stage_X6 <= cross_corr_buf[22];
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stage_X7 <= cross_corr_buf[23];
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stage_Y0 <= { 16'd62, 16'd62};
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stage_Y1 <= { 16'd37, -16'd98};
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stage_Y2 <= {-16'd57, -16'd39};
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stage_Y3 <= {-16'd131, -16'd65};
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stage_Y4 <= { 16'd82, -16'd92};
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stage_Y5 <= { 16'd70, -16'd14};
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stage_Y6 <= {-16'd60, -16'd81};
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stage_Y7 <= {-16'd56, 16'd22};
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mult_stage <= 3;
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end else if (mult_stage == 3) begin
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stage_X0 <= cross_corr_buf[24];
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stage_X1 <= cross_corr_buf[25];
|
|
stage_X2 <= cross_corr_buf[26];
|
|
stage_X3 <= cross_corr_buf[27];
|
|
stage_X4 <= cross_corr_buf[28];
|
|
stage_X5 <= cross_corr_buf[29];
|
|
stage_X6 <= cross_corr_buf[30];
|
|
stage_X7 <= cross_corr_buf[31];
|
|
|
|
stage_Y0 <= {-16'd35, 16'd151};
|
|
stage_Y1 <= {-16'd122, 16'd17};
|
|
stage_Y2 <= {-16'd127, 16'd21};
|
|
stage_Y3 <= { 16'd75, 16'd74};
|
|
stage_Y4 <= {-16'd3, -16'd54};
|
|
stage_Y5 <= {-16'd92, -16'd115};
|
|
stage_Y6 <= { 16'd92, -16'd106};
|
|
stage_Y7 <= { 16'd12, -16'd98};
|
|
|
|
mult_stage <= 4;
|
|
end else if (mult_stage == 4) begin
|
|
mult_stage <= 0;
|
|
mult_strobe <= 0;
|
|
in_raddr <= in_raddr + 1;
|
|
num_input_consumed <= num_input_consumed + 1;
|
|
end
|
|
|
|
if (stage_sum_stb) begin
|
|
sum_stage <= sum_stage + 1;
|
|
sum_i <= sum_i + stage_sum_i;
|
|
sum_q <= sum_q + stage_sum_q;
|
|
if (sum_stage == 3) begin
|
|
sum_stb <= 1;
|
|
end
|
|
end else begin
|
|
sum_stb <= 0;
|
|
sum_i <= 0;
|
|
sum_q <= 0;
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task do_clear; begin
|
|
|
|
in_waddr <= 0;
|
|
in_raddr <= 0;
|
|
in_offset <= 0;
|
|
num_input_produced <= 0;
|
|
num_input_consumed <= 0;
|
|
num_input_avail <= 0;
|
|
|
|
phase_correction <= 0;
|
|
next_phase_correction <= 0;
|
|
|
|
raw_stb <= 0;
|
|
|
|
sum_i <= 0;
|
|
sum_q <= 0;
|
|
sum_stb <= 0;
|
|
sum_stage <= 0;
|
|
mult_strobe <= 0;
|
|
|
|
metric_max1 <= 0;
|
|
addr1 <= 0;
|
|
|
|
mult_stage <= 0;
|
|
|
|
long_preamble_detected <= 0;
|
|
num_sample <= 0;
|
|
num_ofdm_symbol <= 0;
|
|
|
|
fft_start <= 0;
|
|
fft_loading <= 0;
|
|
|
|
sample_out_strobe <= 0;
|
|
sample_out <= 0;
|
|
|
|
stage_X0 <= 0;
|
|
stage_X1 <= 0;
|
|
stage_X2 <= 0;
|
|
stage_X3 <= 0;
|
|
stage_X4 <= 0;
|
|
stage_X5 <= 0;
|
|
stage_X6 <= 0;
|
|
stage_X7 <= 0;
|
|
|
|
stage_Y0 <= 0;
|
|
stage_Y1 <= 0;
|
|
stage_Y2 <= 0;
|
|
stage_Y3 <= 0;
|
|
stage_Y4 <= 0;
|
|
stage_Y5 <= 0;
|
|
stage_Y6 <= 0;
|
|
stage_Y7 <= 0;
|
|
end
|
|
endtask
|
|
|
|
endmodule
|