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132 Commits 1 Branch 0 Tags 28 MiB
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6 Commits

Author SHA1 Message Date
Xianjun Jiao
a7b95b492c Workaround to supress the error message when the 1st time run simulation 2022-05-13 13:21:19 +02:00
mmehari
36c738fe98 phase estimation update: quadrant quantization from 256 slices -> 512 slices 2022-01-04 22:15:16 +01:00
Xianjun Jiao
abbe9ecde9 extend support to zcu102/Zynq MPSoC ultra_scale 2020-04-27 15:46:16 +02:00
Xianjun Jiao
2643844f2f necessary bug fixes and improvements for openwifi 2019-12-10 13:31:16 +01:00
weiliu
10ff8da3d7 port dot11 to zynq 2019-12-10 14:09:31 +01:00
Jinghao Shi
9edf1899bd verilog init 2017-04-03 12:52:03 -04:00