ExternalVendorCode/openofdm
1
0
Fork 0
mirror of https://github.com/jhshi/openofdm.git synced 2024-12-19 21:58:14 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge pull request #25 from open-sdr/dot11zynq

Browse Source 
Changes for openwifi coming release
This commit is contained in:
Jinghao Shi 2023-01-28 21:08:45 -08:00 committed by GitHub
commit ea638eb2d3
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
23 changed files with 1585 additions and 1499 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

79
create_vivado_proj.sh Executable file
View File

@ -0,0 +1,79 @@
#!/bin/bash
# Author: Xianjun jiao
# SPDX-FileCopyrightText: 2022 UGent
# SPDX-License-Identifier: AGPL-3.0-or-later
print_usage () {
echo "usage:"
echo "Need at least 2 arguments: \$XILINX_DIR \$TCL_FILENAME"
echo "More arguments (max 7) will be passed as arguments to the .tcl script to create ip_name_pre_def.v"
echo "Among these max 7 arguments:"
echo "- the 1st: BOARD_NAME (antsdr antsdr_e200 sdrpi zc706_fmcs2 zed_fmcs2 zc702_fmcs2 adrv9361z7035 adrv9364z7020 zcu102_fmcs2 neptunesdr)"
echo "- the 2nd: NUM_CLK_PER_US (for example: input 100 for 100MHz)"
echo "- the 3rd-7th: User pre defines (assume it is ABC) for conditional compiling. Will be \`define IP_NAME_ABC in ip_name_pre_def.v"
echo " - the 3rd exception: in the case of openofdm_rx, it indicates SAMPLE_FILE for simulation. Can be changed later in openofdm_rx_pre_def.v"
}
print_usage
if [ "$#" -lt 2 ]; then
exit 1
fi
XILINX_DIR=$1
TCL_FILENAME=$2
echo XILINX_DIR $XILINX_DIR
echo TCL_FILENAME $TCL_FILENAME
if [ -d "$XILINX_DIR/Vivado" ]; then
echo "\$XILINX_DIR is found!"
else
echo "\$XILINX_DIR is not correct. Please check!"
exit 1
fi
if [ -f "$TCL_FILENAME" ]; then
echo "\$TCL_FILENAME is found!"
else
echo "\$TCL_FILENAME does NOT exist. Please check!"
exit 1
fi
source $XILINX_DIR/Vivado/2021.1/settings64.sh
ARG1=""
ARG2=""
ARG3=""
ARG4=""
ARG5=""
ARG6=""
ARG7=""
if [[ -n $3 ]]; then
ARG1=$3
fi
if [[ -n $4 ]]; then
ARG2=$4
fi
if [[ -n $5 ]]; then
ARG3=$5
fi
if [[ -n $6 ]]; then
ARG4=$6
fi
if [[ -n $7 ]]; then
ARG5=$7
fi
if [[ -n $8 ]]; then
ARG6=$8
fi
if [[ -n $9 ]]; then
ARG7=$9
fi
set -x
vivado -source $TCL_FILENAME -tclargs $ARG1 $ARG2 $ARG3 $ARG4 $ARG5 $ARG6 $ARG7
set +x

155
openofdm_rx.tcl
View File

@ -16,6 +16,99 @@
# #
#***************************************************************************************** #*****************************************************************************************
#-----------process arguments (if exist)-------
# set argv [] before source this .tcl to not having any arguments
# set argv [list ARGUMENT1 ARGUMENT2 ...] to before source this .tcl to have arguments
# argument 1: BOARD_NAME
# argument 2: NUM_CLK_PER_US. For example: input 100 for 100MHz. Valid values: 100/200/240/400
# argument 3: IQ sample filename with full path (for SAMPLE_FILE in dot11_tb.v). Change it in pre_def.v according to your need later on.
# argument 4~7 (if exist): for `define OPENOFDM_RX_ARGUMENT in openofdm_rx_pre_def.v to enable some compiling time conditions
set ARGUMENT1 [lindex $argv 0]
set ARGUMENT2 [lindex $argv 1]
set ARGUMENT3 [lindex $argv 2]
set ARGUMENT4 [lindex $argv 3]
set ARGUMENT5 [lindex $argv 4]
set ARGUMENT6 [lindex $argv 5]
set ARGUMENT7 [lindex $argv 6]
if {$ARGUMENT1 eq ""} {
set BOARD_NAME zed_fmcs2
} else {
set BOARD_NAME $ARGUMENT1
}
if {$ARGUMENT2 eq ""} {
set NUM_CLK_PER_US 100
} else {
set NUM_CLK_PER_US $ARGUMENT2
}
source ./parse_board_name.tcl
set MODULE_NAME OPENOFDM_RX
set fd [open "./verilog/openofdm_rx_pre_def.v" w]
if {$NUM_CLK_PER_US == 100} {
puts $fd "`define CLK_SPEED_100M"
} elseif {$NUM_CLK_PER_US == 200} {
puts $fd "`define CLK_SPEED_200M"
} elseif {$NUM_CLK_PER_US == 240} {
puts $fd "`define CLK_SPEED_240M"
} elseif {$NUM_CLK_PER_US == 400} {
puts $fd "`define CLK_SPEED_400M"
} else {
throw {NUM_CLK_PER_US MUST BE 100/200/240/400!}
}
puts $fd "`define BETTER_SENSITIVITY"
if {$ARGUMENT3 eq ""} {
puts $fd "`define SAMPLE_FILE \"../../../../../testing_inputs/simulated/ht_mcs7_gi1_aggr0_len14_pre100_post200_openwifi.txt\""
} else {
puts $fd "`define SAMPLE_FILE \"$ARGUMENT3\""
}
if {$ARGUMENT4 eq ""} {
puts $fd " "
} else {
puts $fd "`define $MODULE_NAME\_$ARGUMENT4"
}
if {$ARGUMENT5 eq ""} {
puts $fd " "
} else {
puts $fd "`define $MODULE_NAME\_$ARGUMENT5"
}
if {$ARGUMENT6 eq ""} {
puts $fd " "
} else {
puts $fd "`define $MODULE_NAME\_$ARGUMENT6"
}
if {$ARGUMENT7 eq ""} {
puts $fd " "
} else {
puts $fd "`define $MODULE_NAME\_$ARGUMENT7"
}
close $fd
#-----end of process arguments (if exist)-------
puts "BOARD_NAME $BOARD_NAME"
puts "NUM_CLK_PER_US $NUM_CLK_PER_US"
puts "ultra_scale_flag $ultra_scale_flag"
puts "part_string $part_string"
puts "fpga_size_flag $fpga_size_flag"
puts "ARGUMENT3 $ARGUMENT3"
puts "ARGUMENT4 $MODULE_NAME\_$ARGUMENT4"
puts "ARGUMENT5 $MODULE_NAME\_$ARGUMENT5"
puts "ARGUMENT6 $MODULE_NAME\_$ARGUMENT6"
puts "ARGUMENT7 $MODULE_NAME\_$ARGUMENT7"
#------------some defines related to sub-IP---------------------
if {$ultra_scale_flag == 0} {
set ip_fix_string zynq
} else {
set ip_fix_string zynquplus
}
#-----end of some defines related to sub-IP---------------------
# -----------generate openofdm_rx_git_rev.v--------------- # -----------generate openofdm_rx_git_rev.v---------------
set fd [open "./verilog/openofdm_rx_git_rev.v" w] set fd [open "./verilog/openofdm_rx_git_rev.v" w]
set HASHCODE [exec ./get_git_rev.sh] set HASHCODE [exec ./get_git_rev.sh]
@ -26,6 +119,15 @@ close $fd
# Set the reference directory for source file relative paths (by default the value is script directory path) # Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir [file dirname [info script]] set origin_dir [file dirname [info script]]
#----------Copy the IP files to a dedicated/git-un-tracked ip_repo folder-----------------------
#----------because they will be changed during status reporting and upgrading at the end--------
file delete -force $origin_dir/ip_repo
file mkdir $origin_dir/ip_repo
file copy -force $origin_dir/verilog/coregen/div_gen_new_ip_core_$ip_fix_string $origin_dir/ip_repo/div_gen_new
exec cp -rf $origin_dir/verilog/Xilinx/$ip_fix_string/. $origin_dir/ip_repo/
#---end of copy---------------------------------------------------------------------------------
# Use origin directory path location variable, if specified in the tcl shell # Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } { if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc set origin_dir $::origin_dir_loc
@ -92,7 +194,7 @@ if { $::argc > 0 } {
set src_dir "[file normalize "$origin_dir/verilog"]" set src_dir "[file normalize "$origin_dir/verilog"]"
# Create project # Create project
create_project ${project_name} ./${project_name} -part xc7z045ffg900-2 create_project ${project_name} ./${project_name} -part $part_string
# Set the directory path for the new project # Set the directory path for the new project
set proj_dir [get_property directory [current_project]] set proj_dir [get_property directory [current_project]]
@ -103,7 +205,7 @@ set proj_dir [get_property directory [current_project]]
# Set project properties # Set project properties
set obj [current_project] set obj [current_project]
set_property -name "board_connections" -value "" -objects $obj set_property -name "board_connections" -value "" -objects $obj
set_property -name "board_part" -value "xilinx.com:zc706:part0:1.2" -objects $obj # set_property -name "board_part" -value "xilinx.com:zc706:part0:1.2" -objects $obj
set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/activehdl" -objects $obj set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/activehdl" -objects $obj
set_property -name "compxlib.funcsim" -value "1" -objects $obj set_property -name "compxlib.funcsim" -value "1" -objects $obj
set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/ies" -objects $obj set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/ies" -objects $obj
@ -145,7 +247,7 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
# Set IP repository paths # Set IP repository paths
set obj [get_filesets sources_1] set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynq"]" $obj set_property "ip_repo_paths" "[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_$ip_fix_string"]" $obj
# Rebuild user ip_repo's index before adding any source files # Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild update_ip_catalog -rebuild
@ -153,8 +255,6 @@ update_ip_catalog -rebuild
# Set 'sources_1' fileset object # Set 'sources_1' fileset object
set obj [get_filesets sources_1] set obj [get_filesets sources_1]
set files [list \ set files [list \
"[file normalize "$origin_dir/verilog/Xilinx/zynq/complex_multiplier/complex_multiplier.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/atan_lut/atan_lut.xci"]"\
"[file normalize "$origin_dir/verilog/bits_to_bytes.v"]"\ "[file normalize "$origin_dir/verilog/bits_to_bytes.v"]"\
"[file normalize "$origin_dir/verilog/calc_mean.v"]"\ "[file normalize "$origin_dir/verilog/calc_mean.v"]"\
"[file normalize "$origin_dir/verilog/complex_mult.v"]"\ "[file normalize "$origin_dir/verilog/complex_mult.v"]"\
@ -163,16 +263,17 @@ set files [list \
"[file normalize "$origin_dir/verilog/crc32.v"]"\ "[file normalize "$origin_dir/verilog/crc32.v"]"\
"[file normalize "$origin_dir/verilog/deinterleave.v"]"\ "[file normalize "$origin_dir/verilog/deinterleave.v"]"\
"[file normalize "$origin_dir/verilog/delayT.v"]"\ "[file normalize "$origin_dir/verilog/delayT.v"]"\
"[file normalize "$origin_dir/verilog/delay_sample.v"]"\ "[file normalize "$origin_dir/verilog/fifo_sample_delay.v"]"\
"[file normalize "$origin_dir/verilog/common_defs.v"]"\ "[file normalize "$origin_dir/verilog/common_defs.v"]"\
"[file normalize "$origin_dir/verilog/demodulate.v"]"\ "[file normalize "$origin_dir/verilog/demodulate.v"]"\
"[file normalize "$origin_dir/verilog/descramble.v"]"\ "[file normalize "$origin_dir/verilog/descramble.v"]"\
"[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynq/src/div_gen.v"]"\
"[file normalize "$origin_dir/verilog/divider.v"]"\ "[file normalize "$origin_dir/verilog/divider.v"]"\
"[file normalize "$origin_dir/verilog/dot11.v"]"\ "[file normalize "$origin_dir/verilog/dot11.v"]"\
"[file normalize "$origin_dir/verilog/equalizer.v"]"\ "[file normalize "$origin_dir/verilog/equalizer.v"]"\
"[file normalize "$origin_dir/verilog/ht_sig_crc.v"]"\ "[file normalize "$origin_dir/verilog/ht_sig_crc.v"]"\
"[file normalize "$origin_dir/verilog/moving_avg.v"]"\ "[file normalize "$origin_dir/verilog/moving_avg.v"]"\
"[file normalize "$origin_dir/verilog/mv_avg.v"]"\
"[file normalize "$origin_dir/verilog/mv_avg_dual_ch.v"]"\
"[file normalize "$origin_dir/verilog/ofdm_decoder.v"]"\ "[file normalize "$origin_dir/verilog/ofdm_decoder.v"]"\
"[file normalize "$origin_dir/verilog/openofdm_rx_s_axi.v"]"\ "[file normalize "$origin_dir/verilog/openofdm_rx_s_axi.v"]"\
"[file normalize "$origin_dir/verilog/phase.v"]"\ "[file normalize "$origin_dir/verilog/phase.v"]"\
@ -184,15 +285,19 @@ set files [list \
"[file normalize "$origin_dir/verilog/openofdm_rx.v"]"\ "[file normalize "$origin_dir/verilog/openofdm_rx.v"]"\
"[file normalize "$origin_dir/verilog/running_sum_dual_ch.v"]"\ "[file normalize "$origin_dir/verilog/running_sum_dual_ch.v"]"\
"[file normalize "$origin_dir/verilog/signal_watchdog.v"]"\ "[file normalize "$origin_dir/verilog/signal_watchdog.v"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/deinter_lut/deinter_lut.coe"]"\ "[file normalize "$origin_dir/verilog/phy_len_calculation.v"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/atan_lut/atan_lut.coe"]"\ "[file normalize "$origin_dir/ip_repo/complex_multiplier/complex_multiplier.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/rot_lut/rot_lut.coe"]"\ "[file normalize "$origin_dir/ip_repo/atan_lut/atan_lut.coe"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/viterbi/viterbi_v7_0.xci"]"\ "[file normalize "$origin_dir/ip_repo/atan_lut/atan_lut.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/deinter_lut/deinter_lut.xci"]"\ "[file normalize "$origin_dir/ip_repo/viterbi/viterbi_v7_0.xci"]"\
"[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynq/src/div_gen_div_gen_0_0/div_gen_div_gen_0_0.xci"]"\ "[file normalize "$origin_dir/ip_repo/deinter_lut/deinter_lut.coe"]"\
"[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynq/src/div_gen_xlslice_0_0/div_gen_xlslice_0_0.xci"]"\ "[file normalize "$origin_dir/ip_repo/deinter_lut/deinter_lut.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/xfft/xfft_v9.xci"]"\ "[file normalize "$origin_dir/ip_repo/xfft/xfft_v9.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/rot_lut/rot_lut.xci"]"\ "[file normalize "$origin_dir/ip_repo/rot_lut/rot_lut.coe"]"\
"[file normalize "$origin_dir/ip_repo/rot_lut/rot_lut.xci"]"\
"[file normalize "$origin_dir/ip_repo/div_gen_new/src/div_gen.v"]"\
"[file normalize "$origin_dir/ip_repo/div_gen_new/src/div_gen_div_gen_0_0/div_gen_div_gen_0_0.xci"]"\
"[file normalize "$origin_dir/ip_repo/div_gen_new/src/div_gen_xlslice_0_0/div_gen_xlslice_0_0.xci"]"\
] ]
# If you want to make a copy of the file to new src folder, use following command # If you want to make a copy of the file to new src folder, use following command
# set imported_files [import_files -fileset sources_1 $files] # set imported_files [import_files -fileset sources_1 $files]
@ -226,6 +331,11 @@ set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "0" -objects $file_obj set_property -name "used_in_implementation" -value "0" -objects $file_obj
set file "phy_len_calculation.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "0" -objects $file_obj
# Set 'sources_1' fileset file properties for local files # Set 'sources_1' fileset file properties for local files
# Set 'sources_1' fileset properties # Set 'sources_1' fileset properties
@ -308,7 +418,7 @@ set_property -name "xsim.simulate.xsim.more_options" -value "" -objects $obj
# Create 'synth_1' run (if not found) # Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} { if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xc7z045ffg900-2 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 create_run -name synth_1 -part $part_string -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
} else { } else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2018" [get_runs synth_1] set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
@ -373,7 +483,7 @@ current_run -synthesis [get_runs synth_1]
# Create 'impl_1' run (if not found) # Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} { if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part xc7z045ffg900-2 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 create_run -name impl_1 -part $part_string -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
} else { } else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2018" [get_runs impl_1] set_property flow "Vivado Implementation 2018" [get_runs impl_1]
@ -778,3 +888,12 @@ set_property -name "steps.write_bitstream.args.more options" -value "" -objects
current_run -implementation [get_runs impl_1] current_run -implementation [get_runs impl_1]
puts "INFO: Project created:$project_name" puts "INFO: Project created:$project_name"
#--------to avoid IP error message (parameter error or not found, need to be reported status and upgraded)-------
update_compile_order -fileset sources_1
report_ip_status -name ip_status
upgrade_ip [get_ips {atan_lut complex_multiplier deinter_lut div_gen_div_gen_0_0 div_gen_xlslice_0_0 rot_lut viterbi_v7_0 xfft_v9}] -log ip_upgrade.log
export_ip_user_files -of_objects [get_ips {atan_lut complex_multiplier deinter_lut div_gen_div_gen_0_0 div_gen_xlslice_0_0 rot_lut viterbi_v7_0 xfft_v9}] -no_script -sync -force -quiet
update_compile_order -fileset sources_1
report_ip_status -name ip_status

777
openofdm_rx_ultra_scale.tcl
View File

@ -1,777 +0,0 @@
#*****************************************************************************************
#
# By xianjun.jiao@imec.be; wei.liu@imec.be
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#
#*****************************************************************************************
# -----------generate openofdm_rx_git_rev.v---------------
set fd [open "./verilog/openofdm_rx_git_rev.v" w]
set HASHCODE [exec ./get_git_rev.sh]
puts $fd "`define OPENOFDM_RX_GIT_REV (32'h$HASHCODE)"
close $fd
# ----end of generate openofdm_rx_git_rev.v---------------
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir [file dirname [info script]]
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
# Set the project name
set project_name "openofdm_rx_ultra_scale"
exec rm -rf $project_name
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
set project_name $::user_project_name
}
variable script_file
set script_file "openofdm_rx_ultra_scale.tcl"
# Help information for this script
proc help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--project_name <name>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--project_name <name>\] Create project with the specified name. Default"
puts " name is the name of the project from where this"
puts " script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < [llength $::argc]} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--project_name" { incr i; set project_name [lindex $::argv $i] }
"--help" { help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
set src_dir "[file normalize "$origin_dir/verilog"]"
# Create project
create_project ${project_name} ./${project_name} -part xczu9eg-ffvb1156-2-e
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Reconstruct message rules
# None
# Set project properties
set obj [current_project]
set_property -name "board_connections" -value "" -objects $obj
set_property -name "board_part" -value "xilinx.com:zcu102:part0:3.1" -objects $obj
set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/activehdl" -objects $obj
set_property -name "compxlib.funcsim" -value "1" -objects $obj
set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/ies" -objects $obj
set_property -name "compxlib.modelsim_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/modelsim" -objects $obj
set_property -name "compxlib.overwrite_libs" -value "0" -objects $obj
set_property -name "compxlib.questa_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/questa" -objects $obj
set_property -name "compxlib.riviera_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/riviera" -objects $obj
set_property -name "compxlib.timesim" -value "1" -objects $obj
set_property -name "compxlib.vcs_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/vcs" -objects $obj
set_property -name "compxlib.xsim_compiled_library_dir" -value "" -objects $obj
set_property -name "corecontainer.enable" -value "0" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "dsa.num_compute_units" -value "60" -objects $obj
set_property -name "dsa.rom.debug_type" -value "0" -objects $obj
set_property -name "dsa.rom.prom_type" -value "0" -objects $obj
set_property -name "enable_optional_runs_sta" -value "0" -objects $obj
set_property -name "generate_ip_upgrade_log" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_interface_inference_priority" -value "" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${project_name}.cache/ip" -objects $obj
set_property -name "project_type" -value "Default" -objects $obj
set_property -name "pr_flow" -value "0" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "sim.use_ip_compiled_libs" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "source_mgmt_mode" -value "All" -objects $obj
set_property -name "target_language" -value "Verilog" -objects $obj
set_property -name "target_simulator" -value "XSim" -objects $obj
set_property -name "xpm_libraries" -value "XPM_MEMORY" -objects $obj
set_property -name "xsim.array_display_limit" -value "1024" -objects $obj
set_property -name "xsim.radix" -value "hex" -objects $obj
set_property -name "xsim.time_unit" -value "ns" -objects $obj
set_property -name "xsim.trace_limit" -value "65536" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
# Set IP repository paths
set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynquplus"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/complex_multiplier/complex_multiplier.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/atan_lut/atan_lut.xci"]"\
"[file normalize "$origin_dir/verilog/bits_to_bytes.v"]"\
"[file normalize "$origin_dir/verilog/calc_mean.v"]"\
"[file normalize "$origin_dir/verilog/complex_mult.v"]"\
"[file normalize "$origin_dir/verilog/complex_to_mag.v"]"\
"[file normalize "$origin_dir/verilog/complex_to_mag_sq.v"]"\
"[file normalize "$origin_dir/verilog/crc32.v"]"\
"[file normalize "$origin_dir/verilog/deinterleave.v"]"\
"[file normalize "$origin_dir/verilog/delayT.v"]"\
"[file normalize "$origin_dir/verilog/delay_sample.v"]"\
"[file normalize "$origin_dir/verilog/common_defs.v"]"\
"[file normalize "$origin_dir/verilog/demodulate.v"]"\
"[file normalize "$origin_dir/verilog/descramble.v"]"\
"[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen.v"]"\
"[file normalize "$origin_dir/verilog/divider.v"]"\
"[file normalize "$origin_dir/verilog/dot11.v"]"\
"[file normalize "$origin_dir/verilog/equalizer.v"]"\
"[file normalize "$origin_dir/verilog/ht_sig_crc.v"]"\
"[file normalize "$origin_dir/verilog/moving_avg.v"]"\
"[file normalize "$origin_dir/verilog/ofdm_decoder.v"]"\
"[file normalize "$origin_dir/verilog/openofdm_rx_s_axi.v"]"\
"[file normalize "$origin_dir/verilog/phase.v"]"\
"[file normalize "$origin_dir/verilog/usrp2/ram_2port.v"]"\
"[file normalize "$origin_dir/verilog/rotate.v"]"\
"[file normalize "$origin_dir/verilog/stage_mult.v"]"\
"[file normalize "$origin_dir/verilog/sync_long.v"]"\
"[file normalize "$origin_dir/verilog/sync_short.v"]"\
"[file normalize "$origin_dir/verilog/openofdm_rx.v"]"\
"[file normalize "$origin_dir/verilog/running_sum_dual_ch.v"]"\
"[file normalize "$origin_dir/verilog/signal_watchdog.v"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/deinter_lut/deinter_lut.coe"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/atan_lut/atan_lut.coe"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/rot_lut/rot_lut.coe"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/viterbi/viterbi_v7_0.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/deinter_lut/deinter_lut.xci"]"\
"[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen_div_gen_0_0/div_gen_div_gen_0_0.xci"]"\
"[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen_xlslice_0_0/div_gen_xlslice_0_0.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/xfft/xfft_v9.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/rot_lut/rot_lut.xci"]"\
]
# If you want to make a copy of the file to new src folder, use following command
# set imported_files [import_files -fileset sources_1 $files]
# If you want to keep the files remote, use the following command
# set added_files [add_files -fileset sources_1 $files]
add_files -norecurse -fileset $obj $files
# #Set 'sources_1' fileset file properties for remote files
#set file "$origin_dir/verilog/coregen/div_gen_v3_0.ngc"
#set file [file normalize $file]
#set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
#set_property -name "file_type" -value "NGC" -objects $file_obj
set file "openofdm_rx_s_axi.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "0" -objects $file_obj
set file "openofdm_rx.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "0" -objects $file_obj
set file "running_sum_dual_ch.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "0" -objects $file_obj
set file "signal_watchdog.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "0" -objects $file_obj
# Set 'sources_1' fileset file properties for local files
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "openofdm_rx" -objects $obj
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
create_fileset -constrset constrs_1
}
# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]
# Empty (no sources present)
# Create constraints !
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
# Create runs
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
create_fileset -simset sim_1
}
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
set files [list \
"[file normalize "$origin_dir/verilog/dot11_tb.v"]"
]
add_files -norecurse -fileset $obj $files
# Empty (no sources present)
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "32bit" -value "0" -objects $obj
set_property -name "generic" -value "" -objects $obj
set_property -name "include_dirs" -value "" -objects $obj
set_property -name "incremental" -value "1" -objects $obj
set_property -name "name" -value "sim_1" -objects $obj
set_property -name "nl.cell" -value "" -objects $obj
set_property -name "nl.incl_unisim_models" -value "0" -objects $obj
set_property -name "nl.process_corner" -value "slow" -objects $obj
set_property -name "nl.rename_top" -value "" -objects $obj
set_property -name "nl.sdf_anno" -value "1" -objects $obj
set_property -name "nl.write_all_overrides" -value "0" -objects $obj
set_property -name "source_set" -value "sources_1" -objects $obj
set_property -name "top" -value "dot11_tb" -objects $obj
set_property -name "transport_int_delay" -value "0" -objects $obj
set_property -name "transport_path_delay" -value "0" -objects $obj
set_property -name "verilog_define" -value "" -objects $obj
set_property -name "verilog_uppercase" -value "0" -objects $obj
set_property -name "xelab.dll" -value "0" -objects $obj
set_property -name "xsim.compile.tcl.pre" -value "" -objects $obj
set_property -name "xsim.compile.xvhdl.more_options" -value "" -objects $obj
set_property -name "xsim.compile.xvhdl.nosort" -value "1" -objects $obj
set_property -name "xsim.compile.xvhdl.relax" -value "1" -objects $obj
set_property -name "xsim.compile.xvlog.more_options" -value "" -objects $obj
set_property -name "xsim.compile.xvlog.nosort" -value "1" -objects $obj
set_property -name "xsim.compile.xvlog.relax" -value "1" -objects $obj
set_property -name "xsim.elaborate.debug_level" -value "typical" -objects $obj
set_property -name "xsim.elaborate.load_glbl" -value "1" -objects $obj
set_property -name "xsim.elaborate.mt_level" -value "auto" -objects $obj
set_property -name "xsim.elaborate.rangecheck" -value "0" -objects $obj
set_property -name "xsim.elaborate.relax" -value "1" -objects $obj
set_property -name "xsim.elaborate.sdf_delay" -value "sdfmax" -objects $obj
set_property -name "xsim.elaborate.snapshot" -value "" -objects $obj
set_property -name "xsim.elaborate.xelab.more_options" -value "" -objects $obj
set_property -name "xsim.simulate.custom_tcl" -value "" -objects $obj
set_property -name "xsim.simulate.log_all_signals" -value "0" -objects $obj
set_property -name "xsim.simulate.runtime" -value "1000ns" -objects $obj
set_property -name "xsim.simulate.saif" -value "" -objects $obj
set_property -name "xsim.simulate.saif_all_signals" -value "0" -objects $obj
set_property -name "xsim.simulate.saif_scope" -value "" -objects $obj
set_property -name "xsim.simulate.tcl.post" -value "" -objects $obj
set_property -name "xsim.simulate.wdb" -value "" -objects $obj
set_property -name "xsim.simulate.xsim.more_options" -value "" -objects $obj
# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
} else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Synthesis Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'synth_1_synth_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
}
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.pblocks" -value "" -objects $obj
set_property -name "options.cells" -value "" -objects $obj
set_property -name "options.slr" -value "0" -objects $obj
set_property -name "options.packthru" -value "0" -objects $obj
set_property -name "options.hierarchical" -value "0" -objects $obj
set_property -name "options.hierarchical_depth" -value "" -objects $obj
set_property -name "options.hierarchical_percentages" -value "0" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
set obj [get_runs synth_1]
set_property -name "constrset" -value "constrs_1" -objects $obj
set_property -name "description" -value "Vivado Synthesis Defaults" -objects $obj
set_property -name "flow" -value "Vivado Synthesis 2018" -objects $obj
set_property -name "name" -value "synth_1" -objects $obj
set_property -name "needs_refresh" -value "0" -objects $obj
set_property -name "srcset" -value "sources_1" -objects $obj
# set_property -name "incremental_checkpoint" -value "" -objects $obj
set_property -name "include_in_archive" -value "1" -objects $obj
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
set_property -name "steps.synth_design.tcl.pre" -value "" -objects $obj
set_property -name "steps.synth_design.tcl.post" -value "" -objects $obj
set_property -name "steps.synth_design.args.flatten_hierarchy" -value "rebuilt" -objects $obj
set_property -name "steps.synth_design.args.gated_clock_conversion" -value "off" -objects $obj
set_property -name "steps.synth_design.args.bufg" -value "12" -objects $obj
set_property -name "steps.synth_design.args.fanout_limit" -value "10000" -objects $obj
set_property -name "steps.synth_design.args.directive" -value "Default" -objects $obj
set_property -name "steps.synth_design.args.retiming" -value "0" -objects $obj
set_property -name "steps.synth_design.args.fsm_extraction" -value "auto" -objects $obj
set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "0" -objects $obj
set_property -name "steps.synth_design.args.resource_sharing" -value "auto" -objects $obj
set_property -name "steps.synth_design.args.control_set_opt_threshold" -value "auto" -objects $obj
set_property -name "steps.synth_design.args.no_lc" -value "0" -objects $obj
set_property -name "steps.synth_design.args.no_srlextract" -value "0" -objects $obj
set_property -name "steps.synth_design.args.shreg_min_size" -value "3" -objects $obj
set_property -name "steps.synth_design.args.max_bram" -value "-1" -objects $obj
set_property -name "steps.synth_design.args.max_uram" -value "-1" -objects $obj
set_property -name "steps.synth_design.args.max_dsp" -value "-1" -objects $obj
set_property -name "steps.synth_design.args.max_bram_cascade_height" -value "-1" -objects $obj
set_property -name "steps.synth_design.args.max_uram_cascade_height" -value "-1" -objects $obj
set_property -name "steps.synth_design.args.cascade_dsp" -value "auto" -objects $obj
set_property -name "steps.synth_design.args.assert" -value "0" -objects $obj
set_property -name "steps.synth_design.args.more options" -value "" -objects $obj
# set the current synth run
current_run -synthesis [get_runs synth_1]
# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
} else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2018" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Implementation Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.check_timing_verbose" -value "0" -objects $obj
set_property -name "options.delay_type" -value "" -objects $obj
set_property -name "options.setup" -value "0" -objects $obj
set_property -name "options.hold" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.nworst" -value "" -objects $obj
set_property -name "options.unique_pins" -value "0" -objects $obj
set_property -name "options.path_type" -value "" -objects $obj
set_property -name "options.slack_lesser_than" -value "" -objects $obj
set_property -name "options.report_unconstrained" -value "0" -objects $obj
set_property -name "options.warn_on_violation" -value "0" -objects $obj
set_property -name "options.significant_digits" -value "" -objects $obj
set_property -name "options.cell" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_opt_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.upgrade_cw" -value "0" -objects $obj
set_property -name "options.checks" -value "" -objects $obj
set_property -name "options.ruledecks" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.check_timing_verbose" -value "0" -objects $obj
set_property -name "options.delay_type" -value "" -objects $obj
set_property -name "options.setup" -value "0" -objects $obj
set_property -name "options.hold" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.nworst" -value "" -objects $obj
set_property -name "options.unique_pins" -value "0" -objects $obj
set_property -name "options.path_type" -value "" -objects $obj
set_property -name "options.slack_lesser_than" -value "" -objects $obj
set_property -name "options.report_unconstrained" -value "0" -objects $obj
set_property -name "options.warn_on_violation" -value "0" -objects $obj
set_property -name "options.significant_digits" -value "" -objects $obj
set_property -name "options.cell" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.check_timing_verbose" -value "0" -objects $obj
set_property -name "options.delay_type" -value "" -objects $obj
set_property -name "options.setup" -value "0" -objects $obj
set_property -name "options.hold" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.nworst" -value "" -objects $obj
set_property -name "options.unique_pins" -value "0" -objects $obj
set_property -name "options.path_type" -value "" -objects $obj
set_property -name "options.slack_lesser_than" -value "" -objects $obj
set_property -name "options.report_unconstrained" -value "0" -objects $obj
set_property -name "options.warn_on_violation" -value "0" -objects $obj
set_property -name "options.significant_digits" -value "" -objects $obj
set_property -name "options.cell" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_place_report_io_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_place_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.pblocks" -value "" -objects $obj
set_property -name "options.cells" -value "" -objects $obj
set_property -name "options.slr" -value "0" -objects $obj
set_property -name "options.packthru" -value "0" -objects $obj
set_property -name "options.hierarchical" -value "0" -objects $obj
set_property -name "options.hierarchical_depth" -value "" -objects $obj
set_property -name "options.hierarchical_percentages" -value "0" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_place_report_control_sets_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.verbose" -value "1" -objects $obj
set_property -name "options.cells" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.cells" -value "" -objects $obj
set_property -name "options.hierarchical" -value "0" -objects $obj
set_property -name "options.hierarchical_depth" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.cells" -value "" -objects $obj
set_property -name "options.hierarchical" -value "0" -objects $obj
set_property -name "options.hierarchical_depth" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.check_timing_verbose" -value "0" -objects $obj
set_property -name "options.delay_type" -value "" -objects $obj
set_property -name "options.setup" -value "0" -objects $obj
set_property -name "options.hold" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.nworst" -value "" -objects $obj
set_property -name "options.unique_pins" -value "0" -objects $obj
set_property -name "options.path_type" -value "" -objects $obj
set_property -name "options.slack_lesser_than" -value "" -objects $obj
set_property -name "options.report_unconstrained" -value "0" -objects $obj
set_property -name "options.warn_on_violation" -value "0" -objects $obj
set_property -name "options.significant_digits" -value "" -objects $obj
set_property -name "options.cell" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.check_timing_verbose" -value "0" -objects $obj
set_property -name "options.delay_type" -value "" -objects $obj
set_property -name "options.setup" -value "0" -objects $obj
set_property -name "options.hold" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.nworst" -value "" -objects $obj
set_property -name "options.unique_pins" -value "0" -objects $obj
set_property -name "options.path_type" -value "" -objects $obj
set_property -name "options.slack_lesser_than" -value "" -objects $obj
set_property -name "options.report_unconstrained" -value "0" -objects $obj
set_property -name "options.warn_on_violation" -value "0" -objects $obj
set_property -name "options.significant_digits" -value "" -objects $obj
set_property -name "options.cell" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.check_timing_verbose" -value "0" -objects $obj
set_property -name "options.delay_type" -value "" -objects $obj
set_property -name "options.setup" -value "0" -objects $obj
set_property -name "options.hold" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.nworst" -value "" -objects $obj
set_property -name "options.unique_pins" -value "0" -objects $obj
set_property -name "options.path_type" -value "" -objects $obj
set_property -name "options.slack_lesser_than" -value "" -objects $obj
set_property -name "options.report_unconstrained" -value "0" -objects $obj
set_property -name "options.warn_on_violation" -value "0" -objects $obj
set_property -name "options.significant_digits" -value "" -objects $obj
set_property -name "options.cell" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_route_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.upgrade_cw" -value "0" -objects $obj
set_property -name "options.checks" -value "" -objects $obj
set_property -name "options.ruledecks" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_route_report_methodology_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.checks" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_route_report_power_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.advisory" -value "0" -objects $obj
set_property -name "options.xpe" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_route_report_route_status_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.of_objects" -value "" -objects $obj
set_property -name "options.route_type" -value "" -objects $obj
set_property -name "options.list_all_nets" -value "0" -objects $obj
set_property -name "options.show_all" -value "0" -objects $obj
set_property -name "options.has_routing" -value "0" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.check_timing_verbose" -value "0" -objects $obj
set_property -name "options.delay_type" -value "" -objects $obj
set_property -name "options.setup" -value "0" -objects $obj
set_property -name "options.hold" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.nworst" -value "" -objects $obj
set_property -name "options.unique_pins" -value "0" -objects $obj
set_property -name "options.path_type" -value "" -objects $obj
set_property -name "options.slack_lesser_than" -value "" -objects $obj
set_property -name "options.report_unconstrained" -value "0" -objects $obj
set_property -name "options.warn_on_violation" -value "0" -objects $obj
set_property -name "options.significant_digits" -value "" -objects $obj
set_property -name "options.cell" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.cells" -value "" -objects $obj
set_property -name "options.hierarchical" -value "0" -objects $obj
set_property -name "options.hierarchical_depth" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.write_xdc" -value "0" -objects $obj
set_property -name "options.clock_roots_only" -value "0" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
}
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "1" -objects $obj
set_property -name "options.check_timing_verbose" -value "0" -objects $obj
set_property -name "options.delay_type" -value "" -objects $obj
set_property -name "options.setup" -value "0" -objects $obj
set_property -name "options.hold" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.nworst" -value "" -objects $obj
set_property -name "options.unique_pins" -value "0" -objects $obj
set_property -name "options.path_type" -value "" -objects $obj
set_property -name "options.slack_lesser_than" -value "" -objects $obj
set_property -name "options.report_unconstrained" -value "0" -objects $obj
set_property -name "options.warn_on_violation" -value "1" -objects $obj
set_property -name "options.significant_digits" -value "" -objects $obj
set_property -name "options.cell" -value "" -objects $obj
set_property -name "options.more_options" -value "" -objects $obj
}
set obj [get_runs impl_1]
set_property -name "constrset" -value "constrs_1" -objects $obj
set_property -name "description" -value "Default settings for Implementation." -objects $obj
set_property -name "flow" -value "Vivado Implementation 2018" -objects $obj
set_property -name "name" -value "impl_1" -objects $obj
set_property -name "needs_refresh" -value "0" -objects $obj
set_property -name "pr_configuration" -value "" -objects $obj
set_property -name "srcset" -value "sources_1" -objects $obj
# set_property -name "incremental_checkpoint" -value "" -objects $obj
set_property -name "include_in_archive" -value "1" -objects $obj
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
set_property -name "steps.opt_design.is_enabled" -value "1" -objects $obj
set_property -name "steps.opt_design.tcl.pre" -value "" -objects $obj
set_property -name "steps.opt_design.tcl.post" -value "" -objects $obj
set_property -name "steps.opt_design.args.verbose" -value "0" -objects $obj
set_property -name "steps.opt_design.args.directive" -value "Default" -objects $obj
set_property -name "steps.opt_design.args.more options" -value "" -objects $obj
set_property -name "steps.power_opt_design.is_enabled" -value "0" -objects $obj
set_property -name "steps.power_opt_design.tcl.pre" -value "" -objects $obj
set_property -name "steps.power_opt_design.tcl.post" -value "" -objects $obj
set_property -name "steps.power_opt_design.args.more options" -value "" -objects $obj
set_property -name "steps.place_design.tcl.pre" -value "" -objects $obj
set_property -name "steps.place_design.tcl.post" -value "" -objects $obj
set_property -name "steps.place_design.args.directive" -value "Default" -objects $obj
set_property -name "steps.place_design.args.more options" -value "" -objects $obj
set_property -name "steps.post_place_power_opt_design.is_enabled" -value "0" -objects $obj
set_property -name "steps.post_place_power_opt_design.tcl.pre" -value "" -objects $obj
set_property -name "steps.post_place_power_opt_design.tcl.post" -value "" -objects $obj
set_property -name "steps.post_place_power_opt_design.args.more options" -value "" -objects $obj
set_property -name "steps.phys_opt_design.is_enabled" -value "0" -objects $obj
set_property -name "steps.phys_opt_design.tcl.pre" -value "" -objects $obj
set_property -name "steps.phys_opt_design.tcl.post" -value "" -objects $obj
set_property -name "steps.phys_opt_design.args.directive" -value "Default" -objects $obj
set_property -name "steps.phys_opt_design.args.more options" -value "" -objects $obj
set_property -name "steps.route_design.tcl.pre" -value "" -objects $obj
set_property -name "steps.route_design.tcl.post" -value "" -objects $obj
set_property -name "steps.route_design.args.directive" -value "Default" -objects $obj
set_property -name "steps.route_design.args.more options" -value "" -objects $obj
set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "0" -objects $obj
set_property -name "steps.post_route_phys_opt_design.tcl.pre" -value "" -objects $obj
set_property -name "steps.post_route_phys_opt_design.tcl.post" -value "" -objects $obj
set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Default" -objects $obj
set_property -name "steps.post_route_phys_opt_design.args.more options" -value "" -objects $obj
set_property -name "steps.write_bitstream.tcl.pre" -value "" -objects $obj
set_property -name "steps.write_bitstream.tcl.post" -value "" -objects $obj
set_property -name "steps.write_bitstream.args.raw_bitfile" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.mask_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.no_binary_bitfile" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.bin_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.logic_location_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.more options" -value "" -objects $obj
# set the current impl run
current_run -implementation [get_runs impl_1]
puts "INFO: Project created:$project_name"

52
parse_board_name.tcl Normal file
View File

@ -0,0 +1,52 @@
# // Author: Xianjun Jiao
# // SPDX-FileCopyrightText: 2022 UGent
# // SPDX-License-Identifier: AGPL-3.0-or-later
# fpga_size_flag: 0 small; 1 big
if {$BOARD_NAME=="zed_fmcs2"} {
set ultra_scale_flag 0
set part_string xc7z020clg484-1
set fpga_size_flag 0
} elseif {$BOARD_NAME=="zcu102_fmcs2"} {
set ultra_scale_flag 1
set part_string xczu9eg-ffvb1156-2-e
set fpga_size_flag 1
} elseif {$BOARD_NAME=="zc706_fmcs2"} {
set ultra_scale_flag 0
set part_string xc7z045ffg900-2
set fpga_size_flag 1
} elseif {$BOARD_NAME=="zc702_fmcs2"} {
set ultra_scale_flag 0
set part_string xc7z020clg484-1
set fpga_size_flag 0
} elseif {$BOARD_NAME=="antsdr"} {
set ultra_scale_flag 0
set part_string xc7z020clg400-1
set fpga_size_flag 0
} elseif {$BOARD_NAME=="antsdr_e200"} {
set ultra_scale_flag 0
set part_string xc7z020clg400-1
set fpga_size_flag 0
} elseif {$BOARD_NAME=="sdrpi"} {
set ultra_scale_flag 0
set part_string xc7z020clg400-1
set fpga_size_flag 0
} elseif {$BOARD_NAME=="adrv9361z7035"} {
set ultra_scale_flag 0
set part_string xc7z035ifbg676-2L
set fpga_size_flag 1
} elseif {$BOARD_NAME=="adrv9364z7020"} {
set ultra_scale_flag 0
set part_string xc7z020clg400-1
set fpga_size_flag 0
} elseif {$BOARD_NAME=="neptunesdr"} {
set ultra_scale_flag 0
set part_string xc7z020clg400-1
set fpga_size_flag 0
} else {
set ultra_scale_flag []
set part_string []
set fpga_size_flag []
puts "$BOARD_NAME is not valid!"
}

2
verilog/Xilinx/zynq/deinter_lut/deinter_lut.xci
View File

@ -237,7 +237,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:zc706:part0:1.2</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z045</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>

2
verilog/Xilinx/zynquplus/deinter_lut/deinter_lut.xci
View File

@ -237,7 +237,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplus</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplus</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:zcu102:part0:3.1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu9eg</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu9eg</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvb1156</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvb1156</spirit:configurableElementValue>

24
verilog/common_params.v
View File

@ -56,20 +56,20 @@ localparam E_WRONG_RSVD = 3;
localparam E_WRONG_TAIL = 4; localparam E_WRONG_TAIL = 4;
// erros in HT-SIGNAL // erros in HT-SIGNAL
localparam E_UNSUPPORTED_MCS = 1; localparam E_UNSUPPORTED_MCS = 8;
localparam E_UNSUPPORTED_CBW = 2; localparam E_UNSUPPORTED_CBW = 9;
localparam E_HT_WRONG_RSVD = 3; localparam E_HT_WRONG_RSVD = 10;
localparam E_UNSUPPORTED_STBC = 4; localparam E_UNSUPPORTED_STBC = 11;
localparam E_UNSUPPORTED_FEC = 5; localparam E_UNSUPPORTED_FEC = 12;
localparam E_UNSUPPORTED_SGI = 6; localparam E_UNSUPPORTED_SGI = 13;
localparam E_UNSUPPORTED_SPATIAL = 7; localparam E_UNSUPPORTED_SPATIAL = 14;
localparam E_HT_WRONG_TAIL = 8; localparam E_HT_WRONG_TAIL = 15;
localparam E_HT_AMPDU_WARN = 9; localparam E_HT_AMPDU_WARN = 16;
localparam E_HT_AMPDU_ERROR = 10; localparam E_HT_AMPDU_ERROR = 17;
localparam E_WRONG_CRC = 11; localparam E_WRONG_CRC = 18;
// fcs error // fcs error
localparam E_WRONG_FCS = 1; localparam E_WRONG_FCS = 31;
localparam EXPECTED_FCS = 32'hc704dd7b; localparam EXPECTED_FCS = 32'hc704dd7b;

103
verilog/complex_mult.v
View File

@ -10,69 +10,72 @@ module complex_mult
input [15:0] b_q, input [15:0] b_q,
input input_strobe, input input_strobe,
output reg [31:0] p_i, output [31:0] p_i,
output reg [31:0] p_q, output [31:0] p_q,
output output_strobe output output_strobe
); );
localparam DELAY = 4;
reg [DELAY-1:0] delay;
reg [15:0] ar;
reg [15:0] ai;
reg [15:0] br;
reg [15:0] bi;
wire [31:0] prod_i;
wire [31:0] prod_q;
// instantiation of complex multiplier
wire [31:0] s_axis_a_tdata;
assign s_axis_a_tdata = {ai,ar} ;
wire [31:0] s_axis_b_tdata;
assign s_axis_b_tdata = {bi, br} ;
wire [63:0] m_axis_dout_tdata; wire [63:0] m_axis_dout_tdata;
assign prod_q = m_axis_dout_tdata[63:32]; assign p_q = m_axis_dout_tdata[63:32];
assign prod_i = m_axis_dout_tdata[31:0]; assign p_i = m_axis_dout_tdata[31:0];
wire m_axis_dout_tvalid ; // first try not use it
complex_multiplier mult_inst ( complex_multiplier mult_inst (
.aclk(clock), // input wire aclk .aclk(clock), // input wire aclk
.s_axis_a_tvalid(input_strobe), // input wire s_axis_a_tvalid .s_axis_a_tvalid(input_strobe), // input wire s_axis_a_tvalid
.s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata .s_axis_a_tdata({a_q, a_i}), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid(input_strobe), // input wire s_axis_b_tvalid .s_axis_b_tvalid(input_strobe), // input wire s_axis_b_tvalid
.s_axis_b_tdata(s_axis_b_tdata), // input wire [31 : 0] s_axis_b_tdata .s_axis_b_tdata({b_q, b_i}), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid .m_axis_dout_tvalid(output_strobe), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata .m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata
); );
delayT #(.DATA_WIDTH(1), .DELAY(5)) stb_delay_inst (
.clock(clock),
.reset(reset),
.data_in(input_strobe), // reg [15:0] ar;
.data_out(output_strobe) // reg [15:0] ai;
); // reg [15:0] br;
// reg [15:0] bi;
always @(posedge clock) begin // wire [31:0] prod_i;
if (reset) begin // wire [31:0] prod_q;
ar <= 0;
ai <= 0;
br <= 0;
bi <= 0;
p_i <= 0;
p_q <= 0;
delay <= 0;
end else if (enable) begin
ar <= a_i;
ai <= a_q;
br <= b_i;
bi <= b_q;
p_i <= prod_i; // // instantiation of complex multiplier
p_q <= prod_q; // wire [31:0] s_axis_a_tdata;
end // assign s_axis_a_tdata = {ai,ar} ;
end // wire [31:0] s_axis_b_tdata;
// assign s_axis_b_tdata = {bi, br} ;
// wire [63:0] m_axis_dout_tdata;
// assign prod_q = m_axis_dout_tdata[63:32];
// assign prod_i = m_axis_dout_tdata[31:0];
// wire m_axis_dout_tvalid ;
// assign output_strobe = m_axis_dout_tvalid; //output strobe valid at the beginning of new data -- simulation confirmed
// complex_multiplier mult_inst (
// .aclk(clock), // input wire aclk
// .s_axis_a_tvalid(input_strobe), // input wire s_axis_a_tvalid
// .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata
// .s_axis_b_tvalid(input_strobe), // input wire s_axis_b_tvalid
// .s_axis_b_tdata(s_axis_b_tdata), // input wire [31 : 0] s_axis_b_tdata
// .m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid
// .m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata
// );
// always @(posedge clock) begin
// if (reset) begin
// ar <= 0;
// ai <= 0;
// br <= 0;
// bi <= 0;
// p_i <= 0;
// p_q <= 0;
// end else if (enable) begin
// ar <= a_i;
// ai <= a_q;
// br <= b_i;
// bi <= b_q;
// p_i <= prod_i;
// p_q <= prod_q;
// end
// end
endmodule endmodule

23
verilog/complex_to_mag.v
View File

@ -12,7 +12,7 @@ module complex_to_mag
input input_strobe, input input_strobe,
output reg [DATA_WIDTH-1:0] mag, output reg [DATA_WIDTH-1:0] mag,
output mag_stb output reg mag_stb
); );
reg [DATA_WIDTH-1:0] abs_i; reg [DATA_WIDTH-1:0] abs_i;
@ -21,13 +21,16 @@ reg [DATA_WIDTH-1:0] abs_q;
reg [DATA_WIDTH-1:0] max; reg [DATA_WIDTH-1:0] max;
reg[ DATA_WIDTH-1:0] min; reg[ DATA_WIDTH-1:0] min;
delayT #(.DATA_WIDTH(1), .DELAY(3)) stb_delay_inst ( reg input_strobe_reg0;
.clock(clock), reg input_strobe_reg1;
.reset(reset),
.data_in(input_strobe), // delayT #(.DATA_WIDTH(1), .DELAY(3)) stb_delay_inst (
.data_out(mag_stb) // .clock(clock),
); // .reset(reset),
// .data_in(input_strobe),
// .data_out(mag_stb)
// );
// http://dspguru.com/dsp/tricks/magnitude-estimator // http://dspguru.com/dsp/tricks/magnitude-estimator
@ -40,6 +43,8 @@ always @(posedge clock) begin
abs_q <= 0; abs_q <= 0;
max <= 0; max <= 0;
min <= 0; min <= 0;
input_strobe_reg0 <= 0;
input_strobe_reg1 <= 0;
end else if (enable) begin end else if (enable) begin
abs_i <= i[DATA_WIDTH-1]? (~i+1): i; abs_i <= i[DATA_WIDTH-1]? (~i+1): i;
abs_q <= q[DATA_WIDTH-1]? (~q+1): q; abs_q <= q[DATA_WIDTH-1]? (~q+1): q;
@ -48,6 +53,10 @@ always @(posedge clock) begin
min <= abs_i > abs_q? abs_q: abs_i; min <= abs_i > abs_q? abs_q: abs_i;
mag <= max + (min>>2); mag <= max + (min>>2);
input_strobe_reg0 <= input_strobe;
input_strobe_reg1 <= input_strobe_reg0;
mag_stb <= input_strobe_reg1;
end end
end end

115
verilog/dot11.v
View File

@ -1,9 +1,17 @@
`include "common_defs.v" `include "common_defs.v"
`include "openofdm_rx_pre_def.v"
`ifdef OPENOFDM_RX_ENABLE_DBG
`define DEBUG_PREFIX (*mark_debug="true",DONT_TOUCH="TRUE"*)
`else
`define DEBUG_PREFIX
`endif
module dot11 ( module dot11 (
input clock, input clock,
input enable, input enable,
input reset, input reset,
input reset_without_watchdog,
// setting registers // setting registers
//input set_stb, //input set_stb,
@ -11,17 +19,19 @@ module dot11 (
//input [31:0] set_data, //input [31:0] set_data,
// add ports for register based inputs // add ports for register based inputs
input [10:0] power_thres, input signed [10:0] power_thres,
input [31:0] min_plateau, input [31:0] min_plateau,
input threshold_scale,
// INPUT: RSSI // INPUT: RSSI
input [10:0] rssi_half_db, input signed [10:0] rssi_half_db,
// INPUT: I/Q sample // INPUT: I/Q sample
input [31:0] sample_in, input [31:0] sample_in,
input sample_in_strobe, input sample_in_strobe,
input soft_decoding, input soft_decoding,
input wire force_ht_smoothing, input wire force_ht_smoothing,
input wire disable_all_smoothing, input wire disable_all_smoothing,
input [3:0] fft_win_shift,
// OUTPUT: bytes and FCS status // OUTPUT: bytes and FCS status
output reg demod_is_ongoing, output reg demod_is_ongoing,
@ -46,32 +56,32 @@ module dot11 (
// decode status // decode status
// (* mark_debug = "true", DONT_TOUCH = "TRUE" *) // (* mark_debug = "true", DONT_TOUCH = "TRUE" *)
output reg [4:0] state, `DEBUG_PREFIX output reg [4:0] state,
output reg [3:0] status_code, `DEBUG_PREFIX output reg [4:0] status_code,
output state_changed, `DEBUG_PREFIX output state_changed,
output reg [31:0] state_history, `DEBUG_PREFIX output reg [31:0] state_history,
// power trigger // power trigger
output power_trigger, `DEBUG_PREFIX output power_trigger,
// sync short // sync short
output short_preamble_detected, `DEBUG_PREFIX output short_preamble_detected,
output [15:0] phase_offset, `DEBUG_PREFIX output [15:0] phase_offset,
// sync long // sync long
output [31:0] sync_long_metric, `DEBUG_PREFIX output [31:0] sync_long_metric,
output sync_long_metric_stb, `DEBUG_PREFIX output sync_long_metric_stb,
output long_preamble_detected, `DEBUG_PREFIX output long_preamble_detected,
output [31:0] sync_long_out, `DEBUG_PREFIX output [31:0] sync_long_out,
output sync_long_out_strobe, `DEBUG_PREFIX output sync_long_out_strobe,
output wire signed [31:0] phase_offset_taken, `DEBUG_PREFIX output wire signed [31:0] phase_offset_taken,
output [2:0] sync_long_state, `DEBUG_PREFIX output [2:0] sync_long_state,
// equalizer // equalizer
output [31:0] equalizer_out, `DEBUG_PREFIX output [31:0] equalizer_out,
output equalizer_out_strobe, `DEBUG_PREFIX output equalizer_out_strobe,
output [3:0] equalizer_state, `DEBUG_PREFIX output [3:0] equalizer_state,
output wire ofdm_symbol_eq_out_pulse, `DEBUG_PREFIX output wire ofdm_symbol_eq_out_pulse,
// legacy signal info // legacy signal info
output reg legacy_sig_stb, output reg legacy_sig_stb,
@ -97,6 +107,10 @@ module dot11 (
output [1:0] ht_num_ext, output [1:0] ht_num_ext,
output reg ht_sig_crc_ok, output reg ht_sig_crc_ok,
`DEBUG_PREFIX output [14:0] n_ofdm_sym,//max 20166 = (22+65535*8)/26 (max ht len 65535 in sig, min ndbps 26 for mcs0)
`DEBUG_PREFIX output [9:0] n_bit_in_last_sym,//max ht ndbps 260 (ht mcs7)
`DEBUG_PREFIX output phy_len_valid,
// decoding pipeline // decoding pipeline
output [5:0] demod_out, output [5:0] demod_out,
output [5:0] demod_soft_bits, output [5:0] demod_soft_bits,
@ -119,12 +133,15 @@ module dot11 (
`include "common_params.v" `include "common_params.v"
wire [19:0] n_bit_in_last_sym_tmp;
assign n_bit_in_last_sym = n_bit_in_last_sym_tmp[9:0];
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// extra info output to ease side info and viterbi state monitor // extra info output to ease side info and viterbi state monitor
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
reg [3:0] equalizer_state_reg; `DEBUG_PREFIX reg [3:0] equalizer_state_reg;
assign ofdm_symbol_eq_out_pulse = (equalizer_state==4 && equalizer_state_reg==7); assign ofdm_symbol_eq_out_pulse = (equalizer_state==4 && equalizer_state_reg==8);
always @(posedge clock) begin always @(posedge clock) begin
if (reset==1) begin if (reset==1) begin
@ -206,10 +223,10 @@ phase phase_inst (
); );
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
reg sync_short_reset; reg sync_short_reset;
reg sync_long_reset; reg sync_long_reset;
wire sync_short_enable = state == S_SYNC_SHORT; // wire sync_short_enable = state == S_SYNC_SHORT;
wire sync_short_enable = 1;
reg sync_long_enable; reg sync_long_enable;
wire [15:0] num_ofdm_symbol; wire [15:0] num_ofdm_symbol;
@ -236,7 +253,7 @@ reg [15:0] ofdm_in_i;
reg [15:0] ofdm_in_q; reg [15:0] ofdm_in_q;
reg do_descramble; reg do_descramble;
reg [31:0] num_bits_to_decode; reg [19:0] num_bits_to_decode; //4bits + ht_len: num_bits_to_decode <= (22+(ht_len<<3));
reg short_gi; reg short_gi;
reg [4:0] old_state; reg [4:0] old_state;
@ -254,7 +271,6 @@ assign legacy_sig_parity = signal_bits[17];
assign legacy_sig_tail = signal_bits[23:18]; assign legacy_sig_tail = signal_bits[23:18];
assign legacy_sig_parity_ok = ~^signal_bits[17:0]; assign legacy_sig_parity_ok = ~^signal_bits[17:0];
// HT-SIG information // HT-SIG information
reg [23:0] ht_sig1; reg [23:0] ht_sig1;
reg [23:0] ht_sig2; reg [23:0] ht_sig2;
@ -271,7 +287,6 @@ assign ht_fec_coding = ht_sig2[6];
assign ht_sgi = ht_sig2[7]; assign ht_sgi = ht_sig2[7];
assign ht_num_ext = ht_sig2[9:8]; assign ht_num_ext = ht_sig2[9:8];
wire ht_rsvd = ht_sig2[2]; wire ht_rsvd = ht_sig2[2];
wire [7:0] crc = ht_sig2[17:10]; wire [7:0] crc = ht_sig2[17:10];
wire [5:0] ht_sig_tail = ht_sig2[23:18]; wire [5:0] ht_sig_tail = ht_sig2[23:18];
@ -329,6 +344,8 @@ sync_short sync_short_inst (
.enable(enable & sync_short_enable), .enable(enable & sync_short_enable),
.min_plateau(min_plateau), .min_plateau(min_plateau),
.threshold_scale(threshold_scale),
.sample_in(sample_in), .sample_in(sample_in),
.sample_in_strobe(sample_in_strobe), .sample_in_strobe(sample_in_strobe),
@ -339,6 +356,7 @@ sync_short sync_short_inst (
.phase_out(sync_short_phase_out), .phase_out(sync_short_phase_out),
.phase_out_stb(sync_short_phase_out_stb), .phase_out_stb(sync_short_phase_out_stb),
.demod_is_ongoing(demod_is_ongoing),
.short_preamble_detected(short_preamble_detected), .short_preamble_detected(short_preamble_detected),
.phase_offset(phase_offset) .phase_offset(phase_offset)
); );
@ -352,6 +370,7 @@ sync_long sync_long_inst (
.sample_in_strobe(sample_in_strobe), .sample_in_strobe(sample_in_strobe),
.phase_offset(phase_offset), .phase_offset(phase_offset),
.short_gi(short_gi), .short_gi(short_gi),
.fft_win_shift(fft_win_shift),
.rot_addr(sync_long_rot_addr), .rot_addr(sync_long_rot_addr),
.rot_data(sync_long_rot_data), .rot_data(sync_long_rot_data),
@ -457,6 +476,20 @@ crc32 fcs_inst (
.crc_out(pkt_fcs) .crc_out(pkt_fcs)
); );
phy_len_calculation phy_len_calculation_inst(
.clock(clock),
.reset(reset_without_watchdog | long_preamble_detected),
.enable(),
.state(state),
.old_state(old_state),
.num_bits_to_decode(num_bits_to_decode),
.pkt_rate(pkt_rate),//bit [7] 1 means ht; 0 means non-ht
.n_ofdm_sym(n_ofdm_sym),//max 20166 = (22+65535*8)/26
.n_bit_in_last_sym(n_bit_in_last_sym_tmp),//max ht ndbps 260
.phy_len_valid(phy_len_valid)
);
always @(posedge clock) begin always @(posedge clock) begin
if (reset) begin if (reset) begin
@ -529,6 +562,8 @@ always @(posedge clock) begin
case(state) case(state)
S_WAIT_POWER_TRIGGER: begin S_WAIT_POWER_TRIGGER: begin
sync_short_reset <= 0;
pkt_begin <= 0; pkt_begin <= 0;
pkt_ht <= 0; pkt_ht <= 0;
crc_reset <= 0; crc_reset <= 0;
@ -547,19 +582,17 @@ always @(posedge clock) begin
`ifdef DEBUG_PRINT `ifdef DEBUG_PRINT
$display("Power triggered."); $display("Power triggered.");
`endif `endif
sync_short_reset <= 1; // sync_short_reset <= 1;
state <= S_SYNC_SHORT; state <= S_SYNC_SHORT;
end end
end end
S_SYNC_SHORT: begin S_SYNC_SHORT: begin
if (sync_short_reset) begin
sync_short_reset <= 0;
end
if (~power_trigger) begin if (~power_trigger) begin
// power level drops before finding STS // power level drops before finding STS
state <= S_WAIT_POWER_TRIGGER; state <= S_WAIT_POWER_TRIGGER;
sync_short_reset <= 1;
end end
if (short_preamble_detected) begin if (short_preamble_detected) begin
@ -584,17 +617,19 @@ always @(posedge clock) begin
end end
if (sample_count > 320) begin if (sample_count > 320) begin
state <= S_WAIT_POWER_TRIGGER; state <= S_WAIT_POWER_TRIGGER;
sync_short_reset <= 1;
end end
if (~power_trigger) begin if (~power_trigger) begin
state <= S_WAIT_POWER_TRIGGER; state <= S_WAIT_POWER_TRIGGER;
sync_short_reset <= 1;
end end
if (long_preamble_detected) begin if (long_preamble_detected) begin
demod_is_ongoing <= 1; demod_is_ongoing <= 1;
pkt_rate <= {1'b0, 3'b0, 4'b1011}; pkt_rate <= {1'b0, 3'b0, 4'b1011};
do_descramble <= 0; do_descramble <= 0;
num_bits_to_decode <= 48; num_bits_to_decode <= 24;
ofdm_reset <= 1; ofdm_reset <= 1;
ofdm_enable <= 1; ofdm_enable <= 1;
@ -605,10 +640,12 @@ always @(posedge clock) begin
byte_count <= 0; byte_count <= 0;
byte_count_total <= 0; byte_count_total <= 0;
state <= S_DECODE_SIGNAL; state <= S_DECODE_SIGNAL;
sync_short_reset <= 1;
end end
end end
S_DECODE_SIGNAL: begin S_DECODE_SIGNAL: begin
sync_short_reset <= 0;
ofdm_reset <= 0; ofdm_reset <= 0;
if (equalizer_reset) begin if (equalizer_reset) begin
@ -634,7 +671,7 @@ always @(posedge clock) begin
"tail = %6b", legacy_sig_tail); "tail = %6b", legacy_sig_tail);
`endif `endif
num_bits_to_decode <= (22+(legacy_len<<3))<<1; num_bits_to_decode <= (22+(legacy_len<<3));
pkt_rate <= {1'b0, 3'b0, legacy_rate}; pkt_rate <= {1'b0, 3'b0, legacy_rate};
pkt_len <= legacy_len; pkt_len <= legacy_len;
pkt_len_total <= legacy_len+3; pkt_len_total <= legacy_len+3;
@ -673,7 +710,6 @@ always @(posedge clock) begin
end else begin end else begin
//num_bits_to_decode <= (legacy_len+3)<<4; //num_bits_to_decode <= (legacy_len+3)<<4;
do_descramble <= 1; do_descramble <= 1;
ofdm_reset <= 1;
pkt_header_valid <= 1; pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1; pkt_header_valid_strobe <= 1;
pkt_begin <= 1; pkt_begin <= 1;
@ -691,7 +727,12 @@ always @(posedge clock) begin
S_DETECT_HT: begin S_DETECT_HT: begin
legacy_sig_stb <= 0; legacy_sig_stb <= 0;
ofdm_reset <= 1; ofdm_reset <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
// rotate clockwise by 90 degree
ofdm_in_i <= eq_out_q_delayed;
ofdm_in_q <= ~eq_out_i_delayed+1;
if (equalizer_out_strobe) begin if (equalizer_out_strobe) begin
abs_eq_i <= eq_out_i[15]? ~eq_out_i+1: eq_out_i; abs_eq_i <= eq_out_i[15]? ~eq_out_i+1: eq_out_i;
@ -705,7 +746,7 @@ always @(posedge clock) begin
if (rot_eq_count >= 4) begin if (rot_eq_count >= 4) begin
// HT-SIG detected // HT-SIG detected
num_bits_to_decode <= 96; num_bits_to_decode <= 48;
do_descramble <= 0; do_descramble <= 0;
state <= S_HT_SIGNAL; state <= S_HT_SIGNAL;
end else if (normal_eq_count > 4) begin end else if (normal_eq_count > 4) begin
@ -753,7 +794,7 @@ always @(posedge clock) begin
"tail = %06b", ht_sig_tail); "tail = %06b", ht_sig_tail);
`endif `endif
num_bits_to_decode <= (22+(ht_len<<3))<<1; num_bits_to_decode <= (22+(ht_len<<3));
pkt_rate <= {1'b1, ht_mcs}; pkt_rate <= {1'b1, ht_mcs};
pkt_len_rem <= ht_len; pkt_len_rem <= ht_len;
pkt_len <= ht_len; pkt_len <= ht_len;

2
verilog/dot11_side_ch_tb.v
View File

@ -1,3 +1,5 @@
`include "openofdm_rx_pre_def.v"
`timescale 1ns/1ps `timescale 1ns/1ps
module dot11_side_ch_tb; module dot11_side_ch_tb;

569
verilog/dot11_tb.v
View File

@ -1,8 +1,16 @@
`include "openofdm_rx_pre_def.v"
`timescale 1ns/1ps `timescale 1ns/1ps
module dot11_tb; module dot11_tb;
`include "common_params.v" `include "common_params.v"
`ifdef BETTER_SENSITIVITY
`define THRESHOLD_SCALE 1
`else
`define THRESHOLD_SCALE 0
`endif
reg clock; reg clock;
reg reset; reg reset;
reg enable; reg enable;
@ -12,76 +20,32 @@ reg[31:0] sample_in;
reg sample_in_strobe; reg sample_in_strobe;
reg [15:0] clk_count; reg [15:0] clk_count;
wire [31:0] sync_short_metric;
wire short_preamble_detected;
wire power_trigger;
wire [31:0] sync_long_out;
wire sync_long_out_strobe;
wire [31:0] sync_long_metric;
wire sync_long_metric_stb;
wire long_preamble_detected;
wire [31:0] equalizer_out;
wire equalizer_out_strobe;
wire [5:0] demod_out;
wire [5:0] demod_soft_bits;
wire [3:0] demod_soft_bits_pos;
wire demod_out_strobe;
wire [7:0] deinterleave_erase_out;
wire deinterleave_erase_out_strobe;
wire conv_decoder_out;
wire conv_decoder_out_stb;
wire descramble_out;
wire descramble_out_strobe;
wire [3:0] legacy_rate;
wire legacy_sig_rsvd;
wire [11:0] legacy_len;
wire legacy_sig_parity;
wire [5:0] legacy_sig_tail;
wire legacy_sig_stb;
reg signal_done;
wire [3:0] dot11_state;
wire pkt_header_valid; wire pkt_header_valid;
wire pkt_header_valid_strobe; wire pkt_header_valid_strobe;
wire [7:0] byte_out;
wire byte_out_strobe;
wire [15:0] byte_count_total;
wire [15:0] byte_count;
wire [15:0] pkt_len_total;
wire [15:0] pkt_len; wire [15:0] pkt_len;
// wire [63:0] word_out;
// wire word_out_strobe;
reg set_stb; reg set_stb;
reg [7:0] set_addr; reg [7:0] set_addr;
reg [31:0] set_data; reg [31:0] set_data;
wire fcs_out_strobe, fcs_ok;
wire demod_is_ongoing; wire demod_is_ongoing;
wire receiver_rst; wire receiver_rst;
wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid); wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
integer addr; integer run_out_of_iq_sample;
integer iq_count, iq_count_tmp, end_dl_count;
integer bb_sample_fd; // file descriptors
integer power_trigger_fd; integer sample_file_name_fd;
// integer bb_sample_fd;
// integer power_trigger_fd;
integer short_preamble_detected_fd; integer short_preamble_detected_fd;
integer long_preamble_detected_fd; integer long_preamble_detected_fd;
integer sync_long_metric_fd;
integer sync_long_out_fd; integer sync_long_out_fd;
integer equalizer_out_fd;
integer demod_out_fd; integer demod_out_fd;
integer demod_soft_bits_fd; integer demod_soft_bits_fd;
integer demod_soft_bits_pos_fd; integer demod_soft_bits_pos_fd;
@ -90,66 +54,69 @@ integer conv_out_fd;
integer descramble_out_fd; integer descramble_out_fd;
integer signal_fd; integer signal_fd;
integer ht_sig_fd;
integer byte_out_fd; integer byte_out_fd;
integer fcs_out_fd;
integer status_code_fd;
integer phy_len_fd;
// sync_short
integer mag_sq_fd;
integer mag_sq_avg_fd;
integer prod_fd;
integer prod_avg_fd;
integer phase_in_fd;
integer phase_out_fd;
integer delay_prod_avg_mag_fd;
// sync_long
integer sum_fd;
integer metric_fd;
integer raw_fd;
integer phase_correction_fd;
integer next_phase_correction_fd;
integer fft_in_fd;
// equalizer
integer new_lts_fd;
integer phase_offset_pilot_input_fd;
integer phase_offset_lts_input_fd;
integer phase_offset_pilot_fd;
integer phase_offset_pilot_sum_fd;
integer phase_offset_phase_out_fd;
integer cpe_fd;
integer lvpe_fd;
integer sxy_fd;
integer prev_peg_fd;
integer peg_sym_scale_fd;
integer peg_pilot_scale_fd;
integer rot_in_fd;
integer rot_out_fd;
integer equalizer_prod_fd;
integer equalizer_prod_scaled_fd;
integer equalizer_mag_sq_fd;
integer equalizer_out_fd;
integer file_i, file_q, file_rssi_half_db, iq_sample_file; integer file_i, file_q, file_rssi_half_db, iq_sample_file;
// ONLY allow 100(low FPGA), 200(high FPGA), 240(ultra_scal FPGA) and 400(test)
// do NOT turn on more than one of them
`define CLK_SPEED_100M
//`define CLK_SPEED_200M
//`define CLK_SPEED_240M
//`define CLK_SPEED_400M
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_ht_unsupport_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_ht_sig_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_sig_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_6.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_52mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/dot11n_19.5mbps_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_58.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_65mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/ack-ok-openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/fake-demod-0.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi1_aggr0_len14_pre100_post200_openwifi.txt"
`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi1_aggr0_len1537_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi1_aggr0_len4000_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi0_aggr0_len14_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi0_aggr0_len1537_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi0_aggr0_len4000_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi1_aggr0_len14_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi1_aggr0_len1537_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi1_aggr0_len4000_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi0_aggr0_len14_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi0_aggr0_len1537_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi0_aggr0_len4000_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_54M_len14_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_54M_len1537_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_54M_len4000_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_6M_len14_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_6M_len1537_pre100_post200_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_6M_len4000_pre100_post200_openwifi.txt"
`define NUM_SAMPLE 118560
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/openofdm_tx/PL_100Bytes/54Mbps.txt"
//`define NUM_SAMPLE 2048
initial begin initial begin
$dumpfile("dot11.vcd"); // $dumpfile("dot11.vcd");
$dumpvars; // $dumpvars;
sample_file_name_fd = $fopen("./sample_file_name.txt", "w");
$fwrite(sample_file_name_fd, "%s", `SAMPLE_FILE);
$fflush(sample_file_name_fd);
$fclose(sample_file_name_fd);
run_out_of_iq_sample = 0;
end_dl_count = 0;
clock = 0; clock = 0;
reset = 1; reset = 1;
enable = 0; enable = 0;
signal_done <= 0;
# 20 reset = 0; # 86 reset = 0;
enable = 1; enable = 1;
set_stb = 1; set_stb = 1;
@ -168,16 +135,50 @@ always @(posedge clock) begin
if (file_open_trigger==1) begin if (file_open_trigger==1) begin
iq_sample_file = $fopen(`SAMPLE_FILE, "r"); iq_sample_file = $fopen(`SAMPLE_FILE, "r");
bb_sample_fd = $fopen("./sample_in.txt", "w"); // bb_sample_fd = $fopen("./sample_in.txt", "w");
power_trigger_fd = $fopen("./power_trigger.txt", "w"); // power_trigger_fd = $fopen("./power_trigger.txt", "w");
short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w"); short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w");
sync_long_metric_fd = $fopen("./sync_long_metric.txt", "w");
long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w"); long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
// sync_short
mag_sq_fd = $fopen("./mag_sq.txt", "w");
mag_sq_avg_fd = $fopen("./mag_sq_avg.txt", "w");
prod_fd = $fopen("./prod.txt", "w");
prod_avg_fd = $fopen("./prod_avg.txt", "w");
phase_in_fd = $fopen("./phase_in.txt", "w");
phase_out_fd = $fopen("./phase_out.txt", "w");
delay_prod_avg_mag_fd = $fopen("./delay_prod_avg_mag.txt", "w");
// sync_long
sum_fd = $fopen("./sum.txt", "w");
metric_fd = $fopen("./metric.txt", "w");
raw_fd = $fopen("./raw.txt", "w");
phase_correction_fd = $fopen("./phase_correction.txt", "w");
next_phase_correction_fd = $fopen("./next_phase_correction.txt", "w");
fft_in_fd = $fopen("./fft_in.txt", "w");
sync_long_out_fd = $fopen("./sync_long_out.txt", "w"); sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
// equalizer
new_lts_fd = $fopen("./new_lts.txt", "w");
phase_offset_pilot_input_fd = $fopen("./phase_offset_pilot_input.txt", "w");
phase_offset_lts_input_fd = $fopen("./phase_offset_lts_input.txt", "w");
phase_offset_pilot_fd = $fopen("./phase_offset_pilot.txt", "w");
phase_offset_pilot_sum_fd = $fopen("./phase_offset_pilot_sum.txt", "w");
phase_offset_phase_out_fd = $fopen("./phase_offset_phase_out.txt", "w");
cpe_fd = $fopen("./cpe.txt", "w");
lvpe_fd = $fopen("./lvpe.txt", "w");
sxy_fd = $fopen("./sxy.txt", "w");
prev_peg_fd = $fopen("./prev_peg.txt", "w");
peg_sym_scale_fd = $fopen("./peg_sym_scale.txt", "w");
peg_pilot_scale_fd = $fopen("./peg_pilot_scale.txt", "w");
rot_in_fd = $fopen("./rot_in.txt", "w");
rot_out_fd = $fopen("./rot_out.txt", "w");
equalizer_prod_fd = $fopen("./equalizer_prod.txt", "w");
equalizer_prod_scaled_fd = $fopen("./equalizer_prod_scaled.txt", "w");
equalizer_mag_sq_fd = $fopen("./equalizer_mag_sq.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w"); // ofdm decoder
demod_out_fd = $fopen("./demod_out.txt", "w"); demod_out_fd = $fopen("./demod_out.txt", "w");
demod_soft_bits_fd = $fopen("./demod_soft_bits.txt", "w"); demod_soft_bits_fd = $fopen("./demod_soft_bits.txt", "w");
demod_soft_bits_pos_fd = $fopen("./demod_soft_bits_pos.txt", "w"); demod_soft_bits_pos_fd = $fopen("./demod_soft_bits_pos.txt", "w");
@ -186,8 +187,13 @@ always @(posedge clock) begin
descramble_out_fd = $fopen("./descramble_out.txt", "w"); descramble_out_fd = $fopen("./descramble_out.txt", "w");
signal_fd = $fopen("./signal_out.txt", "w"); signal_fd = $fopen("./signal_out.txt", "w");
ht_sig_fd = $fopen("./ht_sig_out.txt", "w");
byte_out_fd = $fopen("./byte_out.txt", "w"); byte_out_fd = $fopen("./byte_out.txt", "w");
fcs_out_fd = $fopen("./fcs_out.txt", "w");
status_code_fd = $fopen("./status_code.txt","w");
phy_len_fd = $fopen("./phy_len.txt", "w");
end end
end end
@ -208,7 +214,7 @@ always @(posedge clock) begin
sample_in <= 0; sample_in <= 0;
clk_count <= 0; clk_count <= 0;
sample_in_strobe <= 0; sample_in_strobe <= 0;
addr <= 0; iq_count <= 0;
end else if (enable) begin end else if (enable) begin
`ifdef CLK_SPEED_100M `ifdef CLK_SPEED_100M
if (clk_count == 4) begin // for 100M; 100/20 = 5 if (clk_count == 4) begin // for 100M; 100/20 = 5
@ -219,54 +225,92 @@ always @(posedge clock) begin
`elsif CLK_SPEED_400M `elsif CLK_SPEED_400M
if (clk_count == 19) begin // for 200M; 400/20 = 20 if (clk_count == 19) begin // for 200M; 400/20 = 20
`endif `endif
sample_in_strobe <= 1; // sample_in_strobe <= 1;
//$fscanf(iq_sample_file, "%d %d %d", file_i, file_q, file_rssi_half_db); //$fscanf(iq_sample_file, "%d %d %d", file_i, file_q, file_rssi_half_db);
$fscanf(iq_sample_file, "%d %d", file_i, file_q); iq_count_tmp = $fscanf(iq_sample_file, "%d %d", file_i, file_q);
if (iq_count_tmp != 2)
run_out_of_iq_sample = 1;
sample_in[15:0] <= file_q; sample_in[15:0] <= file_q;
sample_in[31:16]<= file_i; sample_in[31:16]<= file_i;
//rssi_half_db <= file_rssi_half_db; //rssi_half_db <= file_rssi_half_db;
rssi_half_db <= 0; rssi_half_db <= 0;
addr <= addr + 1; iq_count <= iq_count + 1;
clk_count <= 0; clk_count <= 0;
end else begin end else begin
sample_in_strobe <= 0; // sample_in_strobe <= 0;
clk_count <= clk_count + 1; clk_count <= clk_count + 1;
end end
if (legacy_sig_stb) begin // for finer sample_in_strobe phase control
if (clk_count == 4) begin
sample_in_strobe <= 1;
end else begin
sample_in_strobe <= 0;
end
if (dot11_inst.legacy_sig_stb) begin
end end
//if (sample_in_strobe && power_trigger) begin //if (sample_in_strobe && power_trigger) begin
if (sample_in_strobe) begin if (sample_in_strobe) begin
$fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0])); // $fwrite(bb_sample_fd, "%d %d %d\n", iq_count, $signed(sample_in[31:16]), $signed(sample_in[15:0]));
$fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger); // $fwrite(power_trigger_fd, "%d %d\n", iq_count, dot11_inst.power_trigger);
$fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected); // $fflush(bb_sample_fd);
// $fflush(power_trigger_fd);
$fwrite(long_preamble_detected_fd, "%d %d\n", $time/2, long_preamble_detected); if ((iq_count % 100) == 0) begin
// $display("%d", iq_count);
$fflush(bb_sample_fd);
$fflush(power_trigger_fd);
$fflush(short_preamble_detected_fd);
$fflush(long_preamble_detected_fd);
if ((addr % 100) == 0) begin
$display("%d", addr);
end end
if (addr == `NUM_SAMPLE) begin if (run_out_of_iq_sample) begin
end_dl_count = end_dl_count+1;
end
if(end_dl_count == 300 ) begin
$fclose(iq_sample_file); $fclose(iq_sample_file);
$fclose(bb_sample_fd); // $fclose(bb_sample_fd);
$fclose(power_trigger_fd); // $fclose(power_trigger_fd);
$fclose(short_preamble_detected_fd); $fclose(short_preamble_detected_fd);
$fclose(sync_long_metric_fd);
$fclose(long_preamble_detected_fd); $fclose(long_preamble_detected_fd);
// close short preamble detection output files
$fclose(mag_sq_fd);
$fclose(mag_sq_avg_fd);
$fclose(prod_fd);
$fclose(prod_avg_fd);
$fclose(phase_in_fd);
$fclose(phase_out_fd);
$fclose(delay_prod_avg_mag_fd);
// close long preamble detection output files
$fclose(sum_fd);
$fclose(metric_fd);
$fclose(raw_fd);
$fclose(phase_correction_fd);
$fclose(next_phase_correction_fd);
$fclose(fft_in_fd);
$fclose(sync_long_out_fd); $fclose(sync_long_out_fd);
// close equalizer output files
$fclose(new_lts_fd);
$fclose(phase_offset_pilot_input_fd);
$fclose(phase_offset_lts_input_fd);
$fclose(phase_offset_pilot_fd);
$fclose(phase_offset_pilot_sum_fd);
$fclose(phase_offset_phase_out_fd);
$fclose(cpe_fd);
$fclose(lvpe_fd);
$fclose(sxy_fd);
$fclose(prev_peg_fd);
$fclose(peg_sym_scale_fd);
$fclose(peg_pilot_scale_fd);
$fclose(rot_in_fd);
$fclose(rot_out_fd);
$fclose(equalizer_prod_fd);
$fclose(equalizer_prod_scaled_fd);
$fclose(equalizer_mag_sq_fd);
$fclose(equalizer_out_fd); $fclose(equalizer_out_fd);
// close ofdm decode files
$fclose(demod_out_fd); $fclose(demod_out_fd);
$fclose(demod_soft_bits_fd); $fclose(demod_soft_bits_fd);
$fclose(demod_soft_bits_pos_fd); $fclose(demod_soft_bits_pos_fd);
@ -275,62 +319,205 @@ always @(posedge clock) begin
$fclose(descramble_out_fd); $fclose(descramble_out_fd);
$fclose(signal_fd); $fclose(signal_fd);
$fclose(ht_sig_fd);
$fclose(byte_out_fd); $fclose(byte_out_fd);
$fclose(fcs_out_fd);
$fclose(status_code_fd);
$fclose(phy_len_fd);
$finish; $finish;
end end
end end
if(dot11_inst.short_preamble_detected && dot11_inst.state == S_SYNC_SHORT) begin
if (sync_long_metric_stb) begin $fwrite(short_preamble_detected_fd, "%d %d\n", iq_count, dot11_inst.sync_short_inst.phase_offset);
$fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric); $fflush(short_preamble_detected_fd);
$fflush(sync_long_metric_fd);
end end
if(dot11_inst.long_preamble_detected) begin
if (sync_long_out_strobe) begin $fwrite(long_preamble_detected_fd, "%d %d\n", iq_count, dot11_inst.sync_long_inst.addr1);
$fwrite(sync_long_out_fd, "%d %d\n", $signed(sync_long_out[31:16]), $signed(sync_long_out[15:0])); $fflush(long_preamble_detected_fd);
$fflush(sync_long_out_fd);
end end
if(dot11_inst.fcs_out_strobe) begin
if (equalizer_out_strobe) begin $fwrite(fcs_out_fd, "%d %d\n", iq_count, dot11_inst.fcs_ok);
$fwrite(equalizer_out_fd, "%d %d\n", $signed(equalizer_out[31:16]), $signed(equalizer_out[15:0])); $fflush(fcs_out_fd);
$fflush(equalizer_out_fd);
end end
if(dot11_inst.fcs_out_strobe && dot11_inst.phy_len_valid) begin
if (legacy_sig_stb) begin $fwrite(phy_len_fd, "%d %d %d\n", iq_count, dot11_inst.n_ofdm_sym, dot11_inst.n_bit_in_last_sym);
signal_done <= 1; $fflush(phy_len_fd);
$fwrite(signal_fd, "%04b %b %012b %b %06b", legacy_rate, legacy_sig_rsvd, legacy_len, legacy_sig_parity, legacy_sig_tail); end
if(dot11_inst.state == S_HT_SIG_ERROR || dot11_inst.state == S_SIGNAL_ERROR) begin
$fwrite(status_code_fd, "%d %d %d\n", iq_count, dot11_inst.status_code, dot11_inst.state);
$fflush(status_code_fd);
end
if (dot11_inst.state == S_CHECK_SIGNAL) begin
$fwrite(signal_fd, "%d %d\n", iq_count, dot11_inst.signal_bits);
$fflush(signal_fd); $fflush(signal_fd);
end end
if (dot11_inst.ht_sig_stb) begin
$fwrite(ht_sig_fd, "%d %d %d\n", iq_count, dot11_inst.ht_sig1, dot11_inst.ht_sig2);
$fflush(ht_sig_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && demod_out_strobe) begin if ((dot11_inst.state == S_MPDU_DELIM || dot11_inst.state == S_DECODE_DATA || dot11_inst.state == S_MPDU_PAD) && dot11_inst.ofdm_decoder_inst.demod_out_strobe) begin
$fwrite(demod_out_fd, "%b %b %b %b %b %b\n",demod_out[0],demod_out[1],demod_out[2],demod_out[3],demod_out[4],demod_out[5]); $fwrite(demod_out_fd, "%d %b %b %b %b %b %b\n",iq_count, dot11_inst.ofdm_decoder_inst.demod_out[0],dot11_inst.ofdm_decoder_inst.demod_out[1],dot11_inst.ofdm_decoder_inst.demod_out[2],dot11_inst.ofdm_decoder_inst.demod_out[3],dot11_inst.ofdm_decoder_inst.demod_out[4],dot11_inst.ofdm_decoder_inst.demod_out[5]);
$fwrite(demod_soft_bits_fd, "%b %b %b %b %b %b\n",demod_soft_bits[0],demod_soft_bits[1],demod_soft_bits[2],demod_soft_bits[3],demod_soft_bits[4],demod_soft_bits[5]); $fwrite(demod_soft_bits_fd, "%d %b %b %b %b %b %b\n",iq_count, dot11_inst.ofdm_decoder_inst.demod_soft_bits[0],dot11_inst.ofdm_decoder_inst.demod_soft_bits[1],dot11_inst.ofdm_decoder_inst.demod_soft_bits[2],dot11_inst.ofdm_decoder_inst.demod_soft_bits[3],dot11_inst.ofdm_decoder_inst.demod_soft_bits[4],dot11_inst.ofdm_decoder_inst.demod_soft_bits[5]);
$fwrite(demod_soft_bits_pos_fd, "%b %b %b %b\n",demod_soft_bits_pos[0],demod_soft_bits_pos[1],demod_soft_bits_pos[2],demod_soft_bits_pos[3]); $fwrite(demod_soft_bits_pos_fd, "%d %b %b %b %b\n",iq_count, dot11_inst.ofdm_decoder_inst.demod_soft_bits_pos[0],dot11_inst.ofdm_decoder_inst.demod_soft_bits_pos[1],dot11_inst.ofdm_decoder_inst.demod_soft_bits_pos[2],dot11_inst.ofdm_decoder_inst.demod_soft_bits_pos[3]);
$fflush(demod_out_fd); $fflush(demod_out_fd);
$fflush(demod_soft_bits_fd); $fflush(demod_soft_bits_fd);
$fflush(demod_soft_bits_pos_fd); $fflush(demod_soft_bits_pos_fd);
end end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && deinterleave_erase_out_strobe) begin if ((dot11_inst.state == S_MPDU_DELIM || dot11_inst.state == S_DECODE_DATA || dot11_inst.state == S_MPDU_PAD) && dot11_inst.deinterleave_erase_out_strobe) begin
$fwrite(deinterleave_erase_out_fd, "%b %b %b %b %b %b %b %b\n", deinterleave_erase_out[0], deinterleave_erase_out[1], deinterleave_erase_out[2], deinterleave_erase_out[3], deinterleave_erase_out[4], deinterleave_erase_out[5], deinterleave_erase_out[6], deinterleave_erase_out[7]); $fwrite(deinterleave_erase_out_fd, "%d %b %b %b %b %b %b %b %b\n", iq_count, dot11_inst.deinterleave_erase_out[0], dot11_inst.deinterleave_erase_out[1], dot11_inst.deinterleave_erase_out[2], dot11_inst.deinterleave_erase_out[3], dot11_inst.deinterleave_erase_out[4], dot11_inst.deinterleave_erase_out[5], dot11_inst.deinterleave_erase_out[6], dot11_inst.deinterleave_erase_out[7]);
$fflush(deinterleave_erase_out_fd); $fflush(deinterleave_erase_out_fd);
end end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && conv_decoder_out_stb) begin if ((dot11_inst.state == S_MPDU_DELIM || dot11_inst.state == S_DECODE_DATA || dot11_inst.state == S_MPDU_PAD) && dot11_inst.conv_decoder_out_stb && dot11_inst.ofdm_decoder_inst.reset==0) begin
$fwrite(conv_out_fd, "%b\n", conv_decoder_out); $fwrite(conv_out_fd, "%d %b\n", iq_count, dot11_inst.conv_decoder_out);
$fflush(conv_out_fd); $fflush(conv_out_fd);
end end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && descramble_out_strobe) begin if ((dot11_inst.state == S_MPDU_DELIM || dot11_inst.state == S_DECODE_DATA || dot11_inst.state == S_MPDU_PAD) && dot11_inst.descramble_out_strobe) begin
$fwrite(descramble_out_fd, "%b\n", descramble_out); $fwrite(descramble_out_fd, "%d %b\n", iq_count, dot11_inst.descramble_out);
$fflush(descramble_out_fd); $fflush(descramble_out_fd);
end end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && byte_out_strobe) begin if ((dot11_inst.state == S_MPDU_DELIM || dot11_inst.state == S_DECODE_DATA || dot11_inst.state == S_MPDU_PAD) && dot11_inst.byte_out_strobe) begin
$fwrite(byte_out_fd, "%02x\n", byte_out); $fwrite(byte_out_fd, "%d %02x\n", iq_count, dot11_inst.byte_out);
$fflush(byte_out_fd); $fflush(byte_out_fd);
end end
// sync_short
if (dot11_inst.sync_short_inst.mag_sq_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset && dot11_inst.state == S_SYNC_SHORT) begin
//if (dot11_inst.sync_short_inst.mag_sq_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(mag_sq_fd, "%d %d\n", iq_count, dot11_inst.sync_short_inst.mag_sq);
$fflush(mag_sq_fd);
end
if (dot11_inst.sync_short_inst.mag_sq_avg_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset && dot11_inst.state == S_SYNC_SHORT) begin
//if (dot11_inst.sync_short_inst.mag_sq_avg_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(mag_sq_avg_fd, "%d %d\n", iq_count, dot11_inst.sync_short_inst.mag_sq_avg);
$fflush(mag_sq_avg_fd);
end
if (dot11_inst.sync_short_inst.prod_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset && dot11_inst.state == S_SYNC_SHORT) begin
//if (dot11_inst.sync_short_inst.prod_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(prod_fd, "%d %d %d\n", iq_count, $signed(dot11_inst.sync_short_inst.prod[63:32]), $signed(dot11_inst.sync_short_inst.prod[31:0]));
$fflush(prod_fd);
end
if (dot11_inst.sync_short_inst.prod_avg_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset && dot11_inst.state == S_SYNC_SHORT) begin
//if (dot11_inst.sync_short_inst.prod_avg_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(prod_avg_fd, "%d %d %d\n", iq_count, $signed(dot11_inst.sync_short_inst.prod_avg[63:32]), $signed(dot11_inst.sync_short_inst.prod_avg[31:0]));
$fflush(prod_avg_fd);
end
if (dot11_inst.sync_short_inst.phase_in_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset && dot11_inst.state == S_SYNC_SHORT) begin
//if (dot11_inst.sync_short_inst.phase_in_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(phase_in_fd, "%d %d %d\n", iq_count, $signed(dot11_inst.sync_short_inst.phase_in_i), $signed(dot11_inst.sync_short_inst.phase_in_q));
$fflush(phase_in_fd);
end
if (dot11_inst.sync_short_inst.phase_out_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset && dot11_inst.state == S_SYNC_SHORT) begin
//if (dot11_inst.sync_short_inst.phase_out_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(phase_out_fd, "%d %d\n", iq_count, $signed(dot11_inst.sync_short_inst.phase_out));
$fflush(phase_out_fd);
end
if (dot11_inst.sync_short_inst.delay_prod_avg_mag_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset && dot11_inst.state == S_SYNC_SHORT) begin
//if (dot11_inst.sync_short_inst.delay_prod_avg_mag_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(delay_prod_avg_mag_fd, "%d %d\n", iq_count, dot11_inst.sync_short_inst.delay_prod_avg_mag);
$fflush(delay_prod_avg_mag_fd);
end
// sync_long
if (dot11_inst.sync_long_inst.sum_stb && dot11_inst.sync_long_inst.enable && ~dot11_inst.sync_long_inst.reset) begin
$fwrite(sum_fd, "%d %d %d\n", iq_count, dot11_inst.sync_long_inst.sum_i, dot11_inst.sync_long_inst.sum_q);
$fflush(sum_fd);
end
if (dot11_inst.sync_long_inst.metric_stb && dot11_inst.sync_long_inst.enable && ~dot11_inst.sync_long_inst.reset) begin
$fwrite(metric_fd, "%d %d\n", iq_count, dot11_inst.sync_long_inst.metric);
$fflush(metric_fd);
end
if (dot11_inst.sync_long_inst.raw_stb && dot11_inst.sync_long_inst.enable && ~dot11_inst.sync_long_inst.reset && dot11_inst.sync_long_inst.state == dot11_inst.sync_long_inst.S_FFT) begin
$fwrite(raw_fd, "%d %d %d\n", iq_count, dot11_inst.sync_long_inst.raw_i, dot11_inst.sync_long_inst.raw_q);
$fflush(raw_fd);
$fwrite(phase_correction_fd, "%d %d\n", iq_count, dot11_inst.sync_long_inst.phase_correction);
$fflush(phase_correction_fd);
$fwrite(next_phase_correction_fd, "%d %d\n", iq_count, dot11_inst.sync_long_inst.next_phase_correction);
$fflush(next_phase_correction_fd);
end
if (dot11_inst.sync_long_inst.fft_in_stb && dot11_inst.sync_long_inst.enable && ~dot11_inst.sync_long_inst.reset && dot11_inst.demod_is_ongoing) begin//add demod_is_ongoing to prevent the garbage fft in after decoding is done overlap with the early sync_short of next packet
$fwrite(fft_in_fd, "%d %d %d\n", iq_count, dot11_inst.sync_long_inst.fft_in_re, dot11_inst.sync_long_inst.fft_in_im);
$fflush(fft_in_fd);
end
if (dot11_inst.sync_long_inst.sample_out_strobe) begin
$fwrite(sync_long_out_fd, "%d %d %d\n",iq_count, $signed(dot11_inst.sync_long_inst.sample_out[31:16]), $signed(dot11_inst.sync_long_inst.sample_out[15:0]));
$fflush(sync_long_out_fd);
end
// equalizer
if ((dot11_inst.equalizer_inst.num_ofdm_sym == 1 || (dot11_inst.equalizer_inst.pkt_ht==1 && dot11_inst.equalizer_inst.num_ofdm_sym==5)) && dot11_inst.equalizer_inst.state == dot11_inst.equalizer_inst.S_CPE_ESTIMATE && dot11_inst.equalizer_inst.sample_in_strobe_dly == 1 && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
$fwrite(new_lts_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.lts_i_out, dot11_inst.equalizer_inst.lts_q_out);
$fflush(new_lts_fd);
end
if (dot11_inst.equalizer_inst.pilot_in_stb && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_CPE_ESTIMATE && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(phase_offset_pilot_input_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.input_i, dot11_inst.equalizer_inst.input_q);
$fflush(phase_offset_pilot_input_fd);
$fwrite(phase_offset_lts_input_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.lts_i_out, dot11_inst.equalizer_inst.lts_q_out);
$fflush(phase_offset_lts_input_fd);
end
if (dot11_inst.equalizer_inst.pilot_out_stb && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_CPE_ESTIMATE && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(phase_offset_pilot_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.pilot_i, dot11_inst.equalizer_inst.pilot_q);
$fflush(phase_offset_pilot_fd);
end
if (dot11_inst.equalizer_inst.phase_in_stb && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_PILOT_PE_CORRECTION && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(phase_offset_pilot_sum_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.pilot_sum_i, dot11_inst.equalizer_inst.pilot_sum_q);
$fflush(phase_offset_pilot_sum_fd);
end
if (dot11_inst.equalizer_inst.phase_out_stb && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_PILOT_PE_CORRECTION && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(phase_offset_phase_out_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.phase_out));
$fflush(phase_offset_phase_out_fd);
end
if (dot11_inst.equalizer_inst.lvpe_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(cpe_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.cpe));
$fflush(cpe_fd);
end
if (dot11_inst.equalizer_inst.lvpe_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(lvpe_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.lvpe));
$fflush(lvpe_fd);
end
if (dot11_inst.equalizer_inst.lvpe_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(sxy_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.Sxy));
$fflush(sxy_fd);
end
if (dot11_inst.equalizer_inst.num_output == dot11_inst.equalizer_inst.num_data_carrier && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_ALL_SC_PE_CORRECTION && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(prev_peg_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.prev_peg_reg));
$fflush(prev_peg_fd);
end
if (dot11_inst.equalizer_inst.lvpe_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(peg_sym_scale_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.peg_sym_scale));
$fflush(peg_sym_scale_fd);
end
if (dot11_inst.equalizer_inst.pilot_count1 < 4 && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_PILOT_PE_CORRECTION && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(peg_pilot_scale_fd, "%d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.peg_pilot_scale));
$fflush(peg_pilot_scale_fd);
end
if (dot11_inst.equalizer_inst.rot_in_stb && dot11_inst.equalizer_inst.enable && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_ALL_SC_PE_CORRECTION && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(rot_in_fd, "%d %d %d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.buf_i_out), $signed(dot11_inst.equalizer_inst.buf_q_out), $signed(dot11_inst.equalizer_inst.sym_phase));
$fflush(rot_in_fd);
end
if (dot11_inst.equalizer_inst.rot_out_stb && dot11_inst.equalizer_inst.state==dot11_inst.equalizer_inst.S_ALL_SC_PE_CORRECTION && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
// when enable is 0, it locked equalizer all internal variables till the next reset/enable, some large delayed signal, such as rot out, logged with some garbage
// limite the log to dot11_inst.equalizer_inst.S_ALL_SC_PE_CORRECTION state
$fwrite(rot_out_fd, "%d %d %d\n", iq_count, dot11_inst.equalizer_inst.rot_i, dot11_inst.equalizer_inst.rot_q);
$fflush(rot_out_fd);
end
if (dot11_inst.equalizer_inst.prod_out_strobe && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(equalizer_prod_fd, "%d %d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.prod_i), $signed(dot11_inst.equalizer_inst.prod_q));
$fflush(equalizer_prod_fd);
$fwrite(equalizer_prod_scaled_fd, "%d %d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.prod_i_scaled), $signed(dot11_inst.equalizer_inst.prod_q_scaled));
$fflush(equalizer_prod_scaled_fd);
$fwrite(equalizer_mag_sq_fd, "%d %d\n", iq_count, dot11_inst.equalizer_inst.mag_sq);
$fflush(equalizer_mag_sq_fd);
end
if (dot11_inst.equalizer_inst.sample_out_strobe && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset && dot11_inst.demod_is_ongoing) begin
$fwrite(equalizer_out_fd, "%d %d %d\n", iq_count, $signed(dot11_inst.equalizer_inst.sample_out[31:16]), $signed(dot11_inst.equalizer_inst.sample_out[15:0]));
$fflush(equalizer_out_fd);
end
end end
end end
@ -346,8 +533,9 @@ signal_watchdog signal_watchdog_inst (
.signal_len(pkt_len), .signal_len(pkt_len),
.sig_valid(sig_valid), .sig_valid(sig_valid),
.max_signal_len_th(4095), .min_signal_len_th(0),
.dc_running_sum_th(64), .max_signal_len_th(16'hFFFF),
.dc_running_sum_th(65),
.receiver_rst(receiver_rst) .receiver_rst(receiver_rst)
); );
@ -355,7 +543,7 @@ signal_watchdog signal_watchdog_inst (
dot11 dot11_inst ( dot11 dot11_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
.reset(reset|receiver_rst), .reset(reset | receiver_rst),
//.set_stb(set_stb), //.set_stb(set_stb),
//.set_addr(set_addr), //.set_addr(set_addr),
@ -363,59 +551,20 @@ dot11 dot11_inst (
.power_thres(11'd0), .power_thres(11'd0),
.min_plateau(32'd100), .min_plateau(32'd100),
.threshold_scale(`THRESHOLD_SCALE),
.rssi_half_db(rssi_half_db), .rssi_half_db(rssi_half_db),
.sample_in(sample_in), .sample_in(sample_in),
.sample_in_strobe(sample_in_strobe), .sample_in_strobe(sample_in_strobe),
.soft_decoding(1'b1), .soft_decoding(1'b1),
.force_ht_smoothing(1'b0),
.disable_all_smoothing(1'b0),
.fft_win_shift(4'b1),
.demod_is_ongoing(demod_is_ongoing), .demod_is_ongoing(demod_is_ongoing),
.pkt_header_valid(pkt_header_valid), .pkt_header_valid(pkt_header_valid),
.pkt_header_valid_strobe(pkt_header_valid_strobe), .pkt_header_valid_strobe(pkt_header_valid_strobe),
.pkt_len(pkt_len), .pkt_len(pkt_len)
.pkt_len_total(pkt_len_total),
.byte_out_strobe(byte_out_strobe),
.byte_out(byte_out),
.byte_count_total(byte_count_total),
.byte_count(byte_count),
.fcs_out_strobe(fcs_out_strobe),
.fcs_ok(fcs_ok),
.state(dot11_state),
.power_trigger(power_trigger),
.short_preamble_detected(short_preamble_detected),
.sync_long_metric(sync_long_metric),
.sync_long_metric_stb(sync_long_metric_stb),
.long_preamble_detected(long_preamble_detected),
.sync_long_out(sync_long_out),
.sync_long_out_strobe(sync_long_out_strobe),
.equalizer_out(equalizer_out),
.equalizer_out_strobe(equalizer_out_strobe),
.legacy_sig_stb(legacy_sig_stb),
.legacy_rate(legacy_rate),
.legacy_sig_rsvd(legacy_sig_rsvd),
.legacy_len(legacy_len),
.legacy_sig_parity(legacy_sig_parity),
.legacy_sig_tail(legacy_sig_tail),
.demod_out(demod_out),
.demod_soft_bits(demod_soft_bits),
.demod_soft_bits_pos(demod_soft_bits_pos),
.demod_out_strobe(demod_out_strobe),
.deinterleave_erase_out(deinterleave_erase_out),
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
.conv_decoder_out(conv_decoder_out),
.conv_decoder_out_stb(conv_decoder_out_stb),
.descramble_out(descramble_out),
.descramble_out_strobe(descramble_out_strobe)
); );
/* /*

302
verilog/equalizer.v
View File

@ -69,6 +69,9 @@ localparam HT_POLARITY = 4'b1000;
localparam IN_BUF_LEN_SHIFT = 6; localparam IN_BUF_LEN_SHIFT = 6;
reg enable_delay;
wire reset_internal = (enable==0 && enable_delay==1);//reset internal after the module is disabled in case the disable lock the state/stb to a non-end state.
reg ht; reg ht;
reg [5:0] num_data_carrier; reg [5:0] num_data_carrier;
reg [7:0] num_ofdm_sym; reg [7:0] num_ofdm_sym;
@ -79,11 +82,31 @@ reg [63:0] ht_lts_ref;
reg [63:0] subcarrier_mask; reg [63:0] subcarrier_mask;
reg [63:0] data_subcarrier_mask; reg [63:0] data_subcarrier_mask;
reg [63:0] pilot_mask; reg [63:0] pilot_mask;
reg [5:0] pilot_loc[3:0];
reg signed [5:0] pilot_idx[3:0];
localparam pilot_loc1 = 7;
localparam pilot_loc2 = 21;
localparam pilot_loc3 = 43;
localparam pilot_loc4 = 57;
localparam signed pilot_idx1 = 8;
localparam signed pilot_idx2 = 22;
localparam signed pilot_idx3 = -20;
localparam signed pilot_idx4 = -6;
initial begin
pilot_loc[0] = pilot_loc1;
pilot_idx[0] = pilot_idx1;
pilot_loc[1] = pilot_loc2;
pilot_idx[1] = pilot_idx2;
pilot_loc[2] = pilot_loc3;
pilot_idx[2] = pilot_idx3;
pilot_loc[3] = pilot_loc4;
pilot_idx[3] = pilot_idx4;
end
reg [126:0] polarity; reg [126:0] polarity;
reg [3:0] ht_polarity; reg [3:0] ht_polarity;
reg [3:0] current_polarity; reg [3:0] current_polarity;
reg [3:0] pilot_count1, pilot_count2; reg [3:0] pilot_count1, pilot_count2, pilot_count3;
reg signed [15:0] input_i; reg signed [15:0] input_i;
reg signed [15:0] input_q; reg signed [15:0] input_q;
@ -122,24 +145,29 @@ reg signed [31:0] pilot_sum_q;
assign phase_in_i = pilot_i_reg; assign phase_in_i = pilot_i_reg;
assign phase_in_q = pilot_q_reg; assign phase_in_q = pilot_q_reg;
reg signed [15:0] pilot_phase_err; //reg signed [15:0] pilot_phase_err;
reg signed [16:0] pilot_phase_err; // 15 --> 16 = 15 + 1, extended from cpe
reg signed [15:0] cpe; // common phase error due to RFO reg signed [15:0] cpe; // common phase error due to RFO
reg signed [15:0] Sxy; //reg signed [15:0] Sxy;
reg signed [23:0] Sxy; // 15-->23. to avoid overflow: pilot_phase_err 16 + 5 + 2. 5 for 21* (rounding to 32); 2 for 4 pilots
localparam Sx2 = 980; localparam Sx2 = 980;
// linear varying phase error (LVPE) parameters // linear varying phase error (LVPE) parameters
reg signed [7:0] sym_idx; reg signed [7:0] sym_idx, sym_idx2;
reg lvpe_in_stb; reg lvpe_in_stb;
wire lvpe_out_stb; wire lvpe_out_stb;
wire signed [31:0] lvpe_dividend, lvpe; wire signed [31:0] lvpe_dividend, lvpe, peg_sym_scale;
wire signed [23:0] lvpe_divisor; wire signed [23:0] lvpe_divisor;
assign lvpe_dividend = (sym_idx <= 33 ? sym_idx*Sxy : (sym_idx-64)*Sxy); assign lvpe_dividend = (sym_idx <= 33 ? sym_idx*Sxy : (sym_idx-64)*Sxy);
assign lvpe_divisor = Sx2; assign lvpe_divisor = Sx2;
reg signed [31:0] prev_peg, prev_peg_reg, peg_pilot_scale;
assign peg_sym_scale = (sym_idx2 <= 33 ? sym_idx2*prev_peg : (sym_idx2-64)*prev_peg);
//reg signed [15:0] phase_err;
reg signed [15:0] phase_err; reg signed [17:0] phase_err; // 15-->16: phase_err <= cpe + lvpe[17:0]; 16 + 1 = 17 for sym_phase
wire signed [15:0] sym_phase; //wire signed [15:0] sym_phase;
assign sym_phase = (phase_err > 1608) ? (phase_err - 3217) : ((phase_err < -1608) ? (phase_err + 3217) : phase_err); wire signed [17:0] sym_phase;// phase_err 16 + 1
assign sym_phase = (phase_err > 1608) ? (phase_err - 3217) : ((phase_err < -1608) ? (phase_err + 3217) : phase_err);//only taking [15:0] to rotate could have overflow!
reg rot_in_stb; reg rot_in_stb;
wire signed [15:0] rot_i; wire signed [15:0] rot_i;
@ -172,11 +200,11 @@ reg signed [18:0] lts_sum_q;
reg [2:0] lts_mv_avg_len; reg [2:0] lts_mv_avg_len;
reg lts_div_in_stb; reg lts_div_in_stb;
wire [31:0] dividend_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_i[18] == 0 ? {13'h0,lts_sum_i} : {13'h1FFF,lts_sum_i}) : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? prod_i_scaled : 0); wire [31:0] dividend_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_i[18] == 0 ? {13'h0,lts_sum_i} : {13'h1FFF,lts_sum_i}) : (state == S_ALL_SC_PE_CORRECTION ? prod_i_scaled : 0);
wire [31:0] dividend_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_q[18] == 0 ? {13'h0,lts_sum_q} : {13'h1FFF,lts_sum_q}) : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? prod_q_scaled : 0); wire [31:0] dividend_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_q[18] == 0 ? {13'h0,lts_sum_q} : {13'h1FFF,lts_sum_q}) : (state == S_ALL_SC_PE_CORRECTION ? prod_q_scaled : 0);
wire [23:0] divisor_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? mag_sq[23:0] : 1); wire [23:0] divisor_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ALL_SC_PE_CORRECTION ? mag_sq[23:0] : 1);
wire [23:0] divisor_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? mag_sq[23:0] : 1); wire [23:0] divisor_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ALL_SC_PE_CORRECTION ? mag_sq[23:0] : 1);
wire div_in_stb = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? lts_div_in_stb : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? prod_out_strobe : 0); wire div_in_stb = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? lts_div_in_stb : (state == S_ALL_SC_PE_CORRECTION ? prod_out_strobe : 0);
reg [15:0] num_output; reg [15:0] num_output;
@ -197,89 +225,15 @@ wire prod_out_strobe;
// for side channel // for side channel
reg sample_in_strobe_dly; reg sample_in_strobe_dly;
assign csi = {lts_i_out, lts_q_out}; assign csi = {lts_i_out, lts_q_out};
assign csi_valid = ( (num_ofdm_sym == 1 || (pkt_ht==1 && num_ofdm_sym==5)) && state == S_CALC_FREQ_OFFSET && sample_in_strobe_dly == 1 && enable && (~reset) ); assign csi_valid = ( (num_ofdm_sym == 1 || (pkt_ht==1 && num_ofdm_sym==5)) && state == S_CPE_ESTIMATE && sample_in_strobe_dly == 1 && enable && (~reset) );
/*
// =============save signal to file for matlab bit-true comparison===========
integer file_open_trigger = 0;
integer new_lts_fd, phase_offset_pilot_input_fd, phase_offset_lts_input_fd, phase_offset_pilot_fd, phase_offset_pilot_sum_fd, phase_offset_phase_out_fd, rot_out_fd, equalizer_prod_fd, equalizer_prod_scaled_fd, equalizer_mag_sq_fd, equalizer_out_fd;
wire signed [15:0] norm_i_signed, norm_q_signed;
assign norm_i_signed = sample_out[31:16];
assign norm_q_signed = sample_out[15:0];
wire signed [31:0] prod_i_signed, prod_q_signed, prod_i_scaled_signed, prod_q_scaled_signed;
wire signed [15:0] phase_out_signed;
assign prod_i_signed = prod_i;
assign prod_q_signed = prod_q;
assign prod_i_scaled_signed = prod_i_scaled;
assign prod_q_scaled_signed = prod_q_scaled;
assign phase_out_signed = phase_out;
always @(posedge clock) begin always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1; if (reset) begin
if (file_open_trigger==1) begin enable_delay <= 0;
new_lts_fd = $fopen("./new_lts.txt", "w"); end else begin
phase_offset_pilot_input_fd = $fopen("./phase_offset_pilot_input.txt", "w"); enable_delay <= enable;
phase_offset_lts_input_fd = $fopen("./phase_offset_lts_input.txt", "w");
phase_offset_pilot_fd = $fopen("./phase_offset_pilot.txt", "w");
phase_offset_pilot_sum_fd = $fopen("./phase_offset_pilot_sum.txt", "w");
phase_offset_phase_out_fd = $fopen("./phase_offset_phase_out.txt", "w");
rot_out_fd = $fopen("./rot_out.txt", "w");
equalizer_prod_fd = $fopen("./equalizer_prod.txt", "w");
equalizer_prod_scaled_fd = $fopen("./equalizer_prod_scaled.txt", "w");
equalizer_mag_sq_fd = $fopen("./equalizer_mag_sq.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
end
if ((num_ofdm_sym == 1 || (pkt_ht==1 && num_ofdm_sym==5)) && state == S_CALC_FREQ_OFFSET && sample_in_strobe_dly == 1 && enable && (~reset) ) begin
$fwrite(new_lts_fd, "%d %d\n", lts_i_out, lts_q_out);
$fflush(new_lts_fd);
end
if (pilot_in_stb && enable && (~reset) ) begin
$fwrite(phase_offset_pilot_input_fd, "%d %d\n", input_i, input_q);
$fflush(phase_offset_pilot_input_fd);
$fwrite(phase_offset_lts_input_fd, "%d %d\n", lts_i_out, lts_q_out);
$fflush(phase_offset_lts_input_fd);
end
if (pilot_out_stb && enable && (~reset) ) begin
$fwrite(phase_offset_pilot_fd, "%d %d\n", pilot_i, pilot_q);
$fflush(phase_offset_pilot_fd);
end
if (phase_in_stb && enable && (~reset) ) begin
$fwrite(phase_offset_pilot_sum_fd, "%d %d\n", pilot_sum_i, pilot_sum_q);
$fflush(phase_offset_pilot_sum_fd);
end
if (phase_out_stb && enable && (~reset) ) begin
$fwrite(phase_offset_phase_out_fd, "%d\n", phase_out_signed);
$fflush(phase_offset_phase_out_fd);
end
if (rot_out_stb && enable && (~reset) ) begin
$fwrite(rot_out_fd, "%d %d\n", rot_i, rot_q);
$fflush(rot_out_fd);
end
if (prod_out_strobe && enable && (~reset) ) begin
$fwrite(equalizer_prod_fd, "%d %d\n", prod_i_signed, prod_q_signed);
$fflush(equalizer_prod_fd);
$fwrite(equalizer_prod_scaled_fd, "%d %d\n", prod_i_scaled_signed, prod_q_scaled_signed);
$fflush(equalizer_prod_scaled_fd);
$fwrite(equalizer_mag_sq_fd, "%d\n", mag_sq);
$fflush(equalizer_mag_sq_fd);
end
if (sample_out_strobe && enable && (~reset) ) begin
$fwrite(equalizer_out_fd, "%d %d\n", norm_i_signed, norm_q_signed);
$fflush(equalizer_out_fd);
end end
end end
// ==========end of save signal to file for matlab bit-true comparison===========
*/
ram_2port #(.DWIDTH(32), .AWIDTH(6)) lts_inst ( ram_2port #(.DWIDTH(32), .AWIDTH(6)) lts_inst (
.clka(clock), .clka(clock),
@ -299,7 +253,7 @@ ram_2port #(.DWIDTH(32), .AWIDTH(6)) lts_inst (
calc_mean lts_i_inst ( calc_mean lts_i_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
.reset(reset), .reset(reset|reset_internal),
.a(lts_i_out), .a(lts_i_out),
.b(input_i), .b(input_i),
@ -313,7 +267,7 @@ calc_mean lts_i_inst (
calc_mean lts_q_inst ( calc_mean lts_q_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
.reset(reset), .reset(reset|reset_internal),
.a(lts_q_out), .a(lts_q_out),
.b(input_q), .b(input_q),
@ -341,7 +295,7 @@ ram_2port #(.DWIDTH(32), .AWIDTH(6)) in_buf_inst (
complex_mult pilot_inst ( complex_mult pilot_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
.reset(reset), .reset(reset|reset_internal),
.a_i(input_i), .a_i(input_i),
.a_q(input_q), .a_q(input_q),
.b_i(lts_i_out), .b_i(lts_i_out),
@ -355,11 +309,12 @@ complex_mult pilot_inst (
rotate rotate_inst ( rotate rotate_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
.reset(reset), .reset(reset|reset_internal),
.in_i(buf_i_out), .in_i(buf_i_out),
.in_q(buf_q_out), .in_q(buf_q_out),
.phase(sym_phase), // .phase(sym_phase),
.phase(sym_phase[15:0]),//only taking [15:0] to rotate could have overflow!
.input_strobe(rot_in_stb), .input_strobe(rot_in_stb),
.rot_addr(rot_addr), .rot_addr(rot_addr),
@ -373,7 +328,7 @@ rotate rotate_inst (
complex_mult input_lts_prod_inst ( complex_mult input_lts_prod_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
.reset(reset), .reset(reset|reset_internal),
.a_i(rot_i), .a_i(rot_i),
.a_q(rot_q), .a_q(rot_q),
.b_i(lts_i_out), .b_i(lts_i_out),
@ -387,7 +342,7 @@ complex_mult input_lts_prod_inst (
complex_mult lts_lts_prod_inst ( complex_mult lts_lts_prod_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
.reset(reset), .reset(reset|reset_internal),
.a_i(lts_i_out), .a_i(lts_i_out),
.a_q(lts_q_out), .a_q(lts_q_out),
.b_i(lts_i_out), .b_i(lts_i_out),
@ -399,7 +354,7 @@ complex_mult lts_lts_prod_inst (
divider norm_i_inst ( divider norm_i_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
.reset(reset), .reset(reset|reset_internal),
.dividend(dividend_i), .dividend(dividend_i),
.divisor(divisor_i), .divisor(divisor_i),
@ -412,7 +367,7 @@ divider norm_i_inst (
divider norm_q_inst ( divider norm_q_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
.reset(reset), .reset(reset|reset_internal),
.dividend(dividend_q), .dividend(dividend_q),
.divisor(divisor_q), .divisor(divisor_q),
@ -425,7 +380,7 @@ divider norm_q_inst (
divider lvpe_inst ( divider lvpe_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
.reset(reset), .reset(reset|reset_internal),
.dividend(lvpe_dividend), .dividend(lvpe_dividend),
.divisor(lvpe_divisor), .divisor(lvpe_divisor),
@ -440,13 +395,14 @@ localparam S_SECOND_LTS = 1;
localparam S_SMOOTH_CH_DC = 2; localparam S_SMOOTH_CH_DC = 2;
localparam S_SMOOTH_CH_LTS = 3; localparam S_SMOOTH_CH_LTS = 3;
localparam S_GET_POLARITY = 4; localparam S_GET_POLARITY = 4;
localparam S_CALC_FREQ_OFFSET = 5; localparam S_CPE_ESTIMATE = 5;
localparam S_CALC_SAMPL_OFFSET = 6; localparam S_PILOT_PE_CORRECTION = 6;
localparam S_ADJUST_FREQ_and_SAMPL_OFFSET = 7; localparam S_LVPE_ESTIMATE = 7;
localparam S_HT_LTS = 8; localparam S_ALL_SC_PE_CORRECTION = 8;
localparam S_HT_LTS = 9;
always @(posedge clock) begin always @(posedge clock) begin
if (reset) begin if (reset|reset_internal) begin
sample_out_strobe <= 0; sample_out_strobe <= 0;
lts_raddr <= 0; lts_raddr <= 0;
lts_waddr <= 0; lts_waddr <= 0;
@ -472,10 +428,12 @@ always @(posedge clock) begin
current_polarity <= 0; current_polarity <= 0;
pilot_count1 <= 0; pilot_count1 <= 0;
pilot_count2 <= 0; pilot_count2 <= 0;
pilot_count3 <= 0;
in_waddr <= 0; in_waddr <= 0;
in_raddr <= 0; in_raddr <= 0;
sym_idx <= 0; sym_idx <= 0;
sym_idx2 <= 0;
lts_reg1_i <= 0; lts_reg2_i <= 0; lts_reg3_i <= 0; lts_reg4_i <= 0; lts_reg5_i <= 0; lts_reg1_i <= 0; lts_reg2_i <= 0; lts_reg3_i <= 0; lts_reg4_i <= 0; lts_reg5_i <= 0;
lts_reg1_q <= 0; lts_reg2_q <= 0; lts_reg3_q <= 0; lts_reg4_q <= 0; lts_reg5_q <= 0; lts_reg1_q <= 0; lts_reg2_q <= 0; lts_reg3_q <= 0; lts_reg4_q <= 0; lts_reg5_q <= 0;
@ -496,6 +454,9 @@ always @(posedge clock) begin
pilot_i_reg <= 0; pilot_i_reg <= 0;
pilot_q_reg <= 0; pilot_q_reg <= 0;
pilot_iq_phase[0] <= 0; pilot_iq_phase[1] <= 0; pilot_iq_phase[2] <= 0; pilot_iq_phase[3] <= 0; pilot_iq_phase[0] <= 0; pilot_iq_phase[1] <= 0; pilot_iq_phase[2] <= 0; pilot_iq_phase[3] <= 0;
prev_peg <= 0;
prev_peg_reg <= 0;
peg_pilot_scale <= 0;
prod_in_strobe <= 0; prod_in_strobe <= 0;
@ -669,10 +630,10 @@ always @(posedge clock) begin
input_q <= 0; input_q <= 0;
lts_raddr <= 0; lts_raddr <= 0;
num_ofdm_sym <= num_ofdm_sym + 1; num_ofdm_sym <= num_ofdm_sym + 1;
state <= S_CALC_FREQ_OFFSET; state <= S_CPE_ESTIMATE;
end end
S_CALC_FREQ_OFFSET: begin S_CPE_ESTIMATE: begin
if (~ht & ht_next) begin if (~ht & ht_next) begin
ht <= 1; ht <= 1;
num_data_carrier <= 52; num_data_carrier <= 52;
@ -694,10 +655,8 @@ always @(posedge clock) begin
pilot_mask <= {pilot_mask[0], pilot_mask[63:1]}; pilot_mask <= {pilot_mask[0], pilot_mask[63:1]};
if (pilot_mask[0]) begin if (pilot_mask[0]) begin
pilot_count1 <= pilot_count1 + 1; pilot_count1 <= pilot_count1 + 1;
current_polarity <= {current_polarity[0],
current_polarity[3:1]};
// obtain the conjugate of current pilot sub carrier // obtain the conjugate of current pilot sub carrier
if (current_polarity[0] == 0) begin if (current_polarity[pilot_count1] == 0) begin
input_i <= sample_in[31:16]; input_i <= sample_in[31:16];
input_q <= ~sample_in[15:0] + 1; input_q <= ~sample_in[15:0] + 1;
end else begin end else begin
@ -715,50 +674,92 @@ always @(posedge clock) begin
if (pilot_out_stb) begin if (pilot_out_stb) begin
pilot_sum_i <= pilot_sum_i + pilot_i; pilot_sum_i <= pilot_sum_i + pilot_i;
pilot_sum_q <= pilot_sum_q + pilot_q; pilot_sum_q <= pilot_sum_q + pilot_q;
pilot_count2 <= pilot_count2 + 1;
end else if (pilot_count2 == 4) begin
pilot_i_reg <= pilot_sum_i;
pilot_q_reg <= pilot_sum_q;
phase_in_stb <= 1;
pilot_count2 <= 0;
end else begin
phase_in_stb <= 0;
end
if (phase_out_stb) begin
cpe <= phase_out;
pilot_count1 <= 0;
pilot_count2 <= 0;
pilot_count3 <= 0;
Sxy <= 0;
in_raddr <= pilot_loc[0][5:0]; // sample in location, compensate for RAM read delay
lts_raddr <= pilot_loc[0][5:0]; // LTS location, compensate for RAM read delay
peg_pilot_scale <= pilot_idx[0]*prev_peg;
state <= S_PILOT_PE_CORRECTION;
end
end
S_PILOT_PE_CORRECTION: begin
// rotate pilots with accumulated PEG up to previous symbol
if (pilot_count1 < 4) begin
if (pilot_count1 < 3) begin
in_raddr <= pilot_loc[pilot_count1+1][5:0];
peg_pilot_scale <= (pilot_idx[pilot_count1+1])*prev_peg;
rot_in_stb <= 1;
end
phase_err <= {cpe[15], cpe[15], cpe[15:0]} + peg_pilot_scale[17:0];
pilot_count1 <= pilot_count1 + 1;
end else begin
rot_in_stb <= 0;
end
if (rot_out_stb && pilot_count2 < 4) begin
if (pilot_count2 < 3) begin
lts_raddr <= pilot_loc[pilot_count2+1][5:0];
end
// obtain the conjugate of current pilot sub carrier
if (current_polarity[pilot_count2] == 0) begin
input_i <= rot_i;
input_q <= -rot_q;
end else begin
input_i <= -rot_i;
input_q <= rot_q;
end
pilot_in_stb <= 1; // start complex mult. with LTS pilot
pilot_count2 <= pilot_count2 + 1;
end else begin
pilot_in_stb <= 0;
end
if (pilot_out_stb) begin
pilot_i_reg <= pilot_i; pilot_i_reg <= pilot_i;
pilot_q_reg <= pilot_q; pilot_q_reg <= pilot_q;
phase_in_stb <= 1; phase_in_stb <= 1;
end else begin end else begin
phase_in_stb <= 0; phase_in_stb <= 0;
end end
if (phase_out_stb) begin if (phase_out_stb && pilot_count3 < 4) begin
pilot_count2 <= pilot_count2 + 1; pilot_count3 <= pilot_count3 + 1;
pilot_iq_phase[pilot_count2] <= phase_out; pilot_iq_phase[pilot_count3] <= phase_out;
`ifdef DEBUG_PRINT
$display("[PILOT OFFSET] %d", phase_out);
`endif
end else if (pilot_count2 > 3) begin
pilot_count2 <= pilot_count2 + 1;
end end
if (pilot_count2 == 8) begin if (pilot_count3 == 4) begin
pilot_count1 <= 0; phase_in_stb <= 0;
pilot_count2 <= 0; pilot_count1 <= 0;
cpe <= {(cpe[15] == 0 ? 2'b00:2'b11),cpe[15:2]}; pilot_count2 <= 0;
Sxy <= 0; pilot_count3 <= 0;
state <= S_CALC_SAMPL_OFFSET; state <= S_LVPE_ESTIMATE;
end else if (pilot_count2 > 3) begin
// sampling rate offset (SFO) is calculated as pilot phase error
if(pilot_sum_i < 0 && pilot_sum_q > 0 && pilot_iq_phase[pilot_count2[1:0]] < 0) begin
cpe = cpe + pilot_iq_phase[pilot_count2[1:0]] + 3217;
end else if(pilot_sum_i < 0 && pilot_sum_q < 0 && pilot_iq_phase[pilot_count2[1:0]] > 0) begin
cpe = cpe + pilot_iq_phase[pilot_count2[1:0]] - 3217;
end else begin
cpe = cpe + pilot_iq_phase[pilot_count2[1:0]];
end
end end
end end
S_CALC_SAMPL_OFFSET: begin S_LVPE_ESTIMATE: begin
if (pilot_count1 < 4) begin if (pilot_count1 < 4) begin
// sampling rate offset (SFO) is calculated as pilot phase error // sampling rate offset (SFO) is calculated as pilot phase error
if(cpe > 804 && pilot_iq_phase[pilot_count1] < 0) begin if(pilot_iq_phase[pilot_count1] < -1608) begin
pilot_phase_err <= pilot_iq_phase[pilot_count1] - cpe + 3217; pilot_phase_err <= pilot_iq_phase[pilot_count1] + 3217;
end else if(cpe < -804 && pilot_iq_phase[pilot_count1] > 0) begin end else if(pilot_iq_phase[pilot_count1] > 1608) begin
pilot_phase_err <= pilot_iq_phase[pilot_count1] - cpe - 3217; pilot_phase_err <= pilot_iq_phase[pilot_count1] - 3217;
end else begin end else begin
pilot_phase_err <= pilot_iq_phase[pilot_count1] - cpe; pilot_phase_err <= pilot_iq_phase[pilot_count1];
end end
pilot_count1 <= pilot_count1 + 1; pilot_count1 <= pilot_count1 + 1;
@ -773,20 +774,21 @@ always @(posedge clock) begin
end else if(pilot_count1 == 4) begin end else if(pilot_count1 == 4) begin
Sxy <= Sxy + -7*pilot_phase_err; Sxy <= Sxy + -7*pilot_phase_err;
in_raddr <= 0; in_raddr <= 0;
sym_idx <= 0; sym_idx <= 0;
sym_idx2 <= 1;
lvpe_in_stb <= 0; lvpe_in_stb <= 0;
// compensate for RAM read delay // compensate for RAM read delay
lts_raddr <= 1; lts_raddr <= 1;
rot_in_stb <= 0; rot_in_stb <= 0;
num_output <= 0; num_output <= 0;
state <= S_ADJUST_FREQ_and_SAMPL_OFFSET; state <= S_ALL_SC_PE_CORRECTION;
end end
// Sx² = ∑(x-x̄)*(x-x̄) = ∑x² = (7² + 21² + (-21)² + (-7)²) = 980 // Sx² = ∑(x-x̄)*(x-x̄) = ∑x² = (7² + 21² + (-21)² + (-7)²) = 980
// phase error gradient (PEG) = Sxy/Sx² // phase error gradient (PEG) = Sxy/Sx²
end end
S_ADJUST_FREQ_and_SAMPL_OFFSET: begin S_ALL_SC_PE_CORRECTION: begin
if (sym_idx < 64) begin if (sym_idx < 64) begin
sym_idx <= sym_idx + 1; sym_idx <= sym_idx + 1;
lvpe_in_stb <= 1; lvpe_in_stb <= 1;
@ -796,9 +798,14 @@ always @(posedge clock) begin
// first rotate, then normalize by avg LTS // first rotate, then normalize by avg LTS
if (lvpe_out_stb) begin if (lvpe_out_stb) begin
phase_err <= cpe + lvpe[15:0]; sym_idx2 <= sym_idx2 + 1;
phase_err <= {cpe[15], cpe[15], cpe[15:0]} + lvpe[17:0] + peg_sym_scale[17:0];
rot_in_stb <= 1; rot_in_stb <= 1;
in_raddr <= in_raddr + 1; in_raddr <= in_raddr + 1;
if (sym_idx2 == 32) begin
// lvpe output is 32*PEG due to sym_idx
prev_peg_reg <= prev_peg_reg + (lvpe >>> 5);
end
end else begin end else begin
rot_in_stb <= 0; rot_in_stb <= 0;
end end
@ -823,6 +830,7 @@ always @(posedge clock) begin
end end
if (num_output == num_data_carrier) begin if (num_output == num_data_carrier) begin
prev_peg <= prev_peg_reg;
state <= S_GET_POLARITY; state <= S_GET_POLARITY;
end end
end end

91
verilog/fifo_sample_delay.v Normal file
View File

@ -0,0 +1,91 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
`timescale 1 ns / 1 ps
module fifo_sample_delay #
(
parameter integer DATA_WIDTH = 8,
parameter integer LOG2_FIFO_DEPTH = 7
)
(
input wire clk,
input wire rst,
input wire [(LOG2_FIFO_DEPTH-1):0] delay_ctl,
input wire [(DATA_WIDTH-1):0] data_in,
input wire data_in_valid,
output wire [(DATA_WIDTH-1):0] data_out,
output wire data_out_valid
);
wire [LOG2_FIFO_DEPTH:0] rd_data_count;
wire [LOG2_FIFO_DEPTH:0] wr_data_count;
wire full;
wire empty;
reg rd_en_start;
wire rd_en;
reg [LOG2_FIFO_DEPTH:0] wr_data_count_reg;
wire wr_complete_pulse;
assign wr_complete_pulse = (wr_data_count > wr_data_count_reg);
assign rd_en = (rd_en_start&wr_complete_pulse);
assign data_out_valid = (rd_en_start&data_in_valid);
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"), // String
.ECC_MODE("no_ecc"), // String
.FIFO_MEMORY_TYPE("auto"), // String
.FIFO_READ_LATENCY(0), // DECIMAL
.FIFO_WRITE_DEPTH(1<<LOG2_FIFO_DEPTH), // DECIMAL
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(10), // DECIMAL
.PROG_FULL_THRESH(10), // DECIMAL
.RD_DATA_COUNT_WIDTH(LOG2_FIFO_DEPTH+1), // DECIMAL
.READ_DATA_WIDTH(DATA_WIDTH), // DECIMAL
.READ_MODE("fwft"), // String
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
.WAKEUP_TIME(0), // DECIMAL
.WRITE_DATA_WIDTH(DATA_WIDTH), // DECIMAL
.WR_DATA_COUNT_WIDTH(LOG2_FIFO_DEPTH+1) // DECIMAL
) fifo_1clk_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout(data_out),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(rd_data_count),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din(data_in),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(rst),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (rst) begin
wr_data_count_reg <= 0;
rd_en_start <= 0;
end else begin
wr_data_count_reg <= wr_data_count;
rd_en_start <= ((wr_data_count == delay_ctl)?1:rd_en_start);
end
end
endmodule

104
verilog/mv_avg.v Normal file
View File

@ -0,0 +1,104 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
module mv_avg
#(
parameter DATA_WIDTH = 16,
parameter LOG2_AVG_LEN = 5
)
(
input clk,
input rstn,
input signed [DATA_WIDTH-1:0] data_in,
input data_in_valid,
output wire signed [DATA_WIDTH-1:0] data_out,
output wire data_out_valid
);
localparam FIFO_SIZE = 1<<LOG2_AVG_LEN;
localparam TOTAL_WIDTH = DATA_WIDTH + LOG2_AVG_LEN;
reg signed [(TOTAL_WIDTH-1):0] running_total;
reg signed [DATA_WIDTH-1:0] data_in_reg; // to lock data_in by data_in_valid in case it changes in between two valid strobes
wire signed [DATA_WIDTH-1:0] data_in_old;
wire signed [TOTAL_WIDTH-1:0] ext_data_in_old = {{LOG2_AVG_LEN{data_in_old[DATA_WIDTH-1]}}, data_in_old};
wire signed [TOTAL_WIDTH-1:0] ext_data_in = {{LOG2_AVG_LEN{data_in_reg[DATA_WIDTH-1]}}, data_in_reg};
reg rd_en, rd_en_start;
wire [LOG2_AVG_LEN:0] wr_data_count;
reg [LOG2_AVG_LEN:0] wr_data_count_reg;
wire wr_complete_pulse;
reg wr_complete_pulse_reg;
assign wr_complete_pulse = (wr_data_count > wr_data_count_reg);
assign data_out_valid = wr_complete_pulse_reg;
assign data_out = running_total[TOTAL_WIDTH-1:LOG2_AVG_LEN];
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"), // String
.ECC_MODE("no_ecc"), // String
.FIFO_MEMORY_TYPE("auto"), // String
.FIFO_READ_LATENCY(0), // DECIMAL
.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL minimum 16!
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(10), // DECIMAL
.PROG_FULL_THRESH(10), // DECIMAL
.RD_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1), // DECIMAL
.READ_DATA_WIDTH(DATA_WIDTH), // DECIMAL
.READ_MODE("fwft"), // String
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
.WAKEUP_TIME(0), // DECIMAL
.WRITE_DATA_WIDTH(DATA_WIDTH), // DECIMAL
.WR_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1) // DECIMAL
) fifo_1clk_for_mv_avg_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout(data_in_old),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din(data_in),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(~rstn),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (~rstn) begin
data_in_reg <= 0;
wr_data_count_reg <= 0;
running_total <= 0;
rd_en <= 0;
rd_en_start <= 0;
wr_complete_pulse_reg <= 0;
end else begin
wr_complete_pulse_reg <= wr_complete_pulse;
data_in_reg <= (data_in_valid?data_in:data_in_reg);
wr_data_count_reg <= wr_data_count;
rd_en_start <= ((wr_data_count == (FIFO_SIZE))?1:rd_en_start);
rd_en <= (rd_en_start?wr_complete_pulse:rd_en);
if (wr_complete_pulse) begin
running_total <= running_total + ext_data_in - (rd_en_start?ext_data_in_old:0);
end
end
end
endmodule

118
verilog/mv_avg_dual_ch.v Normal file
View File

@ -0,0 +1,118 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
module mv_avg_dual_ch
#(
parameter DATA_WIDTH0 = 16,
parameter DATA_WIDTH1 = 16,
parameter LOG2_AVG_LEN = 5
)
(
input clk,
input rstn,
input signed [DATA_WIDTH0-1:0] data_in0,
input signed [DATA_WIDTH1-1:0] data_in1,
input data_in_valid,
output signed [DATA_WIDTH0-1:0] data_out0,
output signed [DATA_WIDTH1-1:0] data_out1,
output data_out_valid
);
localparam FIFO_SIZE = 1<<LOG2_AVG_LEN;
localparam TOTAL_WIDTH0 = DATA_WIDTH0 + LOG2_AVG_LEN;
localparam TOTAL_WIDTH1 = DATA_WIDTH1 + LOG2_AVG_LEN;
reg signed [(TOTAL_WIDTH0-1):0] running_total0;
reg signed [(TOTAL_WIDTH1-1):0] running_total1;
reg signed [DATA_WIDTH0-1:0] data_in0_reg; // to lock data_in by data_in_valid in case it changes in between two valid strobes
reg signed [DATA_WIDTH0-1:0] data_in1_reg; // to lock data_in by data_in_valid in case it changes in between two valid strobes
wire signed [DATA_WIDTH0-1:0] data_in_old0;
wire signed [DATA_WIDTH1-1:0] data_in_old1;
wire signed [TOTAL_WIDTH0-1:0] ext_data_in_old0 = {{LOG2_AVG_LEN{data_in_old0[DATA_WIDTH0-1]}}, data_in_old0};
wire signed [TOTAL_WIDTH0-1:0] ext_data_in0 = {{LOG2_AVG_LEN{data_in0_reg[DATA_WIDTH0-1]}}, data_in0_reg};
wire signed [TOTAL_WIDTH1-1:0] ext_data_in_old1 = {{LOG2_AVG_LEN{data_in_old1[DATA_WIDTH1-1]}}, data_in_old1};
wire signed [TOTAL_WIDTH1-1:0] ext_data_in1 = {{LOG2_AVG_LEN{data_in1_reg[DATA_WIDTH1-1]}}, data_in1_reg};
reg rd_en, rd_en_start;
wire [LOG2_AVG_LEN:0] wr_data_count;
reg [LOG2_AVG_LEN:0] wr_data_count_reg;
wire wr_complete_pulse;
reg wr_complete_pulse_reg;
assign wr_complete_pulse = (wr_data_count > wr_data_count_reg);
assign data_out_valid = wr_complete_pulse_reg;
assign data_out0 = running_total0[TOTAL_WIDTH0-1:LOG2_AVG_LEN];
assign data_out1 = running_total1[TOTAL_WIDTH1-1:LOG2_AVG_LEN];
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"), // String
.ECC_MODE("no_ecc"), // String
.FIFO_MEMORY_TYPE("auto"), // String
.FIFO_READ_LATENCY(0), // DECIMAL
.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL minimum 16!
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(10), // DECIMAL
.PROG_FULL_THRESH(10), // DECIMAL
.RD_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1), // DECIMAL
.READ_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL
.READ_MODE("fwft"), // String
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
.WAKEUP_TIME(0), // DECIMAL
.WRITE_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL
.WR_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1) // DECIMAL
) fifo_1clk_for_mv_avg_dual_ch_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout({data_in_old1, data_in_old0}),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din({data_in1, data_in0}),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(~rstn),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (~rstn) begin
data_in0_reg <= 0;
data_in1_reg <= 0;
wr_complete_pulse_reg <= 0;
wr_data_count_reg <= 0;
running_total0 <= 0;
running_total1 <= 0;
rd_en <= 0;
rd_en_start <= 0;
end else begin
data_in0_reg <= (data_in_valid?data_in0:data_in0_reg);
data_in1_reg <= (data_in_valid?data_in1:data_in1_reg);
wr_complete_pulse_reg <= wr_complete_pulse;
wr_data_count_reg <= wr_data_count;
rd_en_start <= ((wr_data_count == (FIFO_SIZE))?1:rd_en_start);
rd_en <= (rd_en_start?wr_complete_pulse:rd_en);
if (wr_complete_pulse) begin
running_total0 <= running_total0 + ext_data_in0 - (rd_en_start?ext_data_in_old0:0);
running_total1 <= running_total1 + ext_data_in1 - (rd_en_start?ext_data_in_old1:0);
end
end
end
endmodule

6
verilog/ofdm_decoder.v
View File

@ -11,7 +11,7 @@ module ofdm_decoder
// decode instructions // decode instructions
input [7:0] rate, input [7:0] rate,
input do_descramble, input do_descramble,
input [31:0] num_bits_to_decode, input [19:0] num_bits_to_decode, //4bits + ht_len: num_bits_to_decode <= (22+(ht_len<<3));
output [5:0] demod_out, output [5:0] demod_out,
output [5:0] demod_soft_bits, output [5:0] demod_soft_bits,
@ -55,7 +55,7 @@ reg [3:0] skip_bit;
reg bit_in; reg bit_in;
reg bit_in_stb; reg bit_in_stb;
reg [31:0] deinter_out_count; reg [19:0] deinter_out_count; // bitwidth same as num_bits_to_decode
//reg flush; //reg flush;
assign deinterleave_erase_out = {erase,deinterleave_out}; assign deinterleave_erase_out = {erase,deinterleave_out};
@ -159,7 +159,7 @@ always @(posedge clock) begin
deinter_out_count <= 0; deinter_out_count <= 0;
end else if (enable) begin end else if (enable) begin
if (deinterleave_out_strobe) begin if (deinterleave_out_strobe) begin
deinter_out_count <= deinter_out_count + 2; deinter_out_count <= deinter_out_count + 1;
end //else begin end //else begin
// wait for finishing deinterleaving current symbol // wait for finishing deinterleaving current symbol
// only do flush for non-DATA bits, such as SIG and HT-SIG, which // only do flush for non-DATA bits, such as SIG and HT-SIG, which

123
verilog/openofdm_rx.v
View File

@ -1,8 +1,16 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; // Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
`include "openofdm_rx_pre_def.v"
`timescale 1 ns / 1 ps `timescale 1 ns / 1 ps
`include "openofdm_rx_git_rev.v" `include "openofdm_rx_git_rev.v"
`ifdef OPENOFDM_RX_ENABLE_DBG
`define DEBUG_PREFIX (*mark_debug="true",DONT_TOUCH="TRUE"*)
`else
`define DEBUG_PREFIX
`endif
module openofdm_rx # module openofdm_rx #
( (
parameter integer IQ_DATA_WIDTH = 16, parameter integer IQ_DATA_WIDTH = 16,
@ -16,7 +24,7 @@
//input wire openofdm_core_rst, //input wire openofdm_core_rst,
input wire signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db, input wire signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db,
input wire [(2*IQ_DATA_WIDTH-1):0] sample_in, input wire [(2*IQ_DATA_WIDTH-1):0] sample_in,
input wire sample_in_strobe, input wire sample_in_strobe,
output wire demod_is_ongoing, // this needs to be corrected further to indicate actual RF on going regardless the latency output wire demod_is_ongoing, // this needs to be corrected further to indicate actual RF on going regardless the latency
// output wire pkt_ht, // output wire pkt_ht,
@ -38,13 +46,18 @@
output wire fcs_out_strobe, output wire fcs_out_strobe,
output wire fcs_ok, output wire fcs_ok,
// for side channel // for side channel
output wire [31:0] csi, output wire [31:0] csi,
output wire csi_valid, output wire csi_valid,
output wire signed [31:0] phase_offset_taken, output wire signed [31:0] phase_offset_taken,
output wire [31:0] equalizer, output wire [31:0] equalizer,
output wire equalizer_valid, output wire equalizer_valid,
output wire ofdm_symbol_eq_out_pulse, output wire ofdm_symbol_eq_out_pulse,
// phy len info
output [14:0] n_ofdm_sym,//max 20166 = (22+65535*8)/26 (max ht len 65535 in sig, min ndbps 26 for mcs0)
output [9:0] n_bit_in_last_sym,//max ht ndbps 260 (ht mcs7)
output phy_len_valid,
// axi lite based register configuration interface // axi lite based register configuration interface
input wire s00_axi_aclk, input wire s00_axi_aclk,
input wire s00_axi_aresetn, input wire s00_axi_aresetn,
@ -70,46 +83,50 @@
); );
// reg0~19 for config write; from reg20 for reading status // reg0~19 for config write; from reg20 for reading status
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg0; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg0;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg1; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg1; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg2; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg2;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg3; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg3; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg4; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg4; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg5; //
/* /*
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg5; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg6; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg6; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg7; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg7; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg8;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg8; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg9; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg9; // wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg10;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg10; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg11;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg11; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg12;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg12; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg13;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg13; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg14;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg14; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg15;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg15; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg16;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg16; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg17;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg17; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg18;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg18; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg19; */
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg19; */ wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg20; // read openofdm rx core internal state
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg20; // read openofdm rx core internal state /*
/* wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg21;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg21; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg22;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg22; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg23;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg23; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg24;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg24; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg25;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg25; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg26;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg26; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg27;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg27; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg28;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg28; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg29;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg29; wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg30;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg30; */
*/ wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31;
`DEBUG_PREFIX wire [(RSSI_HALF_DB_WIDTH-1):0] rx_sensitivity_th;
wire power_trigger;
wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
wire receiver_rst;
assign slv_reg31 = `OPENOFDM_RX_GIT_REV; assign slv_reg31 = `OPENOFDM_RX_GIT_REV;
wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid); assign rx_sensitivity_th = slv_reg2[(RSSI_HALF_DB_WIDTH-1):0];
wire receiver_rst;
signal_watchdog signal_watchdog_inst ( signal_watchdog signal_watchdog_inst (
.clk(s00_axi_aclk), .clk(s00_axi_aclk),
@ -120,10 +137,13 @@
.q_data(sample_in[15:0]), .q_data(sample_in[15:0]),
.iq_valid(sample_in_strobe), .iq_valid(sample_in_strobe),
.signal_len(pkt_len), .power_trigger(power_trigger|(~slv_reg1[12])),//by default the watchdog will run regardless the power_trigger
.sig_valid(sig_valid),
.max_signal_len_th(slv_reg4[31:16]), .signal_len(pkt_len),
.sig_valid(sig_valid),
.min_signal_len_th(slv_reg4[15:12]),
.max_signal_len_th(slv_reg4[31:16]),
.dc_running_sum_th(slv_reg2[23:16]), .dc_running_sum_th(slv_reg2[23:16]),
.receiver_rst(receiver_rst) .receiver_rst(receiver_rst)
@ -135,9 +155,11 @@
.enable( 1 ), .enable( 1 ),
//.reset ( (~s00_axi_aresetn)|slv_reg0[0]|openofdm_core_rst ), //.reset ( (~s00_axi_aresetn)|slv_reg0[0]|openofdm_core_rst ),
.reset ( (~s00_axi_aresetn)|slv_reg0[0]|receiver_rst ), .reset ( (~s00_axi_aresetn)|slv_reg0[0]|receiver_rst ),
.reset_without_watchdog((~s00_axi_aresetn)|slv_reg0[0]),
.power_thres(slv_reg2[10:0]), .power_thres(rx_sensitivity_th),
.min_plateau(slv_reg3), .min_plateau(slv_reg3),
.threshold_scale(~slv_reg1[8]),
.rssi_half_db(rssi_half_db), .rssi_half_db(rssi_half_db),
@ -164,16 +186,20 @@
.fcs_out_strobe(fcs_out_strobe), .fcs_out_strobe(fcs_out_strobe),
.fcs_ok(fcs_ok), .fcs_ok(fcs_ok),
.n_ofdm_sym(n_ofdm_sym),//max 20166 = (22+65535*8)/26 (max ht len 65535 in sig, min ndbps 26 for mcs0)
.n_bit_in_last_sym(n_bit_in_last_sym),//max ht ndbps 260 (ht mcs7)
.phy_len_valid(phy_len_valid),
///////////////////////////////////////////////////////// /////////////////////////////////////////////////////////
// DEBUG PORTS // DEBUG PORTS
///////////////////////////////////////////////////////// /////////////////////////////////////////////////////////
// decode status // decode status
.state(state), .state(),
.status_code(), .status_code(),
.state_changed(state_changed), .state_changed(state_changed),
.state_history(slv_reg20), .state_history(slv_reg20),
// power trigger // power trigger
.power_trigger(), .power_trigger(power_trigger),
// sync short // sync short
.short_preamble_detected(short_preamble_detected), .short_preamble_detected(short_preamble_detected),
@ -187,11 +213,12 @@
.sync_long_out_strobe(), .sync_long_out_strobe(),
.phase_offset_taken(phase_offset_taken), .phase_offset_taken(phase_offset_taken),
.sync_long_state(), .sync_long_state(),
.fft_win_shift(slv_reg5[3:0]),
// equalizer // equalizer
.equalizer_out(equalizer), .equalizer_out(equalizer),
.equalizer_out_strobe(equalizer_valid), .equalizer_out_strobe(equalizer_valid),
.equalizer_state(equalizer_state), .equalizer_state(),
.ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse), .ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse),
// legacy signal info // legacy signal info
@ -268,8 +295,8 @@
.SLV_REG1(slv_reg1), .SLV_REG1(slv_reg1),
.SLV_REG2(slv_reg2), .SLV_REG2(slv_reg2),
.SLV_REG3(slv_reg3), .SLV_REG3(slv_reg3),
.SLV_REG4(slv_reg4), /*, .SLV_REG4(slv_reg4),
.SLV_REG5(slv_reg5), .SLV_REG5(slv_reg5), /*,
.SLV_REG6(slv_reg6), .SLV_REG6(slv_reg6),
.SLV_REG7(slv_reg7), .SLV_REG7(slv_reg7),
.SLV_REG8(slv_reg8), .SLV_REG8(slv_reg8),

28
verilog/openofdm_rx_s_axi.v
View File

@ -21,8 +21,8 @@
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG1, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG1,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG2, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG2,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG3, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG3,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG4,/* output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG4,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG5, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG5,/*
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG6, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG6,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG7, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG7,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG8, output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG8,
@ -141,8 +141,8 @@
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;/* reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;/*
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
@ -189,8 +189,8 @@
assign SLV_REG1 = slv_reg1; assign SLV_REG1 = slv_reg1;
assign SLV_REG2 = slv_reg2; assign SLV_REG2 = slv_reg2;
assign SLV_REG3 = slv_reg3; assign SLV_REG3 = slv_reg3;
assign SLV_REG4 = slv_reg4;/* assign SLV_REG4 = slv_reg4;
assign SLV_REG5 = slv_reg5; assign SLV_REG5 = slv_reg5; /*
assign SLV_REG6 = slv_reg6; assign SLV_REG6 = slv_reg6;
assign SLV_REG7 = slv_reg7; assign SLV_REG7 = slv_reg7;
assign SLV_REG8 = slv_reg8; assign SLV_REG8 = slv_reg8;
@ -298,8 +298,8 @@
slv_reg1 <= 32'h0; slv_reg1 <= 32'h0;
slv_reg2 <= 32'h0; slv_reg2 <= 32'h0;
slv_reg3 <= 32'h0; slv_reg3 <= 32'h0;
slv_reg4 <= 32'h0;/* slv_reg4 <= 32'h0;
slv_reg5 <= 32'h0; slv_reg5 <= 32'h0; /*
slv_reg6 <= 32'h0; slv_reg6 <= 32'h0;
slv_reg7 <= 32'h0; slv_reg7 <= 32'h0;
slv_reg8 <= 32'h0; slv_reg8 <= 32'h0;
@ -353,14 +353,14 @@
// Respective byte enables are asserted as per write strobes // Respective byte enables are asserted as per write strobes
// Slave register 4 // Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end /* end
5'h05: 5'h05:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes // Respective byte enables are asserted as per write strobes
// Slave register 5 // Slave register 5
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end end /*
5'h06: 5'h06:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin if ( S_AXI_WSTRB[byte_index] == 1 ) begin
@ -548,8 +548,8 @@
slv_reg1 <= slv_reg1; slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2; slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3; slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;/* slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5; slv_reg5 <= slv_reg5; /*
slv_reg6 <= slv_reg6; slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7; slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8; slv_reg8 <= slv_reg8;
@ -688,8 +688,8 @@
5'h01 : reg_data_out <= slv_reg1; 5'h01 : reg_data_out <= slv_reg1;
5'h02 : reg_data_out <= slv_reg2; 5'h02 : reg_data_out <= slv_reg2;
5'h03 : reg_data_out <= slv_reg3; 5'h03 : reg_data_out <= slv_reg3;
5'h04 : reg_data_out <= slv_reg4;/* 5'h04 : reg_data_out <= slv_reg4;
5'h05 : reg_data_out <= slv_reg5; 5'h05 : reg_data_out <= slv_reg5; /*
5'h06 : reg_data_out <= slv_reg6; 5'h06 : reg_data_out <= slv_reg6;
5'h07 : reg_data_out <= slv_reg7; 5'h07 : reg_data_out <= slv_reg7;
5'h08 : reg_data_out <= slv_reg8; 5'h08 : reg_data_out <= slv_reg8;

116
verilog/phy_len_calculation.v Normal file
View File

@ -0,0 +1,116 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
// Calculate PHY related info:
// n_ofdm_sym, n_bit_in_last_sym (for decoding latency prediction)
module phy_len_calculation
(
input clock,
input reset,
input enable,
input [4:0] state,
input [4:0] old_state,
input [19:0] num_bits_to_decode,
input [7:0] pkt_rate,//bit [7] 1 means ht; 0 means non-ht
output reg [14:0] n_ofdm_sym,//max 20166 = (22+65535*8)/26
output reg [19:0] n_bit_in_last_sym,//max ht ndbps 260
output reg phy_len_valid
);
reg start_calculation;
reg end_calculation;
reg [8:0] n_dbps;
// lookup table for N_DBPS (Number of data bits per OFDM symbol)
always @( pkt_rate[7],pkt_rate[3:0] )
begin
case ({pkt_rate[7],pkt_rate[3:0]})
5'b01011 : begin //non-ht 6Mbps
n_dbps = 24;
end
5'b01111 : begin //non-ht 9Mbps
n_dbps = 36;
end
5'b01010 : begin //non-ht 12Mbps
n_dbps = 48;
end
5'b01110 : begin //non-ht 18Mbps
n_dbps = 72;
end
5'b01001 : begin //non-ht 24Mbps
n_dbps = 96;
end
5'b01101 : begin //non-ht 36Mbps
n_dbps = 144;
end
5'b01000 : begin //non-ht 48Mbps
n_dbps = 192;
end
5'b01100 : begin //non-ht 54Mbps
n_dbps = 216;
end
5'b10000 : begin //ht mcs 0
n_dbps = 26;
end
5'b10001 : begin //ht mcs 1
n_dbps = 52;
end
5'b10010 : begin //ht mcs 2
n_dbps = 78;
end
5'b10011 : begin //ht mcs 3
n_dbps = 104;
end
5'b10100 : begin //ht mcs 4
n_dbps = 156;
end
5'b10101 : begin //ht mcs 5
n_dbps = 208;
end
5'b10110 : begin //ht mcs 6
n_dbps = 234;
end
5'b10111 : begin //ht mcs 7
n_dbps = 260;
end
default: begin
n_dbps = 0;
end
endcase
end
`include "common_params.v"
always @(posedge clock) begin
if (reset) begin
n_ofdm_sym <= 1;
n_bit_in_last_sym <= 130; // half of max num bits to have a rough mid-point estimation in case no calculation happen
phy_len_valid <= 0;
start_calculation <= 0;
end_calculation <= 0;
end else begin
if ( (state != S_HT_SIG_ERROR && old_state == S_CHECK_HT_SIG) || ((state == S_DECODE_DATA && (old_state == S_CHECK_SIGNAL || old_state == S_DETECT_HT))) ) begin
n_bit_in_last_sym <= num_bits_to_decode;
if (num_bits_to_decode <= n_dbps) begin
phy_len_valid <= 1;
end_calculation <= 1;
end else begin
start_calculation <= 1;
end
end
if (start_calculation == 1 && end_calculation != 1) begin
if (n_bit_in_last_sym <= n_dbps) begin
phy_len_valid <= 1;
end_calculation <= 1;
end else begin
n_bit_in_last_sym <= n_bit_in_last_sym - n_dbps;
n_ofdm_sym = n_ofdm_sym + 1;
end
end
end
end
endmodule

18
verilog/signal_watchdog.v
View File

@ -14,9 +14,12 @@ module signal_watchdog
input signed [(IQ_DATA_WIDTH-1):0] q_data, input signed [(IQ_DATA_WIDTH-1):0] q_data,
input iq_valid, input iq_valid,
input power_trigger,
input [15:0] signal_len, input [15:0] signal_len,
input sig_valid, input sig_valid,
input [15:0] min_signal_len_th,
input [15:0] max_signal_len_th, input [15:0] max_signal_len_th,
input signed [(LOG2_SUM_LEN+2-1):0] dc_running_sum_th, input signed [(LOG2_SUM_LEN+2-1):0] dc_running_sum_th,
@ -24,6 +27,7 @@ module signal_watchdog
); );
wire signed [1:0] i_sign; wire signed [1:0] i_sign;
wire signed [1:0] q_sign; wire signed [1:0] q_sign;
reg signed [1:0] fake_non_dc_in_case_all_zero;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i; wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q; wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i_abs; wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i_abs;
@ -33,8 +37,8 @@ module signal_watchdog
reg receiver_rst_reg; reg receiver_rst_reg;
wire receiver_rst_pulse; wire receiver_rst_pulse;
assign i_sign = (i_data[(IQ_DATA_WIDTH-1)] ? -1 : 1); assign i_sign = (i_data == 0? fake_non_dc_in_case_all_zero : (i_data[(IQ_DATA_WIDTH-1)] ? -1 : 1) );
assign q_sign = (q_data[(IQ_DATA_WIDTH-1)] ? -1 : 1); assign q_sign = (q_data == 0? fake_non_dc_in_case_all_zero : (q_data[(IQ_DATA_WIDTH-1)] ? -1 : 1) );
assign running_sum_result_i_abs = (running_sum_result_i[LOG2_SUM_LEN+2-1]?(-running_sum_result_i):running_sum_result_i); assign running_sum_result_i_abs = (running_sum_result_i[LOG2_SUM_LEN+2-1]?(-running_sum_result_i):running_sum_result_i);
assign running_sum_result_q_abs = (running_sum_result_q[LOG2_SUM_LEN+2-1]?(-running_sum_result_q):running_sum_result_q); assign running_sum_result_q_abs = (running_sum_result_q[LOG2_SUM_LEN+2-1]?(-running_sum_result_q):running_sum_result_q);
@ -43,13 +47,21 @@ module signal_watchdog
assign receiver_rst_pulse = (receiver_rst_internal&&(~receiver_rst_reg)); assign receiver_rst_pulse = (receiver_rst_internal&&(~receiver_rst_reg));
assign receiver_rst = ( receiver_rst_reg | (sig_valid && (signal_len<14 || signal_len>max_signal_len_th)) ); assign receiver_rst = ( power_trigger & ( receiver_rst_reg | (sig_valid && (signal_len<min_signal_len_th || signal_len>max_signal_len_th)) ) );
always @(posedge clk) begin always @(posedge clk) begin
if (~rstn) begin if (~rstn) begin
receiver_rst_reg <= 0; receiver_rst_reg <= 0;
fake_non_dc_in_case_all_zero <= 1;
end else begin end else begin
receiver_rst_reg <= receiver_rst_internal; receiver_rst_reg <= receiver_rst_internal;
if (iq_valid) begin
if (fake_non_dc_in_case_all_zero == 1) begin
fake_non_dc_in_case_all_zero <= -1;
end else begin
fake_non_dc_in_case_all_zero <= 1;
end
end
end end
end end

50
verilog/sync_long.v
View File

@ -7,6 +7,7 @@ module sync_long (
input sample_in_strobe, input sample_in_strobe,
input signed [15:0] phase_offset, input signed [15:0] phase_offset,
input short_gi, input short_gi,
input [3:0] fft_win_shift,
output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr, output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
input [31:0] rot_data, input [31:0] rot_data,
@ -55,53 +56,6 @@ reg signed [31:0] next_phase_correction;
reg reset_delay ; // add reset signal for fft, somehow all kinds of event flag raises when feeding real rf signal, maybe reset will help reg reset_delay ; // add reset signal for fft, somehow all kinds of event flag raises when feeding real rf signal, maybe reset will help
wire fft_resetn ; wire fft_resetn ;
/*
// =============save signal to file for matlab bit-true comparison===========
integer file_open_trigger = 0;
integer sum_fd, metric_fd, phase_correction_fd, next_phase_correction_fd, fft_in_fd, fft_out_fd;
wire signed [15:0] fft_out_re_signed, fft_out_im_signed;
// wire signed [31:0] prod_i, prod_q, prod_avg_i, prod_avg_q, phase_in_i_signed, phase_in_q_signed, phase_out_signed;
// assign prod_i = prod[63:32];
assign fft_out_re_signed = fft_out_re[22:7];
assign fft_out_im_signed = fft_out_im[22:7];
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
sum_fd = $fopen("./sum.txt", "w");
metric_fd = $fopen("./metric.txt", "w");
phase_correction_fd = $fopen("./phase_correction.txt", "w");
next_phase_correction_fd = $fopen("./next_phase_correction.txt", "w");
fft_in_fd = $fopen("./fft_in.txt", "w");
fft_out_fd = $fopen("./fft_out.txt", "w");
end
if (sum_stb && enable && (~reset) ) begin
$fwrite(sum_fd, "%d %d\n", sum_i, sum_q);
$fflush(sum_fd);
end
if (metric_stb && enable && (~reset) ) begin
$fwrite(metric_fd, "%d\n", metric);
$fflush(metric_fd);
end
if (raw_stb && enable && (~reset) ) begin
$fwrite(phase_correction_fd, "%d\n", phase_correction);
$fflush(phase_correction_fd);
$fwrite(next_phase_correction_fd, "%d\n", next_phase_correction);
$fflush(next_phase_correction_fd);
end
if (fft_in_stb && enable && (~reset) ) begin
$fwrite(fft_in_fd, "%d %d\n", fft_in_re, fft_in_im);
$fflush(fft_in_fd);
end
if (fft_valid && enable && (~reset) ) begin
$fwrite(fft_out_fd, "%d %d\n", fft_out_re_signed, fft_out_im_signed);
$fflush(fft_out_fd);
end
end
// ==========end of save signal to file for matlab bit-true comparison===========
*/
always @(posedge clock) begin always @(posedge clock) begin
reset_delay = reset ; reset_delay = reset ;
end end
@ -324,7 +278,7 @@ always @(posedge clock) begin
if (metric_stb && (metric > metric_max1)) begin if (metric_stb && (metric > metric_max1)) begin
metric_max1 <= metric; metric_max1 <= metric;
addr1 <= in_raddr - 1; addr1 <= in_raddr - 1 -fft_win_shift;
end end
if (num_sample >= 88) begin if (num_sample >= 88) begin

225
verilog/sync_short.v
View File

@ -6,10 +6,12 @@ module sync_short (
input enable, input enable,
input [31:0] min_plateau, input [31:0] min_plateau,
input threshold_scale,
input [31:0] sample_in, input [31:0] sample_in,
input sample_in_strobe, input sample_in_strobe,
input demod_is_ongoing,
output reg short_preamble_detected, output reg short_preamble_detected,
input [15:0] phase_out, input [15:0] phase_out,
@ -26,6 +28,11 @@ module sync_short (
localparam WINDOW_SHIFT = 4; localparam WINDOW_SHIFT = 4;
localparam DELAY_SHIFT = 4; localparam DELAY_SHIFT = 4;
reg reset_delay1;
reg reset_delay2;
reg reset_delay3;
reg reset_delay4;
wire [31:0] mag_sq; wire [31:0] mag_sq;
wire mag_sq_stb; wire mag_sq_stb;
@ -42,16 +49,9 @@ reg sample_delayed_conj_stb;
wire [63:0] prod; wire [63:0] prod;
wire prod_stb; wire prod_stb;
reg [15:0] delay_i;
reg [15:0] delay_q_neg;
wire [63:0] prod_avg; wire [63:0] prod_avg;
wire prod_avg_stb; wire prod_avg_stb;
wire [31:0] freq_offset_i;
wire [31:0] freq_offset_q;
wire freq_offset_stb;
reg [15:0] phase_out_neg; reg [15:0] phase_out_neg;
reg [15:0] phase_offset_neg; reg [15:0] phase_offset_neg;
@ -78,64 +78,6 @@ reg has_neg;
.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), .clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(min_plateau), .changed());*/ .out(min_plateau), .changed());*/
/*
// =============save signal to file for matlab bit-true comparison===========
integer file_open_trigger = 0;
integer mag_sq_fd, mag_sq_avg_fd, prod_fd, prod_avg_fd, phase_in_fd, phase_out_fd, delay_prod_avg_mag_fd;
wire signed [31:0] prod_i, prod_q, prod_avg_i, prod_avg_q, phase_in_i_signed, phase_in_q_signed;
wire signed [15:0] phase_out_signed;
assign prod_i = prod[63:32];
assign prod_q = prod[31:0];
assign prod_avg_i = prod_avg[63:32];
assign prod_avg_q = prod_avg[31:0];
assign phase_in_i_signed = phase_in_i;
assign phase_in_q_signed = phase_in_q;
assign phase_out_signed = phase_out;
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
mag_sq_fd = $fopen("./mag_sq.txt", "w");
mag_sq_avg_fd = $fopen("./mag_sq_avg.txt", "w");
prod_fd = $fopen("./prod.txt", "w");
prod_avg_fd = $fopen("./prod_avg.txt", "w");
phase_in_fd = $fopen("./phase_in.txt", "w");
phase_out_fd = $fopen("./phase_out.txt", "w");
delay_prod_avg_mag_fd = $fopen("./delay_prod_avg_mag.txt", "w");
end
if (mag_sq_stb && enable && (~reset) ) begin
$fwrite(mag_sq_fd, "%d\n", mag_sq);
$fflush(mag_sq_fd);
end
if (mag_sq_avg_stb && enable && (~reset) ) begin
$fwrite(mag_sq_avg_fd, "%d\n", mag_sq_avg);
$fflush(mag_sq_avg_fd);
end
if (prod_stb && enable && (~reset) ) begin
$fwrite(prod_fd, "%d %d\n", prod_i, prod_q);
$fflush(prod_fd);
end
if (prod_avg_stb && enable && (~reset) ) begin
$fwrite(prod_avg_fd, "%d %d\n", prod_avg_i, prod_avg_q);
$fflush(prod_avg_fd);
end
if (phase_in_stb && enable && (~reset) ) begin
$fwrite(phase_in_fd, "%d %d\n", phase_in_i_signed, phase_in_q_signed);
$fflush(phase_in_fd);
end
if (phase_out_stb && enable && (~reset) ) begin
$fwrite(phase_out_fd, "%d\n", phase_out_signed);
$fflush(phase_out_fd);
end
if (delay_prod_avg_mag_stb && enable && (~reset) ) begin
$fwrite(delay_prod_avg_mag_fd, "%d\n", delay_prod_avg_mag);
$fflush(delay_prod_avg_mag_fd);
end
end
// ==========end of save signal to file for matlab bit-true comparison===========
*/
complex_to_mag_sq mag_sq_inst ( complex_to_mag_sq mag_sq_inst (
.clock(clock), .clock(clock),
.enable(enable), .enable(enable),
@ -149,26 +91,46 @@ complex_to_mag_sq mag_sq_inst (
.mag_sq_strobe(mag_sq_stb) .mag_sq_strobe(mag_sq_stb)
); );
moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(WINDOW_SHIFT)) mag_sq_avg_inst ( // moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(WINDOW_SHIFT)) mag_sq_avg_inst (
.clock(clock), // .clock(clock),
.enable(enable), // .enable(enable),
.reset(reset), // .reset(reset),
.data_in(mag_sq), // .data_in(mag_sq),
.input_strobe(mag_sq_stb), // .input_strobe(mag_sq_stb),
// .data_out(mag_sq_avg),
// .output_strobe(mag_sq_avg_stb)
// );
mv_avg #(.DATA_WIDTH(33), .LOG2_AVG_LEN(WINDOW_SHIFT)) mag_sq_avg_inst (
.clk(clock),
.rstn(~(reset|reset_delay1|reset_delay2|reset_delay3|reset_delay4)),
// .rstn(~reset),
.data_in({1'd0, mag_sq}),
.data_in_valid(mag_sq_stb),
.data_out(mag_sq_avg), .data_out(mag_sq_avg),
.output_strobe(mag_sq_avg_stb) .data_out_valid(mag_sq_avg_stb)
); );
delay_sample #(.DATA_WIDTH(32), .DELAY_SHIFT(DELAY_SHIFT)) sample_delayed_inst ( // delay_sample #(.DATA_WIDTH(32), .DELAY_SHIFT(DELAY_SHIFT)) sample_delayed_inst (
.clock(clock), // .clock(clock),
.enable(enable), // .enable(enable),
.reset(reset), // .reset(reset),
// .data_in(sample_in),
// .input_strobe(sample_in_strobe),
// .data_out(sample_delayed),
// .output_strobe(sample_delayed_stb)
// );
fifo_sample_delay # (.DATA_WIDTH(32), .LOG2_FIFO_DEPTH(5)) sample_delayed_inst (
.clk(clock),
.rst(reset|reset_delay1|reset_delay2|reset_delay3|reset_delay4),
.delay_ctl(16),
.data_in(sample_in), .data_in(sample_in),
.input_strobe(sample_in_strobe), .data_in_valid(sample_in_strobe),
.data_out(sample_delayed), .data_out(sample_delayed),
.output_strobe(sample_delayed_stb) .data_out_valid(sample_delayed_stb)
); );
complex_mult delay_prod_inst ( complex_mult delay_prod_inst (
@ -187,48 +149,53 @@ complex_mult delay_prod_inst (
.output_strobe(prod_stb) .output_strobe(prod_stb)
); );
moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(WINDOW_SHIFT)) // moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(WINDOW_SHIFT))
delay_prod_avg_i_inst ( // delay_prod_avg_i_inst (
.clock(clock), // .clock(clock),
.enable(enable), // .enable(enable),
.reset(reset), // .reset(reset),
.data_in(prod[63:32]), // .data_in(prod[63:32]),
.input_strobe(prod_stb), // .input_strobe(prod_stb),
.data_out(prod_avg[63:32]), // .data_out(prod_avg[63:32]),
.output_strobe(prod_avg_stb) // .output_strobe(prod_avg_stb)
// );
// moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(WINDOW_SHIFT))
// delay_prod_avg_q_inst (
// .clock(clock),
// .enable(enable),
// .reset(reset),
// .data_in(prod[31:0]),
// .input_strobe(prod_stb),
// .data_out(prod_avg[31:0])
// );
mv_avg_dual_ch #(.DATA_WIDTH0(32), .DATA_WIDTH1(32), .LOG2_AVG_LEN(WINDOW_SHIFT)) delay_prod_avg_inst (
.clk(clock),
.rstn(~(reset|reset_delay1|reset_delay2|reset_delay3|reset_delay4)),
// .rstn(~reset),
.data_in0(prod[63:32]),
.data_in1(prod[31:0]),
.data_in_valid(prod_stb),
.data_out0(prod_avg[63:32]),
.data_out1(prod_avg[31:0]),
.data_out_valid(prod_avg_stb)
); );
moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(WINDOW_SHIFT)) mv_avg_dual_ch #(.DATA_WIDTH0(32), .DATA_WIDTH1(32), .LOG2_AVG_LEN(6)) freq_offset_inst (
delay_prod_avg_q_inst ( .clk(clock),
.clock(clock), .rstn(~(reset|reset_delay1|reset_delay2|reset_delay3|reset_delay4)),
.enable(enable), // .rstn(~reset),
.reset(reset),
.data_in(prod[31:0]), .data_in0(prod[63:32]),
.input_strobe(prod_stb), .data_in1(prod[31:0]),
.data_out(prod_avg[31:0]) .data_in_valid(prod_stb),
);
.data_out0(phase_in_i),
// for fixing freq offset .data_out1(phase_in_q),
moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(6)) .data_out_valid(phase_in_stb)
freq_offset_i_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.data_in(prod[63:32]),
.input_strobe(prod_stb),
.data_out(phase_in_i),
.output_strobe(phase_in_stb)
);
moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(6))
freq_offset_q_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.data_in(prod[31:0]),
.input_strobe(prod_stb),
.data_out(phase_in_q)
); );
complex_to_mag #(.DATA_WIDTH(32)) delay_prod_avg_mag_inst ( complex_to_mag #(.DATA_WIDTH(32)) delay_prod_avg_mag_inst (
@ -245,6 +212,11 @@ complex_to_mag #(.DATA_WIDTH(32)) delay_prod_avg_mag_inst (
always @(posedge clock) begin always @(posedge clock) begin
if (reset) begin if (reset) begin
reset_delay1 <= reset;
reset_delay2 <= reset;
reset_delay3 <= reset;
reset_delay4 <= reset;
sample_delayed_conj <= 0; sample_delayed_conj <= 0;
sample_delayed_conj_stb <= 0; sample_delayed_conj_stb <= 0;
@ -260,8 +232,13 @@ always @(posedge clock) begin
plateau_count <= 0; plateau_count <= 0;
short_preamble_detected <= 0; short_preamble_detected <= 0;
phase_offset <= 0; phase_offset <= phase_offset; // do not clear it. sync short will reset soon after stf detected, but sync long still needs it.
end else if (enable) begin end else if (enable) begin
reset_delay4 <= reset_delay3;
reset_delay3 <= reset_delay2;
reset_delay2 <= reset_delay1;
reset_delay1 <= reset;
sample_delayed_conj_stb <= sample_delayed_stb; sample_delayed_conj_stb <= sample_delayed_stb;
sample_delayed_conj[31:16] <= sample_delayed[31:16]; sample_delayed_conj[31:16] <= sample_delayed[31:16];
sample_delayed_conj[15:0] <= ~sample_delayed[15:0]+1; sample_delayed_conj[15:0] <= ~sample_delayed[15:0]+1;
@ -274,7 +251,7 @@ always @(posedge clock) begin
phase_out_neg <= ~phase_out + 1; phase_out_neg <= ~phase_out + 1;
phase_offset_neg <= {{4{phase_out[15]}}, phase_out[15:4]}; phase_offset_neg <= {{4{phase_out[15]}}, phase_out[15:4]};
prod_thres <= {1'b0, mag_sq_avg[31:1]} + {2'b0, mag_sq_avg[31:2]}; prod_thres <= ( threshold_scale? ({2'b0, mag_sq_avg[31:2]} + {3'b0, mag_sq_avg[31:3]}):({1'b0, mag_sq_avg[31:1]} + {2'b0, mag_sq_avg[31:2]}) );
if (delay_prod_avg_mag_stb) begin if (delay_prod_avg_mag_stb) begin
if (delay_prod_avg_mag > prod_thres) begin if (delay_prod_avg_mag > prod_thres) begin
@ -288,10 +265,12 @@ always @(posedge clock) begin
pos_count <= 0; pos_count <= 0;
neg_count <= 0; neg_count <= 0;
short_preamble_detected <= has_pos & has_neg; short_preamble_detected <= has_pos & has_neg;
if(phase_out_neg[3] == 0) // E.g. 131/16 = 8.1875 -> 8, -138/16 = -8.625 -> -9 if (has_pos && has_neg && demod_is_ongoing==0) begin // only update and lock phase_offset to new value when short_preamble_detected and not start demod yet
phase_offset <= {{4{phase_out_neg[15]}}, phase_out_neg[15:4]}; if(phase_out_neg[3] == 0) // E.g. 131/16 = 8.1875 -> 8, -138/16 = -8.625 -> -9
else // E.g. -131/16 = -8.1875 -> -8, 138/16 = 8.625 -> 9 phase_offset <= {{4{phase_out_neg[15]}}, phase_out_neg[15:4]};
phase_offset <= ~phase_offset_neg + 1; else // E.g. -131/16 = -8.1875 -> -8, 138/16 = 8.625 -> 9
phase_offset <= ~phase_offset_neg + 1;
end
end else begin end else begin
plateau_count <= plateau_count + 1; plateau_count <= plateau_count + 1;
short_preamble_detected <= 0; short_preamble_detected <= 0;