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fix the atan_addr overflow issue (phase.v)

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Xianjun Jiao 2020-08-29 14:48:38 +02:00
parent 8c59d3a8dd
commit d7f5806790
1 changed files with 1 additions and 1 deletions
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verilog/phase.v
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@ -34,7 +34,7 @@ wire div_out_stb;
wire [`ATAN_LUT_LEN_SHIFT-1:0] atan_addr;
wire [`ATAN_LUT_SCALE_SHIFT-1:0] atan_data;
assign atan_addr = quotient[`ATAN_LUT_LEN_SHIFT-1:0];
assign atan_addr = (quotient>255?255:quotient[`ATAN_LUT_LEN_SHIFT-1:0]);
wire signed [`ATAN_LUT_SCALE_SHIFT:0] _phase = {1'b0, atan_data};
reg [2:0] quadrant;