From d7f5806790ab540c2bdc98dbe0e3a7f7720079ea Mon Sep 17 00:00:00 2001 From: Xianjun Jiao Date: Sat, 29 Aug 2020 14:48:38 +0200 Subject: [PATCH] fix the atan_addr overflow issue (phase.v) --- verilog/phase.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/phase.v b/verilog/phase.v index 5b2a9fb..4a1a2e3 100644 --- a/verilog/phase.v +++ b/verilog/phase.v @@ -34,7 +34,7 @@ wire div_out_stb; wire [`ATAN_LUT_LEN_SHIFT-1:0] atan_addr; wire [`ATAN_LUT_SCALE_SHIFT-1:0] atan_data; -assign atan_addr = quotient[`ATAN_LUT_LEN_SHIFT-1:0]; +assign atan_addr = (quotient>255?255:quotient[`ATAN_LUT_LEN_SHIFT-1:0]); wire signed [`ATAN_LUT_SCALE_SHIFT:0] _phase = {1'b0, atan_data}; reg [2:0] quadrant;