working

docs/Makefile

@@ -17,4 +17,7 @@ help:
 # Catch-all target: route all unknown targets to Sphinx using the new
 # "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
 %: Makefile
-	@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+	@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+livehtml:
+	sphinx-autobuild -b html $(SPHINXOPTS) $(SOURCEDIR) $(BUILDDIR)/html

docs/source/conf.py

@@ -87,7 +87,7 @@ todo_include_todos = True
 # The theme to use for HTML and HTML Help pages.  See the documentation for
 # a list of builtin themes.
 #
-html_theme = 'alabaster'
+html_theme = 'sphinx_rtd_theme'
 
 # Theme options are theme-specific and customize the look and feel of a theme
 # further.  For a list of options available for each theme, see the

docs/source/freq_offset.rst

@@ -0,0 +1,4 @@
+.. _freq_offset:
+
+Frequency Offset Correction
+===========================

docs/source/index.rst

@@ -10,6 +10,9 @@ Welcome to OpenOFDM's documentation!
    :maxdepth: 2
    :caption: Contents:
 
+   power
+   freq_offset
+
 
 
 Indices and tables

docs/source/power.rst

@@ -0,0 +1,28 @@
+Packet Detection
+================
+
+802.11 OFDM packets start with a short PLCP Preamble sequence to help the
+receiver detect the beginning of the packet. The short preamble duration is
+8 us. At 20 MSPS sampling rate, it contains 10 repeating sequence of 16 I/Q
+samples. The short preamble also helps the receiver for coarse frequency offset
+correction , which will be discussed separately in :ref:`freq_offset`.
+
+The core idea of detecting the short preamble is to utilize its repeating nature
+by calculating the auto correlation metric. But before that, we need to make sure
+we are trying to detect short preamble from "meaningful" signals. One example of
+"un-meaningful" signal is constant power levels, whose auto correlation metric
+is very high but does not represent packet beginning.
+
+Power Trigger
+-------------
+
+- **Module**: ``power_trigger.v``
+- **Input**: ``sample_in`` (16B I + 16B Q), ``sample_in_strobe`` (1B)
+- **Output**: ``trigger`` (1B)
+
+The first module in the pipeline is the ``power_trigger.v``. It takes the I/Q
+samples as input and asserts the ``trigger`` signal during a potential packet
+activity. Optionally, it can be configured to skip the first certain number of
+samples before detecting a power trigger. This is useful to skip the spurious
+signals during the intimal hardware stabilization phase.
+

requirements.txt

@@ -1,3 +1,2 @@
 numpy==1.11.2
 wltrace==1.1.1
-Sphinx==1.5.5

verilog/dot11_tb.v

@@ -111,11 +111,6 @@ initial begin
     set_addr = SR_SKIP_SAMPLE;
     set_data = 0;
 
-    # 20
-    // jam filter len
-    set_addr = SR_HEADER_LEN;
-    set_data = 32;
-
     # 20 set_stb = 0;
 
     bb_sample_fd = $fopen("./sim_out/sample_in.txt", "w");

verilog/power_trigger.v

@@ -4,13 +4,13 @@ module power_trigger
     input enable,
     input reset,
 
-    input [31:0] sample_in,
-    input sample_in_strobe,
-
     input set_stb,
     input [7:0] set_addr,
     input [31:0] set_data,
 
+    input [31:0] sample_in,
+    input sample_in_strobe,
+
     output reg trigger
 );
 `include "common_params.v"