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Add FFT window shift register

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This commit is contained in:
thavinga 2023-01-09 15:40:42 +01:00
parent 1b0354f85d
commit b0df85040f
5 changed files with 23 additions and 18 deletions
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2
verilog/dot11.v
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@ -25,6 +25,7 @@ module dot11 (
input soft_decoding,
input wire force_ht_smoothing,
input wire disable_all_smoothing,
input [3:0] fft_win_shift,
// OUTPUT: bytes and FCS status
output reg demod_is_ongoing,
@ -363,6 +364,7 @@ sync_long sync_long_inst (
.sample_in_strobe(sample_in_strobe),
.phase_offset(phase_offset),
.short_gi(short_gi),
.fft_win_shift(fft_win_shift),
.rot_addr(sync_long_rot_addr),
.rot_data(sync_long_rot_data),

1
verilog/dot11_tb.v
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@ -524,6 +524,7 @@ dot11 dot11_inst (
.soft_decoding(1'b1),
.force_ht_smoothing(1'b0),
.disable_all_smoothing(1'b0),
.fft_win_shift(4'b1),
.demod_is_ongoing(demod_is_ongoing),
.pkt_header_valid(pkt_header_valid),

7
verilog/openofdm_rx.v
View File

@ -82,8 +82,8 @@
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg2;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg3; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg4; //
/*
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg5; //
/*
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg6; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg7; //
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg8;
@ -204,6 +204,7 @@
.sync_long_out_strobe(),
.phase_offset_taken(phase_offset_taken),
.sync_long_state(),
.fft_win_shift(slv_reg5[3:0]),
// equalizer
.equalizer_out(equalizer),
@ -285,8 +286,8 @@
.SLV_REG1(slv_reg1),
.SLV_REG2(slv_reg2),
.SLV_REG3(slv_reg3),
.SLV_REG4(slv_reg4), /*,
.SLV_REG5(slv_reg5),
.SLV_REG4(slv_reg4),
.SLV_REG5(slv_reg5), /*,
.SLV_REG6(slv_reg6),
.SLV_REG7(slv_reg7),
.SLV_REG8(slv_reg8),

28
verilog/openofdm_rx_s_axi.v
View File

@ -21,8 +21,8 @@
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG1,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG2,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG3,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG4,/*
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG5,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG4,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG5,/*
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG6,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG7,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG8,
@ -141,8 +141,8 @@
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;/*
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;/*
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
@ -189,8 +189,8 @@
assign SLV_REG1 = slv_reg1;
assign SLV_REG2 = slv_reg2;
assign SLV_REG3 = slv_reg3;
assign SLV_REG4 = slv_reg4;/*
assign SLV_REG5 = slv_reg5;
assign SLV_REG4 = slv_reg4;
assign SLV_REG5 = slv_reg5; /*
assign SLV_REG6 = slv_reg6;
assign SLV_REG7 = slv_reg7;
assign SLV_REG8 = slv_reg8;
@ -298,8 +298,8 @@
slv_reg1 <= 32'h0;
slv_reg2 <= 32'h0;
slv_reg3 <= 32'h0;
slv_reg4 <= 32'h0;/*
slv_reg5 <= 32'h0;
slv_reg4 <= 32'h0;
slv_reg5 <= 32'h0; /*
slv_reg6 <= 32'h0;
slv_reg7 <= 32'h0;
slv_reg8 <= 32'h0;
@ -353,14 +353,14 @@
// Respective byte enables are asserted as per write strobes
// Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end /*
end
5'h05:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 5
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
end /*
5'h06:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
@ -548,8 +548,8 @@
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;/*
slv_reg5 <= slv_reg5;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5; /*
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
@ -688,8 +688,8 @@
5'h01 : reg_data_out <= slv_reg1;
5'h02 : reg_data_out <= slv_reg2;
5'h03 : reg_data_out <= slv_reg3;
5'h04 : reg_data_out <= slv_reg4;/*
5'h05 : reg_data_out <= slv_reg5;
5'h04 : reg_data_out <= slv_reg4;
5'h05 : reg_data_out <= slv_reg5; /*
5'h06 : reg_data_out <= slv_reg6;
5'h07 : reg_data_out <= slv_reg7;
5'h08 : reg_data_out <= slv_reg8;

3
verilog/sync_long.v
View File

@ -7,6 +7,7 @@ module sync_long (
input sample_in_strobe,
input signed [15:0] phase_offset,
input short_gi,
input [3:0] fft_win_shift,
output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
input [31:0] rot_data,
@ -277,7 +278,7 @@ always @(posedge clock) begin
if (metric_stb && (metric > metric_max1)) begin
metric_max1 <= metric;
addr1 <= in_raddr - 1;
addr1 <= in_raddr - 1 -fft_win_shift;
end
if (num_sample >= 88) begin