verilog init

verilog/Makefile

@@ -0,0 +1,45 @@
+###############################################################################
+#
+# ICARUS VERILOG & GTKWAVE MAKEFILE
+# MADE BY WILLIAM GIBB FOR HACDC
+# williamgibb@gmail.com
+# 
+# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
+#	"make check" - compiles your verilog design - good for checking code
+#	"make simulate" - compiles your design+TB & simulates your design
+#	"make display" - compiles, simulates and displays waveforms
+# 
+###############################################################################
+
+#TOOL INPUT
+SRC = $(wildcard *.v) $(wildcard *.mif) $(wildcard *.coe)
+MODULE_LIST = dot11_modules.list
+
+TESTBENCH = dot11_tb.v
+COMPILER_OUT = dot11.out			#COMPILER OUTPUT
+SIM_OUT = dot11.vcd
+
+###############################################################################
+# BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE
+###############################################################################
+#TOOLS
+COMPILER = iverilog
+SIMULATOR = vvp
+VIEWER = gtkwave
+
+#TOOL OPTIONS
+COMPILER_FLAGS = -v -c $(MODULE_LIST) -o $(COMPILER_OUT) -DDEBUG_PRINT
+SIMULATOR_FLAGS = -v -n
+###############################################################################
+
+#MAKE DIRECTIVES
+compile: $(TESTBENCH) $(SRC)
+	$(COMPILER) $(COMPILER_FLAGS) $(TESTBENCH)
+
+simulate: compile
+	$(SIMULATOR) $(SIMULATOR_FLAGS) $(COMPILER_OUT) 
+
+clean:
+	rm -rfv $(COMPILER_OUT) $(SIM_OUT)
+
+.PHONY: clean

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/ASYNC_FIFO_V5_1.v

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+/******************************************************************************
+ *
+ * $RCSfile: ASYNC_FIFO_V5_1.v,v $ $Revision: 1.15 $ $Date: 2008/09/08 20:05:11 $
+ *
+ ******************************************************************************
+ *
+ * Asynchronous FIFO V5_1 - Verilog Behavioral Model
+ *
+ ******************************************************************************
+ *
+ * Filename: ASYNC_FIFO_V5_1.v
+ *
+ * Description: 
+ *  The behavioral model for the asynchronous fifo.
+ *                      
+ ******************************************************************************/
+
+//  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.
+//  This text/file contains proprietary, confidential
+//  information of Xilinx, Inc., is distributed under license
+//  from Xilinx, Inc., and may be used, copied and/or
+//  disclosed only pursuant to the terms of a valid license
+//  agreement with Xilinx, Inc.  Xilinx hereby grants you
+//  a license to use this text/file solely for design, simulation,
+//  implementation and creation of design files limited
+//  to Xilinx devices or technologies. Use with non-Xilinx
+//  devices or technologies is expressly prohibited and
+//  immediately terminates your license unless covered by
+//  a separate agreement.
+//
+//  Xilinx is providing this design, code, or information
+//  "as is" solely for use in developing programs and
+//  solutions for Xilinx devices.  By providing this design,
+//  code, or information as one possible implementation of
+//  this feature, application or standard, Xilinx is making no
+//  representation that this implementation is free from any
+//  claims of infringement.  You are responsible for
+//  obtaining any rights you may require for your implementation.
+//  Xilinx expressly disclaims any warranty whatsoever with
+//  respect to the adequacy of the implementation, including
+//  but not limited to any warranties or representations that this
+//  implementation is free from claims of infringement, implied
+//  warranties of merchantability or fitness for a particular
+//  purpose.
+//
+//  Xilinx products are not intended for use in life support
+//  appliances, devices, or systems. Use in such applications are
+//  expressly prohibited.
+//
+//  This copyright and support notice must be retained as part
+//  of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc.
+//  All rights reserved.
+
+
+`timescale 1ns/10ps
+
+
+/******************************************************************************
+ * Declare top-level module 
+ ******************************************************************************/
+module ASYNC_FIFO_V5_1 (DIN, WR_EN, WR_CLK, RD_EN, RD_CLK, AINIT, DOUT, 
+                        FULL, EMPTY, ALMOST_FULL, ALMOST_EMPTY, 
+                        WR_COUNT, RD_COUNT, RD_ACK, RD_ERR, WR_ACK, WR_ERR);
+
+
+/*************************************************************************
+ * Definition of Ports
+ * DIN         : Input data bus for the fifo.
+ * DOUT        : Output data bus for the fifo.
+ * AINIT       : Asynchronous Reset for the fifo.
+ * WR_EN       : Write enable signal.
+ * WR_CLK      : Write Clock.
+ * FULL        : Indicates a full condition in the FIFO. Full is asserted 
+ *               when no more words can be written into the FIFO.
+ * ALMOST_FULL : Indicates that the FIFO only has room for one additional
+ *               word to be written before it is full.
+ * WR_ACK      : Acknowledgement of a successful write on the 
+ *               previous clock edge
+ * WR_ERR      : The write operation on the previous clock edge was
+ *               unsuccessful due to an overflow condition
+ * WR_COUNT    : Number of data words in fifo(synchronous to WR_CLK)
+ *               This is only the MSBs of the count value.
+ * RD_EN       : Read enable signal.
+ * RD_CLK      : Read Clock.
+ * EMPTY       : Indicates an empty condition in the FIFO. Empty is
+ *               asserted when no more words can be read from the FIFO.
+ * ALMOST_EMPTY: Indicates that the FIFO only has one word remaining 
+ *               in the FIFO. One additional read will cause an 
+ *               EMPTY condition.
+ * RD_ACK      : Acknowledgement of a successful read on the 
+ *               previous clock edge
+ * RD_ERR      : The read operation on the previous clock edge was
+ *               unsuccessful due to an underflow condition
+ * RD_COUNT    : Number of data words in fifo(synchronous to RD_CLK)
+ *               This is only the MSBs of the count value.
+ *************************************************************************/
+
+
+//Declare user parameters and their defaults
+parameter C_DATA_WIDTH		= 8;
+parameter C_ENABLE_RLOCS	= 0;
+parameter C_FIFO_DEPTH 		= 511;
+parameter C_HAS_ALMOST_EMPTY	= 1;
+parameter C_HAS_ALMOST_FULL 	= 1;
+parameter C_HAS_RD_ACK	        = 1;
+parameter C_HAS_RD_COUNT        = 1;
+parameter C_HAS_RD_ERR	        = 1;
+parameter C_HAS_WR_ACK	        = 1;
+parameter C_HAS_WR_COUNT        = 1;
+parameter C_HAS_WR_ERR	        = 1;
+parameter C_RD_ACK_LOW	        = 0;
+parameter C_RD_COUNT_WIDTH      = 2;
+parameter C_RD_ERR_LOW	        = 0;
+parameter C_USE_BLOCKMEM        = 1;
+parameter C_WR_ACK_LOW	        = 0;
+parameter C_WR_COUNT_WIDTH      = 2;
+parameter C_WR_ERR_LOW	        = 0;
+
+//Declare input and output ports
+input  [C_DATA_WIDTH-1 : 0] DIN;
+input  WR_EN;
+input  WR_CLK;
+input  RD_EN;
+input  RD_CLK;
+input  AINIT;
+output [C_DATA_WIDTH-1 : 0] DOUT;		
+output FULL;
+output EMPTY;
+output ALMOST_FULL;
+output ALMOST_EMPTY;
+output [C_WR_COUNT_WIDTH-1 : 0] WR_COUNT;
+output [C_RD_COUNT_WIDTH-1 : 0] RD_COUNT;
+output RD_ACK;
+output RD_ERR;
+output WR_ACK;
+output WR_ERR;
+
+/*************************************************************************
+ * Parameters used as constants
+ *************************************************************************/
+//length of the linked list which will simulate a FIFO
+parameter listlength = C_FIFO_DEPTH*(C_DATA_WIDTH+1);   
+
+/*************************************************************************
+  * Internal regs (for always blocks) and wires (for assign statements)
+ *************************************************************************/
+
+//Linked list to be used as an ideal FIFO
+reg [listlength:0] list;
+
+   
+//pulse asserted at posedge of WR_CLK
+reg wr_pulse;
+   
+//pulse asserted at posedge of RD_CLK
+reg rd_pulse;                  
+
+   
+//pulse asserted at conclusion of write operation
+reg wr_pulse_ack;                
+  
+//pulse asserted at conclusion of read operation
+reg rd_pulse_ack;                
+  
+
+//Special ideal FIFO signals
+reg [C_DATA_WIDTH-1:0] ideal_dout;
+reg ideal_wr_ack;
+reg ideal_rd_ack;
+reg ideal_wr_err;
+reg ideal_rd_err;
+reg ideal_full;
+reg ideal_empty;
+reg ideal_almost_full;
+reg ideal_almost_empty;
+   
+
+//Integer value for the number of words in the FIFO
+reg [31 : 0] ideal_wr_count_tmp;
+reg [31 : 0] ideal_rd_count_tmp;
+   
+//Integer value representing the MSBs of the counts
+reg [31 : 0] ideal_wr_count_int;
+reg [31 : 0] ideal_rd_count_int;
+   
+//MSBs of the counts
+reg [C_WR_COUNT_WIDTH-1 : 0] ideal_wr_count;
+reg [C_RD_COUNT_WIDTH-1 : 0] ideal_rd_count;
+
+   
+/*************************************************************************
+ * binary :
+ *  Calculates how many bits are needed to represent the input number
+ *************************************************************************/
+  function [31:0] binary;
+    input [31:0] inval;
+    integer power;
+    integer bits;
+  begin  
+    power = 1;
+    bits  = 0;
+    while (power <= inval)
+    begin
+      power = power * 2;
+      bits  = bits + 1;      
+    end //while
+    binary = bits;
+  end
+  endfunction //binary
+  
+/************************************************************************
+ * listsize:
+ * Returns number of entries in the linked list
+ *************************************************************************/
+  function [31:0] listsize;
+    input [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] inarray;
+    reg condition;
+    integer i;
+    integer j;
+  begin
+    condition = 1'b0;
+    i = 0;
+    j = 0;
+    while (condition == 1'b0)
+    begin
+      j = (C_DATA_WIDTH+1)*i;
+      if(inarray[j] == 1'b0)
+        condition  = 1'b1;
+      i = i + 1;
+    end //while
+    listsize = (i-1);
+  end
+  endfunction //listsize
+      
+/************************************************************************
+ * addlist :
+ * Add an entry to the end of the linked list
+ *************************************************************************/
+  function [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] addlist;
+    input [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] inarray;
+    input [C_DATA_WIDTH-1:0] inword;
+    reg [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] temp;
+    integer i;
+    integer j;
+  begin
+    temp = 1'b0;
+    i = listsize(inarray);
+    j = (i*(C_DATA_WIDTH+1));
+    temp[C_DATA_WIDTH:0] = {inword, 1'b1};
+    temp = temp << j; 
+    addlist = temp | inarray;
+  end
+  endfunction //addlist
+
+/************************************************************************
+ * readlist :
+ * Non-destructive read from the head of the linked list
+ *************************************************************************/
+  function [C_DATA_WIDTH-1:0] readlist;
+    input [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] inarray;
+  begin
+    readlist = inarray[C_DATA_WIDTH:1];
+  end
+  endfunction //readlist  
+
+/************************************************************************
+ * removelist :
+ * Remove/Delete entry from head of the linked list
+ *************************************************************************/
+  function [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] removelist;
+    input [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] inarray;
+  begin
+    removelist = inarray >> (C_DATA_WIDTH+1);
+  end
+  endfunction //removelist
+    
+
+/*************************************************************************
+ * Initialize Signals
+ *************************************************************************/
+  initial
+  begin
+   list     = 0;
+   wr_pulse = 1'b0;
+   rd_pulse = 1'b0;
+   wr_pulse_ack = 1'b0;
+   rd_pulse_ack = 1'b0;
+
+   ideal_dout   = 0;
+   ideal_wr_ack = 1'b0;
+   ideal_rd_ack = 1'b0;
+   ideal_wr_err = 1'b0;
+   ideal_rd_err = 1'b0;
+   ideal_full   = 1'b1;
+   ideal_empty  = 1'b1;
+   ideal_almost_full  = 1'b1;
+   ideal_almost_empty = 1'b1;
+   ideal_wr_count = 0;
+   ideal_rd_count = 0;
+  end
+
+
+/*************************************************************************
+ * Assign Internal ideal signals to output ports
+ *************************************************************************/
+assign DOUT         = ideal_dout;
+assign FULL         = ideal_full;
+assign EMPTY        = ideal_empty;
+assign ALMOST_FULL  = ideal_almost_full;
+assign ALMOST_EMPTY = ideal_almost_empty;
+assign WR_COUNT     = ideal_wr_count;
+assign RD_COUNT     = ideal_rd_count;
+
+//Handshaking signals can be active low, depending on _LOW parameters
+assign WR_ACK       = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
+assign WR_ERR       = ideal_wr_err ? !C_WR_ERR_LOW : C_WR_ERR_LOW;
+assign RD_ACK       = ideal_rd_ack ? !C_RD_ACK_LOW : C_RD_ACK_LOW;
+assign RD_ERR       = ideal_rd_err ? !C_RD_ERR_LOW : C_RD_ERR_LOW;
+
+   
+/*************************************************************************
+ * Generate read and write pulse signals
+ * 
+ * These pulses are instantaneous pulses which occur only in delta-time,
+ * and are never active for any amount of simulation time.
+ * 
+ * The pulses handshake with each other and the wr_pulse_ack and rd_pulse_ack
+ * signals to guarantee that they can never occur at the same time, and
+ * to guarantee that a write or read operation completes before the other
+ * can begin.
+ *************************************************************************/
+
+/********wr_pulse generator*************/
+  always @(posedge WR_CLK)
+  begin : gen_wr_pulse
+    //Wait until rd_pulse is 0 before setting the wr_pulse
+    // to make sure that they can't BOTH be active simultaneously.
+    wait (!rd_pulse && !rd_pulse_ack) 
+      wr_pulse = 1'b1;
+    
+    //Wait until read/write always block replies before clearing wr_pulse
+    wait (wr_pulse_ack) 
+      wr_pulse = 1'b0;
+
+  end // wr_pulse generator
+
+   
+/********rd_pulse generator*************/
+  always @(posedge RD_CLK)
+  begin : gen_rd_pulse
+    //Wait until wr_pulse is 0 before setting the rd_pulse
+    // to make sure that they can't BOTH be active simultaneously.
+    wait (!wr_pulse && !wr_pulse_ack) 
+      rd_pulse = 1'b1;
+
+    //Wait until read/write always block replies before clearing rd_pulse
+    wait (rd_pulse_ack) 
+      rd_pulse = 1'b0;
+
+  end // rd_pulse generator
+
+
+   
+/*************************************************************************
+ * Read and Write from FIFO (FIFO is implemented by a linked list)
+ * 
+ * The following are the possible scenarios for the FIFO:
+ *
+ * 1) AINIT=1, in which case a reset condition occurs, all outputs and
+ *    internal states are cleared, and the triggering pulse is cleared.
+ * 
+ * 2) This process was triggered with ONLY a wr_pulse, rd_pulse is 0.
+ *    This is a normal case. Only a write operation is performed.
+ * 
+ * 3) This process was triggered with ONLY a rd_pulse, wr_pulse is 0.
+ *    This is a normal case. Only a read operation is performed.
+ * 
+ * 4) This process was triggered with ONLY a wr_pulse, but rd_pulse is also 1.
+ *    The pulse generator processes (above) require that one pulse be cleared
+ *    before the other can be activated. This should prevent this case from 
+ *    occurring.
+ * 
+ * 5) This process was triggered with ONLY a rd_pulse, but wr_pulse is also 1.
+ *    The pulse generator processes (above) require that one pulse be cleared
+ *    before the other can be activated. This should prevent this case from 
+ *    occurring.
+ * 
+ * 6) This process was triggered with BOTH a wr_pulse and a rd_pulse
+ *    simultaneously, and was only triggerred once. It was found through
+ *    experimentation that this case is actually possible.
+ *    This case is handled explicitly below as an error.
+ *    Handshaking between pulse generation processes, and the requirement
+ *    that a rd_pulse_ack or wr_pulse_ack must be asserted before continuing
+ *    should prevent this from occuring.
+ *************************************************************************/
+   
+   always @(posedge wr_pulse or posedge rd_pulse or posedge AINIT)
+     begin : gen_fifo
+	
+	/****** Reset fifo (case 1)***************************************/
+	if (AINIT == 1'b1)
+	  begin
+	     list   <= 0;
+	     ideal_dout <= 0;
+	     ideal_wr_ack <= 1'b0;
+	     ideal_rd_ack <= 1'b0;
+	     ideal_wr_err <= 1'b0;
+	     ideal_rd_err <= 1'b0;
+	     ideal_full <= 1'b1;
+	     ideal_almost_full <= 1'b1;
+	     ideal_empty <= 1'b1;
+	     ideal_almost_empty <= 1'b1;
+	     ideal_wr_count <= 0;
+	     ideal_rd_count <= 0;
+	     
+	     //If either pulse is set, acknowledge and clear it
+	     if ((wr_pulse == 1'b1) && (rd_pulse == 1'b1))
+	       $display ("ERROR: Illegal operation internal to async_fifo_v5_1 Verilog model.");
+	     
+	     if (wr_pulse == 1'b1)
+	       begin
+		  wr_pulse_ack = 1'b1;
+		  wait (!wr_pulse) 
+                    wr_pulse_ack = 1'b0;
+	       end
+	     
+	     if (rd_pulse == 1'b1)
+	       begin
+		  rd_pulse_ack = 1'b1;
+		  wait (!rd_pulse) 
+                    rd_pulse_ack = 1'b0;
+	       end
+	     
+	     
+	  end // if (AINIT == 1'b1)
+	
+	
+	else  //AINIT == 1'b0
+	  
+	  begin
+	     
+	     /*********** Error: read AND write to the fifo (case 5) ********/
+	     if ((wr_pulse == 1'b1) && (rd_pulse == 1'b1))
+	       $display ("ERROR: Illegal operation internal to async_fifo_v5_1 Verilog model.");
+	     
+	     /****** Write operation (case 2) *******************************/
+	     if (wr_pulse == 1'b1)
+	       begin
+		  //If this is a write, handle the write by adding the value
+		  // to the linked list, and updating all outputs appropriately
+		  if (WR_EN == 1'b1)
+		    begin
+		       
+		       //If the FIFO is completely empty, but we are 
+		       // successfully  writing to it
+		       if (listsize(list) == 0)
+			 begin
+			    //Add value on DIN port to linked list
+			    list         = addlist(list,DIN);
+			    //Write successful, so issue acknowledge
+			    // and no error
+			    ideal_wr_ack = 1'b1;
+			    ideal_wr_err = 1'b0;
+			    //Not even close to full.
+			    ideal_full   = 1'b0;
+			    ideal_almost_full  = 1'b0;
+			    //Writing, so not empty.
+			    ideal_empty  = 1'b0;
+			    // Will still be almost empty after 1 write
+			    ideal_almost_empty = 1'b1;
+			    
+			    ideal_wr_count_tmp = listsize(list);
+			    ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+			    ideal_wr_count     = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0];
+			 end //(listsize(list) == 0)
+		       
+		       //If the FIFO is not close to being full, and not empty
+		       else if ((listsize(list) < C_FIFO_DEPTH-2) && (listsize(list)>=1))
+			 begin
+			    //Add value on DIN port to linked list
+			    list         = addlist(list,DIN);
+			    //Write successful, so issue acknowledge
+			    // and no error
+			    ideal_wr_ack = 1'b1;
+			    ideal_wr_err = 1'b0;
+			    //Not even close to full.
+			    ideal_full   = 1'b0;
+			    ideal_almost_full  = 1'b0;
+			    //not close to empty
+			    ideal_empty  = 1'b0;
+			    //Was not empty, so this write will make FIFO 
+			    // no longer almost_empty
+			    ideal_almost_empty = 1'b0;
+			    
+			    ideal_wr_count_tmp = listsize(list);
+			    ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+			    ideal_wr_count     = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0];
+			 end // if
+		       
+		       //If the FIFO is 2 from full
+		       else if (listsize(list) == C_FIFO_DEPTH-2)
+			 begin
+			    //Add value on DIN port to linked list
+		            list         = addlist(list,DIN);
+			    //Write successful, so issue acknowledge
+			    // and no error
+			    ideal_wr_ack = 1'b1;
+			    ideal_wr_err = 1'b0;
+			    //Still 2 from full
+			    ideal_full   = 1'b0;
+			    //2 from full, and writing, so set almost_full
+			    ideal_almost_full  = 1'b1;
+			    //not even close to empty
+			    ideal_empty  = 1'b0;
+			    ideal_almost_empty = 1'b0;
+			    
+			    ideal_wr_count_tmp = listsize(list);
+			    ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+			    ideal_wr_count     = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0];
+			 end // if (listsize(list) == C_FIFO_DEPTH-2)
+		       
+		       //If the FIFO is one from full
+		       else if (listsize(list) == C_FIFO_DEPTH-1)
+			 begin
+			    //Add value on DIN port to linked list
+		            list         = addlist(list,DIN);
+			    //Write successful, so issue acknowledge
+			    // and no error
+			    ideal_wr_ack = 1'b1;
+			    ideal_wr_err = 1'b0;
+			    //This write is CAUSING the FIFO to go full
+			    ideal_full   = 1'b1;
+			    ideal_almost_full  = 1'b1;
+			    //Not even close to empty
+			    ideal_empty  = 1'b0;
+			    ideal_almost_empty = 1'b0;
+			    
+			    ideal_wr_count_tmp = listsize(list);
+			    ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+			    ideal_wr_count     = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0];
+			 end // if (listsize(list) == C_FIFO_DEPTH-1)
+		       
+ 		       //If the FIFO is full, do NOT perform the write, 
+		       // update flags accordingly
+		       else if (listsize(list) >= C_FIFO_DEPTH)
+			 begin
+			    //write unsuccessful - do not change contents
+		            list         = list;
+			    //Do not acknowledge the write
+			    ideal_wr_ack = 1'b0;
+			    //throw an overflow error
+			    ideal_wr_err = 1'b1;
+			    //Reminder that FIFO is still full
+			    ideal_full   = 1'b1;
+			    ideal_almost_full   = 1'b1;
+			    //Not even close to empty
+ 			    ideal_empty  = 1'b0;
+			    ideal_almost_empty  = 1'b0;
+			    
+			    ideal_wr_count_tmp = listsize(list);
+			    ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+			    ideal_wr_count = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0];
+			 end
+		    end //(WR_EN == 1'b1)
+		  
+		  else //if (WR_EN == 1'b0)
+		    begin
+		       //If user did not attempt a write, then do not 
+		       // give ack or err
+		       ideal_wr_ack = 1'b0; 
+		       ideal_wr_err = 1'b0;
+		       
+		       //Implied statements:
+		       //ideal_empty = ideal_empty;
+		       //ideal_almost_empty = ideal_almost_empty;
+		       
+		       //Check for full
+		       if (listsize(list) > C_FIFO_DEPTH-1)      
+			 ideal_full = 1'b1;
+		       else
+			 ideal_full  = 1'b0;
+		       
+		       //Check for almost_full
+		       if (listsize(list) > C_FIFO_DEPTH-2)      
+			 ideal_almost_full  = 1'b1;
+		       else
+			 ideal_almost_full  = 1'b0;
+		       
+		       
+		       ideal_wr_count_tmp = listsize(list);
+		       ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+		       ideal_wr_count = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0];
+		    end
+		  
+		  
+		  //Whether it was a write or not, clear the pulse
+		  wr_pulse_ack = 1'b1;
+		  wait (!wr_pulse) 
+                    wr_pulse_ack = 1'b0;
+               end
+	     
+	     
+	     /****** Read operation (case 3) **********************************/
+	     if (rd_pulse == 1'b1) 
+	       begin
+		  //If this is a read, handle the read by popping the value off the linked list
+		  if (RD_EN == 1'b1) 
+		    begin
+		       
+		       //If the FIFO is completely empty
+		       if (listsize(list) <= 0)
+			 begin
+			    //Do not change the contents of the FIFO
+			    list         = list;
+			    //Read nothing (0) from the empty FIFO
+			    ideal_dout   = 0;
+                            //Do not acknowledge the read from empty FIFO
+			    ideal_rd_ack = 1'b0;
+			    //Throw an underflow error
+			    ideal_rd_err = 1'b1;
+			    //Not even close to full
+			    ideal_full   = 1'b0;
+			    ideal_almost_full = 1'b0;
+			    //Reminder that FIFO is still empty
+			    ideal_empty  = 1'b1; 
+			    ideal_almost_empty = 1'b1;
+			    
+			    ideal_rd_count_tmp = listsize(list);
+			    ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+			    ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0];
+			 end // if (listsize(list) <= 0)
+		       
+		       //If the FIFO is one from empty
+		       else if (listsize(list) == 1)
+			 begin
+			    //Read top value from the FIFO
+			    ideal_dout   = readlist(list);
+			    //Pop single value off of linked list
+			    list         = removelist(list);
+			    //Acknowledge the read from the FIFO, no error
+			    ideal_rd_ack = 1'b1;
+			    ideal_rd_err = 1'b0;
+			    //Not even close to full
+ 			    ideal_full   = 1'b0;
+			    ideal_almost_full = 1'b0;
+			    //Note that FIFO is GOING empty
+			    ideal_empty  = 1'b1; 
+			    ideal_almost_empty = 1'b1; 
+			    
+			    ideal_rd_count_tmp = listsize(list);
+			    ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+			    ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0];
+			 end // if (listsize(list) == 1)
+		       
+		       //If the FIFO is two from empty
+		       else if (listsize(list) == 2)
+			 begin
+			    //Read top value from the FIFO
+			    ideal_dout   = readlist(list);
+			    //Pop single value off of linked list
+			    list         = removelist(list);
+			    //Acknowledge the read from the FIFO, no error
+			    ideal_rd_ack = 1'b1; 
+			    ideal_rd_err = 1'b0;
+			    //Not even close to full
+ 			    ideal_full   = 1'b0;
+			    ideal_almost_full = 1'b0;
+			    //Fifo is not yet empty
+			    ideal_empty  = 1'b0;
+			    //2 from empty and reading, so going almost_empty
+			    ideal_almost_empty = 1'b1; 
+			    
+			    ideal_rd_count_tmp = listsize(list);
+			    ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+			    ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0];
+			 end // if (listsize(list) == 2)
+		       
+		       //If the FIFO is not close to being empty
+		       else if ((listsize(list) > 2) && (listsize(list)<=C_FIFO_DEPTH-1))
+			 begin
+			    //Read top value from the FIFO
+			    ideal_dout   = readlist(list);
+			    //Pop single value off of linked list
+			    list         = removelist(list);
+			    //Acknowledge the read from the FIFO, no error
+			    ideal_rd_ack = 1'b1; 
+			    ideal_rd_err = 1'b0;
+			    //Reading, so not FULL
+ 			    ideal_full   = 1'b0;
+			    //At least one from full AND reading, so no longer almost_full
+			    ideal_almost_full = 1'b0;
+			    //Not close to empty
+			    ideal_empty  = 1'b0;
+			    ideal_almost_empty = 1'b0;
+			    
+			    ideal_rd_count_tmp = listsize(list);
+			    ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+			    ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0];
+			 end // if ((listsize(list) > 2) && (listsize(list)<=C_FIFO_DEPTH-1))
+		       
+		       //If the FIFO is completely full, and we are successfully reading from it
+		       else if (listsize(list) == C_FIFO_DEPTH)
+			 begin
+			    //Read top value from the FIFO
+			    ideal_dout   = readlist(list);
+			    //Pop single value off of linked list
+			    list         = removelist(list);
+			    //Acknowledge the read from the FIFO, no error
+			    ideal_rd_ack = 1'b1; 
+			    ideal_rd_err = 1'b0;
+			    //Reading, so not FULL
+ 			    ideal_full   = 1'b0;
+			    //Was just full, and this is only the first read
+			    ideal_almost_full = 1'b1;
+			    //Not close to empty
+			    ideal_empty  = 1'b0;
+			    ideal_almost_empty = 1'b0;
+			    
+			    ideal_rd_count_tmp = listsize(list);
+			    ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+			    ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0];
+			 end // if (listsize(list) == C_FIFO_DEPTH)
+		       
+ 		    end //(RD_EN == 1'b1)
+		  
+		  else //if (RD_EN == 1'b0)
+		    begin
+		       //If user did not attempt a read, do not give an ack or err
+		       ideal_rd_ack = 1'b0;
+		       ideal_rd_err = 1'b0;
+		       
+		       //Check for empty
+		       if (listsize(list) < 1)      
+			 ideal_empty  = 1'b1;
+		       else
+			 ideal_empty  = 1'b0;
+		       
+		       //Check for almost_empty
+		       if (listsize(list) < 2)      
+			 ideal_almost_empty  = 1'b1;
+		       else
+			 ideal_almost_empty  = 1'b0;
+		       
+		       //Implied statements:
+		       //ideal_full = ideal_full;
+		       //ideal_almost_full  =ideal_almost_full;
+		       
+		       
+		       ideal_rd_count_tmp = listsize(list);
+		       ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1);
+		       ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0];
+		    end // else: !if(RD_EN == 1'b1)
+		  		  
+		  
+		  //Whether it was a read or not, clear the pulse
+		  rd_pulse_ack = 1'b1;
+		  wait (!rd_pulse) 
+                    rd_pulse_ack = 1'b0;
+               end // if (rd_pulse == 1'b1)
+	     
+	  end // else: !if(AINIT == 1'b1)
+     end // block: gen_fifo
+   
+endmodule // ASYNC_FIFO_V5_1

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V4_0.v

@@ -0,0 +1,534 @@
+/*****************************************************************************
+ * $Id: BLKMEMSP_V4_0.v,v 1.17 2008/09/08 20:06:34 akennedy Exp $
+ *****************************************************************************
+ * Block Memory Compiler - Verilog Behavioral Model
+ *****************************************************************************
+ *
+ * This File is owned and controlled by Xilinx and must be used solely  
+ * for design, simulation, implementation and creation of design files   
+ * limited to Xilinx devices or technologies. Use with non-Xilinx       
+ * devices or technologies is expressly prohibited and immediately      
+ * terminates your license.                                             
+ *                                                                      
+ * Xilinx products are not intended for use in life support             
+ * appliances, devices, or systems. Use in such applications is          
+ * expressly prohibited.
+ * 
+ *        ****************************
+ *        ** Copyright Xilinx, Inc. **
+ *        ** All rights reserved.   **
+ *        ****************************
+ *
+ *************************************************************************
+ * Filename:   blkmemsp_v4_0
+ *
+ * Decsription: Single Port V2 BRAM behavioral model. Extendable depth/width.
+ *              The behavior for EN = `X`, WE = `X`, and for CLK transitions to
+ *              or from `X` is not considered.
+ *
+ **************************************************************************/
+`timescale 1ns/10ps
+
+`celldefine
+
+
+`define c_sp_rom 0
+`define c_sp_ram 1
+`define c_write_first 0
+`define c_read_first  1
+`define c_no_change   2
+
+module BLKMEMSP_V4_0(DOUT,  ADDR, DIN,  EN, CLK, WE, SINIT, ND, RFD, RDY);
+
+  parameter  c_addr_width          =  9 ; // controls address width of memory
+  parameter  c_default_data        = "0"; // indicates string of hex characters used to initialize memory
+  parameter  c_depth               = 512 ; // controls depth of memory
+  parameter  c_enable_rlocs        = 0 ; //  core includes placement constraints
+  parameter  c_has_default_data    =  1; // initializes contents of memory to c_default_data
+  parameter  c_has_din             = 1  ; // indicates memory has data input pins
+  parameter  c_has_en              =  1 ; // indicates memory has a EN pin
+  parameter  c_has_limit_data_pitch       = 0  ; //  
+  parameter  c_has_nd              = 0  ; //  Memory has a new data pin
+  parameter  c_has_rdy             = 0  ; //  Memory has result ready pin
+  parameter  c_has_rfd             = 0  ; //  Memory has ready for data pin
+  parameter  c_has_sinit           =  1 ; // indicates memory has a SINIT pin
+  parameter  c_has_we              =  1 ; // indicates memory has a WE pin
+  parameter  c_limit_data_pitch           = 18;
+  parameter  c_mem_init_file       =  "null.mif";  // controls which .mif file used to initialize memory
+  parameter  c_pipe_stages         =  1 ; // indicates the number of pipe stages needed in port A
+  parameter  c_reg_inputs          = 0 ;  // indicates WE, ADDR, and DIN are registered
+  parameter  c_sinit_value         = "0000"; // indicates string of hex used to initialize  output registers
+  parameter  c_width               =  32 ; // controls data width of memory
+  parameter  c_write_mode          =  2; // controls which write modes shall be used
+   
+  parameter  c_ybottom_addr        = "1024";
+  parameter  c_yclk_is_rising      = 1;
+  parameter  c_yen_is_high         = 1;
+  parameter  c_yhierarchy          = "hierarchy1";
+  parameter  c_ymake_bmm           = 1;
+  parameter  c_yprimitive_type     = "4kx4";
+  parameter  c_ysinit_is_high      = 1;
+  parameter  c_ytop_addr           = "0";
+  parameter  c_yuse_single_primitive = 0;
+  parameter  c_ywe_is_high         = 1;
+
+// IO ports
+
+
+  output [c_width-1:0] DOUT;
+  input [c_addr_width-1:0] ADDR;
+  input [c_width-1:0] DIN;
+  input EN, CLK, WE, SINIT, ND;
+  output RFD, RDY;
+
+  reg RFD ;
+  reg RDY ;
+
+  reg [c_width-1:0] dout_int; // output of RAM
+  reg [c_width-1:0] pipe_out ; // output of pipeline stage
+  wire [c_width-1:0] DOUT = pipe_out ;
+  reg [c_depth*c_width-1:0] mem;
+  reg [24:0] count;
+  reg [1:0] wr_mode;
+
+  wire [c_addr_width-1:0] addr_i = ADDR;
+  reg [c_addr_width-1:0] addr_int ;
+  reg [c_width-1:0] di_int ;
+  wire [c_width-1:0] di_i ;
+  wire clk_int ;
+  wire en_int ;
+  reg we_int  ;
+  wire we_i ;
+  reg  we_q ;
+  wire ssr_int  ;
+  wire nd_int ;
+  wire nd_i ;
+  reg rfd_int ;
+  reg rdy_int ;
+  reg nd_q ;
+  reg [c_width-1:0] di_q ;
+  reg [c_addr_width-1:0] addr_q;
+  reg new_data ;
+  reg new_data_q ; // to track the synchronous PORT RAM output 
+
+  reg [c_width-1:0] default_data ;
+  reg [c_width-1:0] ram_temp [0:c_depth-1];
+  reg [c_width-1:0] bitval;
+  reg [c_width-1:0] sinit_value;
+
+  reg [(c_width-1) : 0] pipeline [0 : c_pipe_stages];
+  reg sub_rdy[0 : c_pipe_stages];
+  reg [10:0] ci, cj ;
+  reg [10:0] dmi, dmj, dni, dnj, doi, doj ;
+  integer i, j, k, l, m;
+  integer ai, aj, ak, al, am, an, ap ;
+
+
+// Generate input control signals
+// Combinational 
+
+// Take care of ROM/RAM functionality
+
+  assign clk_int = defval(CLK, 1, 1, c_yclk_is_rising);
+  assign we_i = defval(WE, c_has_we, 0, c_ywe_is_high);  
+  assign di_i  = (c_has_din == 1)?DIN:'b0;
+  assign en_int  = defval(EN, c_has_en, 1, c_yen_is_high);
+  assign ssr_int = defval(SINIT , c_has_sinit , 0, c_ysinit_is_high);
+  assign nd_i = defval (ND, c_has_nd, 1, 1);
+
+
+//    tri0 GSR = glbl.GSR;
+
+  function defval;
+    input i;
+    input hassig;
+    input val;  
+    input active_high;
+  begin
+    if(hassig == 1)
+    begin
+      if (active_high == 1)
+        defval = i;
+      else
+        defval = ~i;
+    end
+    else
+      defval = val;
+  end
+  endfunction
+
+  function max;
+    input a;  
+    input b;
+  begin
+    max = (a > b) ? a : b;
+  end
+  endfunction
+ 
+  function a_is_X;
+    input [c_width-1 : 0] i;
+    integer j ;
+  begin
+    a_is_X = 1'b0;
+    for(j = 0; j < c_width; j = j + 1)
+    begin
+      if(i[j] === 1'bx)
+        a_is_X = 1'b1;
+    end // loop
+  end
+  endfunction
+
+
+  function [c_width-1:0] hexstr_conv;
+    input [(c_width*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;   
+
+  begin
+    index = 0; 
+    hexstr_conv = 'b0; 
+    for( i=c_width-1; i>=0; i=i-1 )
+    begin
+      case (def_data[7:0])
+        8'b00000000 :  
+      begin
+        bin = 4'b0000;
+        i = -1;
+      end
+      8'b00110000 : bin = 4'b0000;
+      8'b00110001 : bin = 4'b0001;
+      8'b00110010 : bin = 4'b0010;
+      8'b00110011 : bin = 4'b0011;
+      8'b00110100 : bin = 4'b0100;
+      8'b00110101 : bin = 4'b0101;
+      8'b00110110 : bin = 4'b0110;
+      8'b00110111 : bin = 4'b0111;
+      8'b00111000 : bin = 4'b1000;
+      8'b00111001 : bin = 4'b1001;
+      8'b01000001 : bin = 4'b1010;
+      8'b01000010 : bin = 4'b1011;
+      8'b01000011 : bin = 4'b1100;
+      8'b01000100 : bin = 4'b1101;
+      8'b01000101 : bin = 4'b1110;
+      8'b01000110 : bin = 4'b1111;
+      8'b01100001 : bin = 4'b1010;
+      8'b01100010 : bin = 4'b1011;
+      8'b01100011 : bin = 4'b1100;
+      8'b01100100 : bin = 4'b1101;
+      8'b01100101 : bin = 4'b1110;
+      8'b01100110 : bin = 4'b1111;
+      default :
+        begin
+          $display("ERROR in %m at time %t : NOT A HEX CHARACTER",$time);
+          bin = 4'bx;
+        end
+      endcase
+      for( j=0; j<4; j=j+1)
+      begin
+        if ((index*4)+j < c_width)
+        begin
+          hexstr_conv[(index*4)+j] = bin[j];
+        end 
+      end
+      index = index + 1;
+      def_data = def_data >> 8;
+    end
+  end
+  endfunction
+
+
+//  Initialize memory contents to default_data for now . In future, read from .mif file and initialize the content properly
+
+  initial begin
+    sinit_value  = 'b0 ;
+    default_data = hexstr_conv(c_default_data);
+    if (c_has_sinit == 1 )
+      sinit_value = hexstr_conv(c_sinit_value);
+    for(i = 0; i < c_depth; i = i + 1)
+      ram_temp[i] = default_data;
+    if (c_has_default_data == 0)
+      $readmemb(c_mem_init_file, ram_temp);
+    for(i = 0; i < c_depth; i = i + 1)
+      for(j = 0; j < c_width; j = j + 1)
+      begin
+        bitval = (1'b1 << j);
+        mem[(i*c_width) + j] = (ram_temp[i] & bitval) >> j;
+      end
+      for (k = 0; k <= c_pipe_stages; k = k + 1)
+        pipeline[k] = sinit_value ;
+      for (m = 0; m <= c_pipe_stages; m = m + 1)
+        sub_rdy[m] = 0 ;
+      pipe_out = sinit_value ;
+      dout_int = sinit_value ;
+      nd_q = 0 ;
+      new_data_q = 0 ;
+      di_q = 0 ;
+      addr_q = 0 ;
+      we_q = 0 ;
+    end
+
+//  Generate output control signals RFD and  RDY 
+//  Combinational
+
+    always @ ( rfd_int)
+    begin
+      if (c_has_rfd == 1) 
+        RFD = rfd_int ;
+      else
+        RFD = 1'b0 ;
+    end
+
+    always @ (en_int )
+    begin
+      if (en_int == 1'b1)
+        rfd_int = 1'b1 ;
+      else
+        rfd_int = 1'b0 ;
+    end
+
+    always @ (  rdy_int )
+    begin
+      if ((c_has_rdy == 1) && (c_has_nd == 1) && (c_has_rfd == 1) )
+        RDY = rdy_int ;
+      else
+        RDY = 1'b0 ;
+    end
+
+    assign nd_int = en_int && nd_i ; // only pass nd through if en is 1 
+
+// Register hanshaking inputs
+
+    always @(posedge clk_int )
+    begin
+      if (en_int == 1'b1)
+      begin
+        if (ssr_int == 1'b1)
+          nd_q <= 1'b0 ;
+        else
+          nd_q   <= nd_int;
+        end
+      else
+        nd_q   <= nd_q ;
+    end
+// Register data / address / data inputs
+
+  always @(posedge clk_int )
+  begin
+    if (en_int == 1'b1)
+      begin
+        di_q  <= di_i ;
+        addr_q <= addr_i ;
+        we_q <= we_i ;
+      end
+  end
+
+// Register en input 
+
+// always @(posedge clk_int )
+// begin
+//      en_q <= en_i ;
+// end
+
+// Select registered or non-registered en signal
+
+// always @( en_i or en_q)
+// begin
+//    if (c_reg_en == 1)
+//       en_int = en_q ;
+//    else
+//       en_int = en_i ;
+// end
+
+// select registered or non-registered write enable
+
+  always @( we_i or we_q)
+  begin
+    if (c_reg_inputs == 1 )
+      we_int = we_q ;
+     else
+      we_int = we_i ;
+  end
+
+// select registered data/address/nd inputs
+
+  always @( di_i or di_q)
+  begin
+    if ( c_reg_inputs == 1)
+      di_int = di_q ;
+    else
+      di_int = di_i ;
+  end
+
+  always @( addr_i or addr_q or nd_q or nd_int )
+  begin
+    if (c_reg_inputs == 1)
+      begin
+        addr_int = addr_q;
+        new_data = nd_q ;
+      end
+    else
+      begin
+        addr_int = addr_i ;
+        new_data = nd_int ;
+      end
+  end
+
+// Register the new_data signal to track the synchronous RAM output
+
+  always @(posedge clk_int)
+  begin
+    if ( en_int == 1'b1 )
+      begin
+       if (ssr_int == 1'b1)
+          new_data_q <= 0 ;
+       else
+          new_data_q <= new_data ;
+      end
+  end
+
+//  Ininitialize A and B outputs for INIT_A and INIT_B when GSR asserted .
+ 
+//    always @(GSR)
+//        if (GSR) begin
+//            assign dout_int = INIT[c_width-1:0];
+//        end
+//        else begin
+//            deassign dout_int;
+//        end
+
+   initial begin
+     case (c_write_mode)
+       `c_write_first : wr_mode <= 2'b00;
+       `c_read_first  : wr_mode <= 2'b01;
+       `c_no_change   : wr_mode <= 2'b10;
+       default        : begin
+	 $display("Error in %m at time %t: c_write_mode = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time , c_write_mode);
+	 $finish;
+       end
+     endcase
+   end
+
+
+    /***************************************************************
+    *The following always block assigns the value for the DOUT bus
+    ***************************************************************/   
+   always @(posedge clk_int) begin
+     if (en_int == 1'b1) begin
+       if (ssr_int == 1'b1) begin
+         for ( ai = 0; ai < c_width; ai = ai + 1)
+           dout_int[ai] <= sinit_value[ai];
+       end
+       else begin
+	 //The following IF block assigns the output for a write operation
+         if (we_int == 1'b1) begin
+           if (wr_mode == 2'b00) begin
+             if (addr_int < c_depth) 
+               for (aj = 0; aj < c_width; aj = aj + 1)
+                 dout_int[aj] <= di_int[aj];
+             else
+	       //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "Write First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+	       $display("Invalid Address Warning #1: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);    
+           end
+           else if (wr_mode == 2'b01) begin
+             if (addr_int < c_depth) 
+               for (ak = 0; ak < c_width; ak = ak + 1 )
+                 dout_int[ak] <= mem[(addr_int*c_width) + ak];
+             else
+	       //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "Read First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+	      $display("Invalid Address Warning #2: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+           end
+           else begin
+             if (addr_int < c_depth) 
+               dout_int <= dout_int ;
+             else
+	      //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "No Change" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+	      $display("Invalid Address Warning #3: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+           end
+	 end
+	 //The following ELSE block assigns the output for a read operation
+	 else begin
+           if (addr_int < c_depth) 
+             for ( al = 0; al < c_width; al = al + 1)
+               dout_int[al] <= mem[(addr_int*c_width) + al];
+           else
+             //Warning Condition (Error occurs on rising edge of CLK): 
+	     //EN = 1 and SINIT = 0 and WE = 0 and ADDRA out of the valid range 
+	    $display("Invalid Address Warning #4: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+	 end
+       end
+     end
+   end
+
+
+// Write to memory contents
+    /***************************************************************************************
+    *The following always block assigns the DIN bus to the memory during a write operation
+    ***************************************************************************************/ 
+   always @(posedge clk_int) begin
+     if (en_int == 1'b1 && we_int == 1'b1) begin
+       if (addr_int < c_depth) 
+         for (am = 0; am < c_width; am = am + 1 )
+           mem [(addr_int*c_width) + am] <= di_int[am] ;
+       else
+	 //Warning Condition (Error occurs on rising edge of CLK): 
+	 //EN = 1 and WE = 1 and ADDR out of the valid range
+	$display("Invalid Address Warning #5: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+     end
+   end
+
+//  output pipelines 
+ 
+   always @(posedge clk_int) begin
+      if (en_int == 1'b1 && c_pipe_stages > 0)
+	begin
+           for (i = c_pipe_stages; i >= 1; i = i -1 )
+             begin
+		if (ssr_int == 1'b1 && en_int == 1'b1)
+		  begin
+		     pipeline[i] <= sinit_value ;
+		     sub_rdy[i] <=  0 ;
+		  end
+		else
+		  begin
+		     if (i==1)
+		       begin
+			  pipeline[1] <= dout_int;
+			  sub_rdy[1]  <= new_data_q;
+		       end
+		     else
+		       begin
+			  pipeline[i] <= pipeline[i-1] ;
+			  sub_rdy[i]  <= sub_rdy[i-1] ;
+		       end
+		  end
+             end
+	end
+   end
+
+// Select pipelined data output or no-pipelined data output
+ 
+   always @( pipeline[c_pipe_stages] or dout_int or new_data_q or sub_rdy[c_pipe_stages]) begin
+     if (c_pipe_stages == 0 )
+     begin
+       pipe_out = dout_int ;
+       rdy_int = new_data_q ;
+     end
+     else
+     begin
+       pipe_out = pipeline[c_pipe_stages];
+       rdy_int = sub_rdy[c_pipe_stages];
+     end
+   end
+
+
+ //   specify
+// (CLK *> DOUT) = (1, 1);
+//   endspecify
+
+endmodule
+
+`endcelldefine

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V5_0.v

@@ -0,0 +1,488 @@
+/*****************************************************************************
+ * $RCSfile: BLKMEMSP_V5_0.v,v $$Date: 2008/09/08 20:06:36 $
+ *****************************************************************************
+ * Block Memory Compiler - Verilog Behavioral Model
+ *****************************************************************************
+ *
+ * This File is owned and controlled by Xilinx and must be used solely  
+ * for design, simulation, implementation and creation of design files   
+ * limited to Xilinx devices or technologies. Use with non-Xilinx       
+ * devices or technologies is expressly prohibited and immediately      
+ * terminates your license.                                             
+ *                                                                      
+ * Xilinx products are not intended for use in life support             
+ * appliances, devices, or systems. Use in such applications is          
+ * expressly prohibited.
+ * 
+ *        ****************************
+ *        ** Copyright Xilinx, Inc. **
+ *        ** All rights reserved.   **
+ *        ****************************
+ *
+ *************************************************************************
+ * Filename:   BLKMEMSP_V5_0.v
+ *
+ * Decsription: Single Port V2 BRAM behavioral model. Extendable depth/width.
+ *              The behavior for EN = `X`, WE = `X`, and for CLK transitions to
+ *              or from `X` is not considered.
+ *
+ **************************************************************************/
+`timescale 1ns/10ps
+
+`celldefine
+
+
+`define c_sp_rom 0
+`define c_sp_ram 1
+`define c_write_first 0
+`define c_read_first  1
+`define c_no_change   2
+
+module BLKMEMSP_V5_0(DOUT,  ADDR, DIN,  EN, CLK, WE, SINIT, ND, RFD, RDY);
+
+  parameter  c_addr_width          =  9 ; // controls address width of memory
+  parameter  c_default_data        = "0"; // indicates string of hex characters used to initialize memory
+  parameter  c_depth               = 512 ; // controls depth of memory
+  parameter  c_enable_rlocs        = 0 ; //  core includes placement constraints
+  parameter  c_has_default_data    =  1; // initializes contents of memory to c_default_data
+  parameter  c_has_din             = 1  ; // indicates memory has data input pins
+  parameter  c_has_en              =  1 ; // indicates memory has a EN pin
+  parameter  c_has_limit_data_pitch       = 0  ; //  
+  parameter  c_has_nd              = 0  ; //  Memory has a new data pin
+  parameter  c_has_rdy             = 0  ; //  Memory has result ready pin
+  parameter  c_has_rfd             = 0  ; //  Memory has ready for data pin
+  parameter  c_has_sinit           =  1 ; // indicates memory has a SINIT pin
+  parameter  c_has_we              =  1 ; // indicates memory has a WE pin
+  parameter  c_limit_data_pitch           = 18;
+  parameter  c_mem_init_file       =  "null.mif";  // controls which .mif file used to initialize memory
+  parameter  c_pipe_stages         =  1 ; // indicates the number of pipe stages needed in port A
+  parameter  c_reg_inputs          = 0 ;  // indicates WE, ADDR, and DIN are registered
+  parameter  c_sinit_value         = "0000"; // indicates string of hex used to initialize  output registers
+  parameter  c_width               =  32 ; // controls data width of memory
+  parameter  c_write_mode          =  2; // controls which write modes shall be used
+   
+  parameter  c_ybottom_addr        = "1024";
+  parameter  c_yclk_is_rising      = 1;
+  parameter  c_yen_is_high         = 1;
+  parameter  c_yhierarchy          = "hierarchy1";
+  parameter  c_ymake_bmm           = 1;
+  parameter  c_yprimitive_type     = "4kx4";
+  parameter  c_ysinit_is_high      = 1;
+  parameter  c_ytop_addr           = "0";
+  parameter  c_yuse_single_primitive = 0;
+  parameter  c_ywe_is_high         = 1;
+
+// IO ports
+
+
+  output [c_width-1:0] DOUT;
+  input [c_addr_width-1:0] ADDR;
+  input [c_width-1:0] DIN;
+  input EN, CLK, WE, SINIT, ND;
+  output RFD, RDY;
+
+  reg RFD ;
+  reg RDY ;
+
+  reg [c_width-1:0] dout_int; // output of RAM
+  reg [c_width-1:0] pipe_out ; // output of pipeline stage
+  wire [c_width-1:0] DOUT = pipe_out ;
+  reg [c_width-1:0] mem [0:c_depth-1];
+  reg [24:0] count;
+  reg [1:0] wr_mode;
+
+  wire [c_addr_width-1:0] addr_i = ADDR;
+  reg [c_addr_width-1:0] addr_int ;
+  reg [c_width-1:0] di_int ;
+  wire [c_width-1:0] di_i ;
+  wire clk_int ;
+  wire en_int ;
+  reg we_int  ;
+  wire we_i ;
+  reg  we_q ;
+  wire ssr_int  ;
+  wire nd_int ;
+  wire nd_i ;
+  reg rfd_int ;
+  reg rdy_int ;
+  reg nd_q ;
+  reg [c_width-1:0] di_q ;
+  reg [c_addr_width-1:0] addr_q;
+  reg new_data ;
+  reg new_data_q ; // to track the synchronous PORT RAM output 
+
+  reg [c_width-1:0] default_data ;
+  reg [c_width-1:0] ram_temp [0:c_depth-1];
+  reg [c_width-1:0] bitval;
+  reg [c_width-1:0] sinit_value;
+
+  reg [(c_width-1) : 0] pipeline [0 : c_pipe_stages];
+  reg sub_rdy[0 : c_pipe_stages];
+  reg [10:0] ci, cj ;
+  reg [10:0] dmi, dmj, dni, dnj, doi, doj ;
+  integer i, j, k, l, m;
+  integer ai, aj, ak, al, am, an, ap ;
+
+
+// Generate input control signals
+// Combinational 
+
+// Take care of ROM/RAM functionality
+
+  assign clk_int = defval(CLK, 1, 1, c_yclk_is_rising);
+  assign we_i = defval(WE, c_has_we, 0, c_ywe_is_high);  
+  assign di_i  = (c_has_din == 1)?DIN:'b0;
+  assign en_int  = defval(EN, c_has_en, 1, c_yen_is_high);
+  assign ssr_int = defval(SINIT , c_has_sinit , 0, c_ysinit_is_high);
+  assign nd_i = defval (ND, c_has_nd, 1, 1);
+
+
+//    tri0 GSR = glbl.GSR;
+
+  function defval;
+    input i;
+    input hassig;
+    input val;  
+    input active_high;
+  begin
+    if(hassig == 1)
+    begin
+      if (active_high == 1)
+        defval = i;
+      else
+        defval = ~i;
+    end
+    else
+      defval = val;
+  end
+  endfunction
+
+  function max;
+    input a;  
+    input b;
+  begin
+    max = (a > b) ? a : b;
+  end
+  endfunction
+ 
+  function a_is_X;
+    input [c_width-1 : 0] i;
+    integer j ;
+  begin
+    a_is_X = 1'b0;
+    for(j = 0; j < c_width; j = j + 1)
+    begin
+      if(i[j] === 1'bx)
+        a_is_X = 1'b1;
+    end // loop
+  end
+  endfunction
+
+
+  function [c_width-1:0] hexstr_conv;
+    input [(c_width*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;   
+
+  begin
+    index = 0; 
+    hexstr_conv = 'b0; 
+    for( i=c_width-1; i>=0; i=i-1 )
+    begin
+      case (def_data[7:0])
+        8'b00000000 :  
+      begin
+        bin = 4'b0000;
+        i = -1;
+      end
+      8'b00110000 : bin = 4'b0000;
+      8'b00110001 : bin = 4'b0001;
+      8'b00110010 : bin = 4'b0010;
+      8'b00110011 : bin = 4'b0011;
+      8'b00110100 : bin = 4'b0100;
+      8'b00110101 : bin = 4'b0101;
+      8'b00110110 : bin = 4'b0110;
+      8'b00110111 : bin = 4'b0111;
+      8'b00111000 : bin = 4'b1000;
+      8'b00111001 : bin = 4'b1001;
+      8'b01000001 : bin = 4'b1010;
+      8'b01000010 : bin = 4'b1011;
+      8'b01000011 : bin = 4'b1100;
+      8'b01000100 : bin = 4'b1101;
+      8'b01000101 : bin = 4'b1110;
+      8'b01000110 : bin = 4'b1111;
+      8'b01100001 : bin = 4'b1010;
+      8'b01100010 : bin = 4'b1011;
+      8'b01100011 : bin = 4'b1100;
+      8'b01100100 : bin = 4'b1101;
+      8'b01100101 : bin = 4'b1110;
+      8'b01100110 : bin = 4'b1111;
+      default :
+        begin
+          $display("ERROR in %m at time %t : NOT A HEX CHARACTER",$time);
+          bin = 4'bx;
+        end
+      endcase
+      for( j=0; j<4; j=j+1)
+      begin
+        if ((index*4)+j < c_width)
+        begin
+          hexstr_conv[(index*4)+j] = bin[j];
+        end 
+      end
+      index = index + 1;
+      def_data = def_data >> 8;
+    end
+  end
+  endfunction
+
+  initial begin
+    sinit_value  = 'b0 ;
+    default_data = hexstr_conv(c_default_data);
+    if (c_has_sinit == 1 )
+      sinit_value = hexstr_conv(c_sinit_value);
+    for(i = 0; i < c_depth; i = i + 1)
+      mem[i] = default_data;
+    if (c_has_default_data == 0)
+      $readmemb(c_mem_init_file, mem);
+    for (k = 0; k <= c_pipe_stages; k = k + 1)
+      pipeline[k] = sinit_value ;
+    for (m = 0; m <= c_pipe_stages; m = m + 1)
+      sub_rdy[m] = 0 ;
+    dout_int = sinit_value ;
+    nd_q = 0 ;
+    new_data_q = 0 ;
+    di_q = 0 ;
+    addr_q = 0 ;
+    we_q = 0 ;
+    #1 pipe_out = sinit_value;
+  end
+
+//  Generate output control signals RFD and  RDY 
+//  Combinational
+
+    always @ ( rfd_int)
+    begin
+      if (c_has_rfd == 1) 
+        RFD = rfd_int ;
+      else
+        RFD = 1'b0 ;
+    end
+
+    always @ (en_int )
+    begin
+      if (en_int == 1'b1)
+        rfd_int = 1'b1 ;
+      else
+        rfd_int = 1'b0 ;
+    end
+
+    always @ (  rdy_int )
+    begin
+      if ((c_has_rdy == 1) && (c_has_nd == 1) && (c_has_rfd == 1) )
+        RDY = rdy_int ;
+      else
+        RDY = 1'b0 ;
+    end
+
+    assign nd_int = en_int && nd_i ; // only pass nd through if en is 1 
+
+// Register hanshaking inputs
+
+    always @(posedge clk_int )
+    begin
+      if (en_int == 1'b1)
+      begin
+        if (ssr_int == 1'b1)
+          nd_q <= 1'b0 ;
+        else
+          nd_q   <= nd_int;
+        end
+      else
+        nd_q   <= nd_q ;
+    end
+// Register data / address / data inputs
+
+  always @(posedge clk_int )
+  begin
+    if (en_int == 1'b1)
+      begin
+        di_q  <= di_i ;
+        addr_q <= addr_i ;
+        we_q <= we_i ;
+      end
+  end
+
+// select registered or non-registered write enable
+
+  always @( we_i or we_q)
+  begin
+    if (c_reg_inputs == 1 )
+      we_int = we_q ;
+     else
+      we_int = we_i ;
+  end
+
+// select registered data/address/nd inputs
+
+  always @( di_i or di_q)
+  begin
+    if ( c_reg_inputs == 1)
+      di_int = di_q ;
+    else
+      di_int = di_i ;
+  end
+
+  always @( addr_i or addr_q or nd_q or nd_int )
+  begin
+    if (c_reg_inputs == 1)
+      begin
+        addr_int = addr_q;
+        new_data = nd_q ;
+      end
+    else
+      begin
+        addr_int = addr_i ;
+        new_data = nd_int ;
+      end
+  end
+
+// Register the new_data signal to track the synchronous RAM output
+
+  always @(posedge clk_int)
+  begin
+    if ( en_int == 1'b1 )
+      begin
+       if (ssr_int == 1'b1)
+          new_data_q <= 0 ;
+       else
+          new_data_q <= new_data ;
+      end
+  end
+
+   initial begin
+     case (c_write_mode)
+       `c_write_first : wr_mode <= 2'b00;
+       `c_read_first  : wr_mode <= 2'b01;
+       `c_no_change   : wr_mode <= 2'b10;
+       default        : begin
+	 $display("Error in %m at time %t: c_write_mode = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time , c_write_mode);
+	 $finish;
+       end
+     endcase
+   end
+
+
+    /***************************************************************
+    *The following always block assigns the value for the DOUT bus
+    ***************************************************************/   
+   always @(posedge clk_int) begin
+     if (en_int == 1'b1) begin
+       if (ssr_int == 1'b1) begin
+           dout_int <= sinit_value;
+       end
+       else begin
+	 //The following IF block assigns the output for a write operation
+         if (we_int == 1'b1) begin
+           if (wr_mode == 2'b00) begin
+             if (addr_int < c_depth) 
+                 dout_int <= di_int;
+             else
+	       //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "Write First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+	       $display("Invalid Address Warning #1: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);    
+           end
+           else if (wr_mode == 2'b01) begin
+             if (addr_int < c_depth) 
+               dout_int <= mem[addr_int];
+             else
+	       //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "Read First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+	      $display("Invalid Address Warning #2: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+           end
+           else begin
+             if (addr_int < c_depth) 
+               dout_int <= dout_int ;
+             else
+	      //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "No Change" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+	      $display("Invalid Address Warning #3: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+           end
+	 end
+	 //The following ELSE block assigns the output for a read operation
+	 else begin
+           if (addr_int < c_depth) 
+             dout_int <= mem[addr_int];
+           else
+             //Warning Condition (Error occurs on rising edge of CLK): 
+	     //EN = 1 and SINIT = 0 and WE = 0 and ADDRA out of the valid range 
+	    $display("Invalid Address Warning #4: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+	 end
+       end
+     end
+   end
+
+
+// Write to memory contents
+    /***************************************************************************************
+    *The following always block assigns the DIN bus to the memory during a write operation
+    ***************************************************************************************/ 
+   always @(posedge clk_int) begin
+     if (en_int == 1'b1 && we_int == 1'b1) begin
+       if (addr_int < c_depth) 
+         mem [addr_int] <= di_int ;
+       else
+	 //Warning Condition (Error occurs on rising edge of CLK): 
+	 //EN = 1 and WE = 1 and ADDR out of the valid range
+	$display("Invalid Address Warning #5: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+     end
+   end
+
+//  output pipelines 
+ 
+   always @(posedge clk_int) begin
+      if (en_int == 1'b1 && c_pipe_stages > 0)
+	begin
+           for (i = c_pipe_stages; i >= 1; i = i -1 )
+             begin
+		if (ssr_int == 1'b1 && en_int == 1'b1)
+		  begin
+		     pipeline[i] <= sinit_value ;
+		     sub_rdy[i] <=  0 ;
+		  end
+		else
+		  begin
+		     if (i==1)
+		       begin
+			  pipeline[i] <= dout_int;
+			  sub_rdy[i]  <= new_data_q;
+		       end
+		     else
+		       begin
+			  pipeline[i] <= pipeline[i-1] ;
+			  sub_rdy[i]  <= sub_rdy[i-1] ;
+		       end
+		  end
+             end
+	end
+   end
+
+// Select pipelined data output or no-pipelined data output
+ 
+   always @( pipeline[c_pipe_stages] or sub_rdy[c_pipe_stages] or new_data_q or dout_int) begin
+     if (c_pipe_stages == 0 )
+     begin
+       pipe_out = dout_int ;
+       rdy_int = new_data_q ;
+     end
+     else
+     begin
+       rdy_int = sub_rdy[c_pipe_stages];
+       pipe_out = pipeline[c_pipe_stages];
+     end
+   end
+
+endmodule
+
+`endcelldefine

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V6_0.v

@@ -0,0 +1,542 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+/*****************************************************************************
+ * $RCSfile: BLKMEMSP_V6_0.v,v $$Date: 2008/09/08 20:06:40 $
+ *****************************************************************************
+ * Block Memory Compiler - Verilog Behavioral Model
+ *****************************************************************************
+ *
+ *
+ *************************************************************************
+ * Filename:   BLKMEMSP_V6_0.v
+ *
+ * Decsription: Single Port V2 BRAM behavioral model. Extendable depth/width.
+ *              The behavior for EN = `X`, WE = `X`, and for CLK transitions to
+ *              or from `X` is not considered.
+ *
+ **************************************************************************/
+`timescale 1ns/10ps
+
+`celldefine
+
+
+`define c_sp_rom 0
+`define c_sp_ram 1
+`define c_write_first 0
+`define c_read_first  1
+`define c_no_change   2
+
+module BLKMEMSP_V6_0(DOUT,  ADDR, DIN,  EN, CLK, WE, SINIT, ND, RFD, RDY);
+
+  parameter  c_addr_width          =  9 ; // controls address width of memory
+  parameter  c_default_data        = "0"; // indicates string of hex characters used to initialize memory
+  parameter  c_depth               = 512 ; // controls depth of memory
+  parameter  c_enable_rlocs        = 0 ; //  core includes placement constraints
+  parameter  c_has_default_data    =  1; // initializes contents of memory to c_default_data
+  parameter  c_has_din             = 1  ; // indicates memory has data input pins
+  parameter  c_has_en              =  1 ; // indicates memory has a EN pin
+  parameter  c_has_limit_data_pitch       = 0  ; //  
+  parameter  c_has_nd              = 0  ; //  Memory has a new data pin
+  parameter  c_has_rdy             = 0  ; //  Memory has result ready pin
+  parameter  c_has_rfd             = 0  ; //  Memory has ready for data pin
+  parameter  c_has_sinit           =  1 ; // indicates memory has a SINIT pin
+  parameter  c_has_we              =  1 ; // indicates memory has a WE pin
+  parameter  c_limit_data_pitch           = 18;
+  parameter  c_mem_init_file       =  "null.mif";  // controls which .mif file used to initialize memory
+  parameter  c_pipe_stages         =  1 ; // indicates the number of pipe stages needed in port A
+  parameter  c_reg_inputs          = 0 ;  // indicates WE, ADDR, and DIN are registered
+  parameter  c_sinit_value         = "0000"; // indicates string of hex used to initialize  output registers
+  parameter  c_width               =  32 ; // controls data width of memory
+  parameter  c_write_mode          =  2; // controls which write modes shall be used
+   
+  parameter  c_ybottom_addr        = "1024";
+  parameter  c_yclk_is_rising      = 1;
+  parameter  c_yen_is_high         = 1;
+  parameter  c_yhierarchy          = "hierarchy1";
+  parameter  c_ymake_bmm           = 1;
+  parameter  c_yprimitive_type     = "4kx4";
+  parameter  c_ysinit_is_high      = 1;
+  parameter  c_ytop_addr           = "0";
+  parameter  c_yuse_single_primitive = 0;
+  parameter  c_ywe_is_high         = 1;
+ parameter   c_yydisable_warnings  = 0;
+ 
+
+// IO ports
+
+
+  output [c_width-1:0] DOUT;
+  input [c_addr_width-1:0] ADDR;
+  input [c_width-1:0] DIN;
+  input EN, CLK, WE, SINIT, ND;
+  output RFD, RDY;
+
+  reg RFD ;
+  reg RDY ;
+
+  reg [c_width-1:0] dout_int; // output of RAM
+  reg [c_width-1:0] pipe_out ; // output of pipeline stage
+  wire [c_width-1:0] DOUT = pipe_out ;
+  reg [c_width-1:0] mem [0:c_depth-1];
+  reg [24:0] count;
+  reg [1:0] wr_mode;
+
+  wire [c_addr_width-1:0] addr_i = ADDR;
+  reg [c_addr_width-1:0] addr_int ;
+  reg [c_width-1:0] di_int ;
+  wire [c_width-1:0] di_i ;
+  wire clk_int ;
+  wire en_int ;
+  reg we_int  ;
+  wire we_i ;
+  reg  we_q ;
+  wire ssr_int  ;
+  wire nd_int ;
+  wire nd_i ;
+  reg rfd_int ;
+  reg rdy_int ;
+  reg nd_q ;
+  reg [c_width-1:0] di_q ;
+  reg [c_addr_width-1:0] addr_q;
+  reg new_data ;
+  reg new_data_q ; // to track the synchronous PORT RAM output 
+
+  reg [c_width-1:0] default_data ;
+  reg [c_width-1:0] ram_temp [0:c_depth-1];
+  reg [c_width-1:0] bitval;
+  reg [c_width-1:0] sinit_value;
+
+  reg [(c_width-1) : 0] pipeline [0 : c_pipe_stages];
+  reg sub_rdy[0 : c_pipe_stages];
+  reg [10:0] ci, cj ;
+  reg [10:0] dmi, dmj, dni, dnj, doi, doj ;
+  integer i, j, k, l, m;
+  integer ai, aj, ak, al, am, an, ap ;
+
+
+// Generate input control signals
+// Combinational 
+
+// Take care of ROM/RAM functionality
+
+  assign clk_int = defval(CLK, 1, 1, c_yclk_is_rising);
+  assign we_i = defval(WE, c_has_we, 0, c_ywe_is_high);  
+  assign di_i  = (c_has_din == 1)?DIN:'b0;
+  assign en_int  = defval(EN, c_has_en, 1, c_yen_is_high);
+  assign ssr_int = defval(SINIT , c_has_sinit , 0, c_ysinit_is_high);
+  assign nd_i = defval (ND, c_has_nd, 1, 1);
+
+
+//    tri0 GSR = glbl.GSR;
+
+  function defval;
+    input i;
+    input hassig;
+    input val;  
+    input active_high;
+  begin
+    if(hassig == 1)
+    begin
+      if (active_high == 1)
+        defval = i;
+      else
+        defval = ~i;
+    end
+    else
+      defval = val;
+  end
+  endfunction
+
+  function max;
+    input a;  
+    input b;
+  begin
+    max = (a > b) ? a : b;
+  end
+  endfunction
+ 
+  function a_is_X;
+    input [c_width-1 : 0] i;
+    integer j ;
+  begin
+    a_is_X = 1'b0;
+    for(j = 0; j < c_width; j = j + 1)
+    begin
+      if(i[j] === 1'bx)
+        a_is_X = 1'b1;
+    end // loop
+  end
+  endfunction
+
+
+  function [c_width-1:0] hexstr_conv;
+    input [(c_width*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;   
+
+  begin
+    index = 0; 
+    hexstr_conv = 'b0; 
+    for( i=c_width-1; i>=0; i=i-1 )
+    begin
+      case (def_data[7:0])
+        8'b00000000 :  
+      begin
+        bin = 4'b0000;
+        i = -1;
+      end
+      8'b00110000 : bin = 4'b0000;
+      8'b00110001 : bin = 4'b0001;
+      8'b00110010 : bin = 4'b0010;
+      8'b00110011 : bin = 4'b0011;
+      8'b00110100 : bin = 4'b0100;
+      8'b00110101 : bin = 4'b0101;
+      8'b00110110 : bin = 4'b0110;
+      8'b00110111 : bin = 4'b0111;
+      8'b00111000 : bin = 4'b1000;
+      8'b00111001 : bin = 4'b1001;
+      8'b01000001 : bin = 4'b1010;
+      8'b01000010 : bin = 4'b1011;
+      8'b01000011 : bin = 4'b1100;
+      8'b01000100 : bin = 4'b1101;
+      8'b01000101 : bin = 4'b1110;
+      8'b01000110 : bin = 4'b1111;
+      8'b01100001 : bin = 4'b1010;
+      8'b01100010 : bin = 4'b1011;
+      8'b01100011 : bin = 4'b1100;
+      8'b01100100 : bin = 4'b1101;
+      8'b01100101 : bin = 4'b1110;
+      8'b01100110 : bin = 4'b1111;
+      default :
+        begin
+          if (c_yydisable_warnings == 0) begin
+            $display("ERROR in %m at time %t : NOT A HEX CHARACTER",$time);
+          end
+          bin = 4'bx;
+        end
+      endcase
+      for( j=0; j<4; j=j+1)
+      begin
+        if ((index*4)+j < c_width)
+        begin
+          hexstr_conv[(index*4)+j] = bin[j];
+        end 
+      end
+      index = index + 1;
+      def_data = def_data >> 8;
+    end
+  end
+  endfunction
+
+  initial begin
+    sinit_value  = 'b0 ;
+    default_data = hexstr_conv(c_default_data);
+    if (c_has_sinit == 1 )
+      sinit_value = hexstr_conv(c_sinit_value);
+    for(i = 0; i < c_depth; i = i + 1)
+      mem[i] = default_data;
+    if (c_has_default_data == 0)
+      $readmemb(c_mem_init_file, mem);
+    for (k = 0; k <= c_pipe_stages; k = k + 1)
+      pipeline[k] = sinit_value ;
+    for (m = 0; m <= c_pipe_stages; m = m + 1)
+      sub_rdy[m] = 0 ;
+    dout_int = sinit_value ;
+    nd_q = 0 ;
+    new_data_q = 0 ;
+    di_q = 0 ;
+    addr_q = 0 ;
+    we_q = 0 ;
+    #1 pipe_out = sinit_value;
+  end
+
+//  Generate output control signals RFD and  RDY 
+//  Combinational
+
+    always @ ( rfd_int)
+    begin
+      if (c_has_rfd == 1) 
+        RFD = rfd_int ;
+      else
+        RFD = 1'b0 ;
+    end
+
+    always @ (en_int )
+    begin
+      if (en_int == 1'b1)
+        rfd_int = 1'b1 ;
+      else
+        rfd_int = 1'b0 ;
+    end
+
+    always @ (  rdy_int )
+    begin
+      if ((c_has_rdy == 1) && (c_has_nd == 1) && (c_has_rfd == 1) )
+        RDY = rdy_int ;
+      else
+        RDY = 1'b0 ;
+    end
+
+    assign nd_int = en_int && nd_i ; // only pass nd through if en is 1 
+
+// Register hanshaking inputs
+
+    always @(posedge clk_int )
+    begin
+      if (en_int == 1'b1)
+      begin
+        if (ssr_int == 1'b1)
+          nd_q <= 1'b0 ;
+        else
+          nd_q   <= nd_int;
+        end
+      else
+        nd_q   <= nd_q ;
+    end
+// Register data / address / data inputs
+
+  always @(posedge clk_int )
+  begin
+    if (en_int == 1'b1)
+      begin
+        di_q  <= di_i ;
+        addr_q <= addr_i ;
+        we_q <= we_i ;
+      end
+  end
+
+// select registered or non-registered write enable
+
+  always @( we_i or we_q)
+  begin
+    if (c_reg_inputs == 1 )
+      we_int = we_q ;
+     else
+      we_int = we_i ;
+  end
+
+// select registered data/address/nd inputs
+
+  always @( di_i or di_q)
+  begin
+    if ( c_reg_inputs == 1)
+      di_int = di_q ;
+    else
+      di_int = di_i ;
+  end
+
+  always @( addr_i or addr_q or nd_q or nd_int or we_q or we_i)
+  begin
+    if (c_reg_inputs == 1)
+      begin
+        addr_int = addr_q;
+        if ((we_q == 1'b1) && (c_write_mode == 2))
+          new_data = 1'b0 ;
+       	else     
+          new_data = nd_q ;
+      end
+    else
+      begin
+        addr_int = addr_i ;
+        if ((we_i == 1'b1) && (c_write_mode == 2))
+          new_data = 1'b0 ;
+       	else        
+          new_data = nd_int ;
+      end
+  end
+
+// Register the new_data signal to track the synchronous RAM output
+
+  always @(posedge clk_int)
+  begin
+    if ( en_int == 1'b1 )
+      begin
+       if (ssr_int == 1'b1)
+          new_data_q <= 0 ;
+       else
+          new_data_q <= new_data ;
+      end
+  end
+
+   initial begin
+     case (c_write_mode)
+       `c_write_first : wr_mode <= 2'b00;
+       `c_read_first  : wr_mode <= 2'b01;
+       `c_no_change   : wr_mode <= 2'b10;
+       default        : begin
+         if (c_yydisable_warnings == 0) begin
+	   $display("Error in %m at time %t: c_write_mode = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time , c_write_mode);
+         end
+	 $finish;
+       end
+     endcase
+   end
+
+
+    /***************************************************************
+    *The following always block assigns the value for the DOUT bus
+    ***************************************************************/   
+   always @(posedge clk_int) begin
+     if (en_int == 1'b1) begin
+       if (ssr_int == 1'b1) begin
+           dout_int <= sinit_value;
+       end
+       else begin
+	 //The following IF block assigns the output for a write operation
+         if (we_int == 1'b1) begin
+           if (wr_mode == 2'b00) begin
+             if (addr_int < c_depth) 
+                 dout_int <= di_int;
+             else
+	       //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "Write First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+               if (c_yydisable_warnings == 0) begin
+	         $display("Invalid Address Warning #1: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);    
+               end
+           end
+           else if (wr_mode == 2'b01) begin
+             if (addr_int < c_depth) 
+               dout_int <= mem[addr_int];
+             else
+	       //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "Read First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+              if (c_yydisable_warnings == 0) begin
+	        $display("Invalid Address Warning #2: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+              end
+           end
+           else begin
+             if (addr_int < c_depth) 
+               dout_int <= dout_int ;
+             else
+	      //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "No Change" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+              if (c_yydisable_warnings == 0) begin
+	        $display("Invalid Address Warning #3: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+              end
+           end
+	 end
+	 //The following ELSE block assigns the output for a read operation
+	 else begin
+           if (addr_int < c_depth) 
+             dout_int <= mem[addr_int];
+           else
+             //Warning Condition (Error occurs on rising edge of CLK): 
+	     //EN = 1 and SINIT = 0 and WE = 0 and ADDRA out of the valid range 
+            if (c_yydisable_warnings == 0) begin
+	      $display("Invalid Address Warning #4: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+            end
+	 end
+       end
+     end
+   end
+
+
+// Write to memory contents
+    /***************************************************************************************
+    *The following always block assigns the DIN bus to the memory during a write operation
+    ***************************************************************************************/ 
+   always @(posedge clk_int) begin
+     if (en_int == 1'b1 && we_int == 1'b1) begin
+       if (addr_int < c_depth) 
+         mem [addr_int] <= di_int ;
+       else
+	 //Warning Condition (Error occurs on rising edge of CLK): 
+	 //EN = 1 and WE = 1 and ADDR out of the valid range
+        if (c_yydisable_warnings == 0) begin
+	  $display("Invalid Address Warning #5: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+        end
+     end
+   end
+
+//  output pipelines 
+ 
+   always @(posedge clk_int) begin
+      if (en_int == 1'b1 && c_pipe_stages > 0)
+	begin
+           for (i = c_pipe_stages; i >= 1; i = i -1 )
+             begin
+		if (ssr_int == 1'b1 && en_int == 1'b1)
+		  begin
+		     pipeline[i] <= sinit_value ;
+		     sub_rdy[i] <=  0 ;
+		  end
+		else
+		  begin
+                    // Do not update output register if no_change on write and
+                    // WE = 1
+                    if (!(c_write_mode == 2 && we_int == 1)) begin
+                      if (i==1)
+                        begin
+                          pipeline[i] <= dout_int;
+                        end
+                      else
+                        begin
+                          pipeline[i] <= pipeline[i-1] ;
+                        end
+                    end // if (!(c_write_mode == 2 && we_int == 1))
+                    if (i==1)
+                      begin
+                        sub_rdy[i]  <= new_data_q;
+                      end
+                    else
+                      begin
+                        sub_rdy[i]  <= sub_rdy[i-1] ;
+                      end                    
+                  end
+             end
+        end
+    end
+
+// Select pipelined data output or no-pipelined data output
+ 
+   always @( pipeline[c_pipe_stages] or sub_rdy[c_pipe_stages] or new_data_q or dout_int) begin
+     if (c_pipe_stages == 0 )
+     begin
+       pipe_out = dout_int ;
+       rdy_int = new_data_q ;
+     end
+     else
+     begin
+       rdy_int = sub_rdy[c_pipe_stages];
+       pipe_out = pipeline[c_pipe_stages];
+     end
+   end
+
+endmodule
+
+`endcelldefine

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V6_2.v

@@ -0,0 +1,542 @@
+// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. 
+// All rights reserved.
+
+/*****************************************************************************
+ * $RCSfile: BLKMEMSP_V6_2.v,v $
+ *****************************************************************************
+ * Block Memory Compiler - Verilog Behavioral Model
+ *****************************************************************************
+ *
+ *
+ *************************************************************************
+ * Filename:   BLKMEMSP_V6_2.v
+ *
+ * Decsription: Single Port V2 BRAM behavioral model. Extendable depth/width.
+ *              The behavior for EN = `X`, WE = `X`, and for CLK transitions to
+ *              or from `X` is not considered.
+ *
+ **************************************************************************/
+`timescale 1ns/10ps
+
+`celldefine
+
+
+`define c_sp_rom 0
+`define c_sp_ram 1
+`define c_write_first 0
+`define c_read_first  1
+`define c_no_change   2
+
+module BLKMEMSP_V6_2(DOUT,  ADDR, DIN,  EN, CLK, WE, SINIT, ND, RFD, RDY);
+
+  parameter  c_addr_width          =  9 ; // controls address width of memory
+  parameter  c_default_data        = "0"; // indicates string of hex characters used to initialize memory
+  parameter  c_depth               = 512 ; // controls depth of memory
+  parameter  c_enable_rlocs        = 0 ; //  core includes placement constraints
+  parameter  c_has_default_data    =  1; // initializes contents of memory to c_default_data
+  parameter  c_has_din             = 1  ; // indicates memory has data input pins
+  parameter  c_has_en              =  1 ; // indicates memory has a EN pin
+  parameter  c_has_limit_data_pitch       = 0  ; //  
+  parameter  c_has_nd              = 0  ; //  Memory has a new data pin
+  parameter  c_has_rdy             = 0  ; //  Memory has result ready pin
+  parameter  c_has_rfd             = 0  ; //  Memory has ready for data pin
+  parameter  c_has_sinit           =  1 ; // indicates memory has a SINIT pin
+  parameter  c_has_we              =  1 ; // indicates memory has a WE pin
+  parameter  c_limit_data_pitch           = 18;
+  parameter  c_mem_init_file       =  "null.mif";  // controls which .mif file used to initialize memory
+  parameter  c_pipe_stages         =  1 ; // indicates the number of pipe stages needed in port A
+  parameter  c_reg_inputs          = 0 ;  // indicates WE, ADDR, and DIN are registered
+  parameter  c_sinit_value         = "0000"; // indicates string of hex used to initialize  output registers
+  parameter  c_width               =  32 ; // controls data width of memory
+  parameter  c_write_mode          =  2; // controls which write modes shall be used
+   
+  parameter  c_ybottom_addr        = "1024";
+  parameter  c_yclk_is_rising      = 1;
+  parameter  c_yen_is_high         = 1;
+  parameter  c_yhierarchy          = "hierarchy1";
+  parameter  c_ymake_bmm           = 1;
+  parameter  c_yprimitive_type     = "4kx4";
+  parameter  c_ysinit_is_high      = 1;
+  parameter  c_ytop_addr           = "0";
+  parameter  c_yuse_single_primitive = 0;
+  parameter  c_ywe_is_high         = 1;
+ parameter   c_yydisable_warnings  = 0;
+ 
+
+// IO ports
+
+
+  output [c_width-1:0] DOUT;
+  input [c_addr_width-1:0] ADDR;
+  input [c_width-1:0] DIN;
+  input EN, CLK, WE, SINIT, ND;
+  output RFD, RDY;
+
+  reg RFD ;
+  reg RDY ;
+
+  reg [c_width-1:0] dout_int; // output of RAM
+  reg [c_width-1:0] pipe_out ; // output of pipeline stage
+  wire [c_width-1:0] DOUT = pipe_out ;
+  reg [c_width-1:0] mem [0:c_depth-1];
+  reg [24:0] count;
+  reg [1:0] wr_mode;
+
+  wire [c_addr_width-1:0] addr_i = ADDR;
+  reg [c_addr_width-1:0] addr_int ;
+  reg [c_width-1:0] di_int ;
+  wire [c_width-1:0] di_i ;
+  wire clk_int ;
+  wire en_int ;
+  reg we_int  ;
+  wire we_i ;
+  reg  we_q ;
+  wire ssr_int  ;
+  wire nd_int ;
+  wire nd_i ;
+  reg rfd_int ;
+  reg rdy_int ;
+  reg nd_q ;
+  reg [c_width-1:0] di_q ;
+  reg [c_addr_width-1:0] addr_q;
+  reg new_data ;
+  reg new_data_q ; // to track the synchronous PORT RAM output 
+
+  reg [c_width-1:0] default_data ;
+  reg [c_width-1:0] ram_temp [0:c_depth-1];
+  reg [c_width-1:0] bitval;
+  reg [c_width-1:0] sinit_value;
+
+  reg [(c_width-1) : 0] pipeline [0 : c_pipe_stages];
+  reg sub_rdy[0 : c_pipe_stages];
+  reg [10:0] ci, cj ;
+  reg [10:0] dmi, dmj, dni, dnj, doi, doj ;
+  integer i, j, k, l, m;
+  integer ai, aj, ak, al, am, an, ap ;
+
+
+// Generate input control signals
+// Combinational 
+
+// Take care of ROM/RAM functionality
+
+  assign clk_int = defval(CLK, 1, 1, c_yclk_is_rising);
+  assign we_i = defval(WE, c_has_we, 0, c_ywe_is_high);  
+  assign di_i  = (c_has_din == 1)?DIN:'b0;
+  assign en_int  = defval(EN, c_has_en, 1, c_yen_is_high);
+  assign ssr_int = defval(SINIT , c_has_sinit , 0, c_ysinit_is_high);
+  assign nd_i = defval (ND, c_has_nd, 1, 1);
+
+
+//    tri0 GSR = glbl.GSR;
+
+  function defval;
+    input i;
+    input hassig;
+    input val;  
+    input active_high;
+  begin
+    if(hassig == 1)
+    begin
+      if (active_high == 1)
+        defval = i;
+      else
+        defval = ~i;
+    end
+    else
+      defval = val;
+  end
+  endfunction
+
+  function max;
+    input a;  
+    input b;
+  begin
+    max = (a > b) ? a : b;
+  end
+  endfunction
+ 
+  function a_is_X;
+    input [c_width-1 : 0] i;
+    integer j ;
+  begin
+    a_is_X = 1'b0;
+    for(j = 0; j < c_width; j = j + 1)
+    begin
+      if(i[j] === 1'bx)
+        a_is_X = 1'b1;
+    end // loop
+  end
+  endfunction
+
+
+  function [c_width-1:0] hexstr_conv;
+    input [(c_width*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;   
+
+  begin
+    index = 0; 
+    hexstr_conv = 'b0; 
+    for( i=c_width-1; i>=0; i=i-1 )
+    begin
+      case (def_data[7:0])
+        8'b00000000 :  
+      begin
+        bin = 4'b0000;
+        i = -1;
+      end
+      8'b00110000 : bin = 4'b0000;
+      8'b00110001 : bin = 4'b0001;
+      8'b00110010 : bin = 4'b0010;
+      8'b00110011 : bin = 4'b0011;
+      8'b00110100 : bin = 4'b0100;
+      8'b00110101 : bin = 4'b0101;
+      8'b00110110 : bin = 4'b0110;
+      8'b00110111 : bin = 4'b0111;
+      8'b00111000 : bin = 4'b1000;
+      8'b00111001 : bin = 4'b1001;
+      8'b01000001 : bin = 4'b1010;
+      8'b01000010 : bin = 4'b1011;
+      8'b01000011 : bin = 4'b1100;
+      8'b01000100 : bin = 4'b1101;
+      8'b01000101 : bin = 4'b1110;
+      8'b01000110 : bin = 4'b1111;
+      8'b01100001 : bin = 4'b1010;
+      8'b01100010 : bin = 4'b1011;
+      8'b01100011 : bin = 4'b1100;
+      8'b01100100 : bin = 4'b1101;
+      8'b01100101 : bin = 4'b1110;
+      8'b01100110 : bin = 4'b1111;
+      default :
+        begin
+          if (c_yydisable_warnings == 0) begin
+            $display("ERROR in %m at time %t : NOT A HEX CHARACTER",$time);
+          end
+          bin = 4'bx;
+        end
+      endcase
+      for( j=0; j<4; j=j+1)
+      begin
+        if ((index*4)+j < c_width)
+        begin
+          hexstr_conv[(index*4)+j] = bin[j];
+        end 
+      end
+      index = index + 1;
+      def_data = def_data >> 8;
+    end
+  end
+  endfunction
+
+  initial begin
+    sinit_value  = 'b0 ;
+    default_data = hexstr_conv(c_default_data);
+    if (c_has_sinit == 1 )
+      sinit_value = hexstr_conv(c_sinit_value);
+    for(i = 0; i < c_depth; i = i + 1)
+      mem[i] = default_data;
+    if (c_has_default_data == 0)
+      $readmemb(c_mem_init_file, mem);
+    for (k = 0; k <= c_pipe_stages; k = k + 1)
+      pipeline[k] = sinit_value ;
+    for (m = 0; m <= c_pipe_stages; m = m + 1)
+      sub_rdy[m] = 0 ;
+    dout_int = sinit_value ;
+    nd_q = 0 ;
+    new_data_q = 0 ;
+    di_q = 0 ;
+    addr_q = 0 ;
+    we_q = 0 ;
+    #1 pipe_out = sinit_value;
+  end
+
+//  Generate output control signals RFD and  RDY 
+//  Combinational
+
+    always @ ( rfd_int)
+    begin
+      if (c_has_rfd == 1) 
+        RFD = rfd_int ;
+      else
+        RFD = 1'b0 ;
+    end
+
+    always @ (en_int )
+    begin
+      if (en_int == 1'b1)
+        rfd_int = 1'b1 ;
+      else
+        rfd_int = 1'b0 ;
+    end
+
+    always @ (  rdy_int )
+    begin
+      if ((c_has_rdy == 1) && (c_has_nd == 1) && (c_has_rfd == 1) )
+        RDY = rdy_int ;
+      else
+        RDY = 1'b0 ;
+    end
+
+    assign nd_int = en_int && nd_i ; // only pass nd through if en is 1 
+
+// Register hanshaking inputs
+
+    always @(posedge clk_int )
+    begin
+      if (en_int == 1'b1)
+      begin
+        if (ssr_int == 1'b1)
+          nd_q <= 1'b0 ;
+        else
+          nd_q   <= nd_int;
+        end
+      else
+        nd_q   <= nd_q ;
+    end
+// Register data / address / data inputs
+
+  always @(posedge clk_int )
+  begin
+    if (en_int == 1'b1)
+      begin
+        di_q  <= di_i ;
+        addr_q <= addr_i ;
+        we_q <= we_i ;
+      end
+  end
+
+// select registered or non-registered write enable
+
+  always @( we_i or we_q)
+  begin
+    if (c_reg_inputs == 1 )
+      we_int = we_q ;
+     else
+      we_int = we_i ;
+  end
+
+// select registered data/address/nd inputs
+
+  always @( di_i or di_q)
+  begin
+    if ( c_reg_inputs == 1)
+      di_int = di_q ;
+    else
+      di_int = di_i ;
+  end
+
+  always @( addr_i or addr_q or nd_q or nd_int or we_q or we_i)
+  begin
+    if (c_reg_inputs == 1)
+      begin
+        addr_int = addr_q;
+        if ((we_q == 1'b1) && (c_write_mode == 2))
+          new_data = 1'b0 ;
+       	else     
+          new_data = nd_q ;
+      end
+    else
+      begin
+        addr_int = addr_i ;
+        if ((we_i == 1'b1) && (c_write_mode == 2))
+          new_data = 1'b0 ;
+       	else        
+          new_data = nd_int ;
+      end
+  end
+
+// Register the new_data signal to track the synchronous RAM output
+
+  always @(posedge clk_int)
+  begin
+    if ( en_int == 1'b1 )
+      begin
+       if (ssr_int == 1'b1)
+          new_data_q <= 0 ;
+       else
+          new_data_q <= new_data ;
+      end
+  end
+
+   initial begin
+     case (c_write_mode)
+       `c_write_first : wr_mode <= 2'b00;
+       `c_read_first  : wr_mode <= 2'b01;
+       `c_no_change   : wr_mode <= 2'b10;
+       default        : begin
+         if (c_yydisable_warnings == 0) begin
+	   $display("Error in %m at time %t: c_write_mode = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time , c_write_mode);
+         end
+	 $finish;
+       end
+     endcase
+   end
+
+
+    /***************************************************************
+    *The following always block assigns the value for the DOUT bus
+    ***************************************************************/   
+   always @(posedge clk_int) begin
+     if (en_int == 1'b1) begin
+       if (ssr_int == 1'b1) begin
+           dout_int <= sinit_value;
+       end
+       else begin
+	 //The following IF block assigns the output for a write operation
+         if (we_int == 1'b1) begin
+           if (wr_mode == 2'b00) begin
+             if (addr_int < c_depth) 
+                 dout_int <= di_int;
+             else
+	       //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "Write First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+               if (c_yydisable_warnings == 0) begin
+	         $display("Invalid Address Warning #1: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);    
+               end
+           end
+           else if (wr_mode == 2'b01) begin
+             if (addr_int < c_depth) 
+               dout_int <= mem[addr_int];
+             else
+	       //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "Read First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+              if (c_yydisable_warnings == 0) begin
+	        $display("Invalid Address Warning #2: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+              end
+           end
+           else begin
+             if (addr_int < c_depth) 
+               dout_int <= dout_int ;
+             else
+	      //Warning Condition (Error occurs on rising edge of CLK): 
+	       //Write Mode Port is "No Change" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range
+              if (c_yydisable_warnings == 0) begin
+	        $display("Invalid Address Warning #3: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+              end
+           end
+	 end
+	 //The following ELSE block assigns the output for a read operation
+	 else begin
+           if (addr_int < c_depth) 
+             dout_int <= mem[addr_int];
+           else
+             //Warning Condition (Error occurs on rising edge of CLK): 
+	     //EN = 1 and SINIT = 0 and WE = 0 and ADDRA out of the valid range 
+            if (c_yydisable_warnings == 0) begin
+	      $display("Invalid Address Warning #4: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+            end
+	 end
+       end
+     end
+   end
+
+
+// Write to memory contents
+    /***************************************************************************************
+    *The following always block assigns the DIN bus to the memory during a write operation
+    ***************************************************************************************/ 
+   always @(posedge clk_int) begin
+     if (en_int == 1'b1 && we_int == 1'b1) begin
+       if (addr_int < c_depth) 
+         mem [addr_int] <= di_int ;
+       else
+	 //Warning Condition (Error occurs on rising edge of CLK): 
+	 //EN = 1 and WE = 1 and ADDR out of the valid range
+        if (c_yydisable_warnings == 0) begin
+	  $display("Invalid Address Warning #5: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1);
+        end
+     end
+   end
+
+//  output pipelines 
+ 
+   always @(posedge clk_int) begin
+      if (en_int == 1'b1 && c_pipe_stages > 0)
+	begin
+           for (i = c_pipe_stages; i >= 1; i = i -1 )
+             begin
+		if (ssr_int == 1'b1 && en_int == 1'b1)
+		  begin
+		     pipeline[i] <= sinit_value ;
+		     sub_rdy[i] <=  0 ;
+		  end
+		else
+		  begin
+                    // Do not update output register if no_change on write and
+                    // WE = 1
+//                    if (!(c_write_mode == 2 && we_int == 1)) begin
+                      if (i==1)
+                        begin
+                          pipeline[i] <= dout_int;
+                        end
+                      else
+                        begin
+                          pipeline[i] <= pipeline[i-1] ;
+                        end
+//                    end // if (!(c_write_mode == 2 && we_int == 1))
+                    if (i==1)
+                      begin
+                        sub_rdy[i]  <= new_data_q;
+                      end
+                    else
+                      begin
+                        sub_rdy[i]  <= sub_rdy[i-1] ;
+                      end                    
+                  end
+             end
+        end
+    end
+
+// Select pipelined data output or no-pipelined data output
+ 
+   always @( pipeline[c_pipe_stages] or sub_rdy[c_pipe_stages] or new_data_q or dout_int) begin
+     if (c_pipe_stages == 0 )
+     begin
+       pipe_out = dout_int ;
+       rdy_int = new_data_q ;
+     end
+     else
+     begin
+       rdy_int = sub_rdy[c_pipe_stages];
+       pipe_out = pipeline[c_pipe_stages];
+     end
+   end
+
+endmodule
+
+`endcelldefine

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_1.v

@@ -0,0 +1,911 @@
+/******************************************************************************
+ *
+ * Block Memory Generator Core - Block Memory Behavioral Model
+ *
+ * Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
+ * This text/file contains proprietary, confidential
+ * information of Xilinx, Inc., is distributed under
+ * license from Xilinx, Inc., and may be used, copied
+ * and/or disclosed only pursuant to the terms of a valid
+ * license agreement with Xilinx, Inc. Xilinx hereby
+ * grants you a license to use this text/file solely for
+ * design, simulation, implementation and creation of
+ * design files limited to Xilinx devices or technologies.
+ * Use with non-Xilinx devices or technologies is expressly
+ * prohibited and immediately terminates your license unless
+ * covered by a separate agreement.
+ *
+ * Xilinx is providing this design, code, or information
+ * "as-is" solely for use in developing programs and
+ * solutions for Xilinx devices, with no obligation on the
+ * part of Xilinx to provide support. By providing this design,
+ * code, or information as one possible implementation of
+ * this feature, application or standard, Xilinx is making no
+ * representation that this implementation is free from any
+ * claims of infringement. You are responsible for obtaining
+ * any rights you may require for your implementation.
+ * Xilinx expressly disclaims any warranty whatsoever with
+ * respect to the adequacy of the implementation, including
+ * but not limited to any warranties or representations that this
+ * implementation is free from claims of infringement, implied
+ * warranties of merchantability or fitness for a particular
+ * purpose.
+ *
+ * Xilinx products are not intended for use in life support
+ * appliances, devices, or systems. Use in such applications is
+ * expressly prohibited.
+ *
+ * Any modifications that are made to the Source Code are
+ * done at the user's sole risk and will be unsupported.
+ * The Xilinx Support Hotline does not have access to source
+ * code and therefore cannot answer specific questions related
+ * to source HDL. The Xilinx Hotline support of original source
+ * code IP shall only address issues and questions related
+ * to the standard Netlist version of the core (and thus
+ * indirectly, the original core source).
+ *
+ * This copyright and support notice must be retained as part
+ * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc.
+ * All rights reserved.
+ *
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V2_1.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: January 11, 2006 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V2_1_output_stage
+  #(parameter C_DATA_WIDTH       = 32,
+    parameter C_HAS_SSR          = 1,
+    parameter C_SINIT_VAL        = "0",
+    parameter C_HAS_REGCE        = 1,
+    parameter C_HAS_EN           = 1,
+    parameter C_FAMILY           = "virtex5",
+    parameter num_stages         = 1,
+    parameter flop_delay         = 100)
+  (input                         CLK,
+   input                         SSR,
+   input                         REGCE,
+   input                         EN,
+   input      [C_DATA_WIDTH-1:0] DIN,
+   output reg [C_DATA_WIDTH-1:0] DOUT);
+
+  localparam reg_stages  = (num_stages == 0) ? 0 : num_stages-1;
+  reg [C_DATA_WIDTH*reg_stages-1:0] out_regs;
+  reg [C_DATA_WIDTH*8-1:0]          sinit_str = C_SINIT_VAL;
+  reg [C_DATA_WIDTH-1:0]            sinit_val;
+
+  // Wire off optional inputs based on parameters
+  //---------------------------------------------
+  wire                              en_i;
+  wire                              regce_i;
+  wire                              ssr_i;
+  assign   en_i    = (C_HAS_EN==0 || EN);
+  assign   regce_i = ((C_HAS_REGCE==1) && REGCE) ||
+                     ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
+  assign   ssr_i   = (C_HAS_SSR==1) && SSR;
+
+  initial begin
+    // Power on: load up the output registers and latches
+    if (!($sscanf(sinit_str, "%h", sinit_val))) begin
+      sinit_val = 0;
+    end
+    DOUT = sinit_val;
+    // This will be one wider than need, but 0 is an error
+    out_regs = {(reg_stages+1){sinit_val}};
+  end
+
+  generate if (num_stages == 0) begin : zero_stages
+    always @* begin
+      DOUT = DIN;
+    end
+  end
+  endgenerate
+
+ generate if (num_stages == 1) begin : one_stages
+    always @(posedge CLK) begin
+        if (regce_i && ssr_i) begin
+           DOUT <= #flop_delay sinit_val;
+        end else if (regce_i) begin
+           DOUT <= #flop_delay DIN;
+        end
+    end
+    end
+  endgenerate
+
+ generate if (num_stages > 1) begin : multi_stage
+    always @(posedge CLK) begin
+        if (regce_i && ssr_i) begin
+            DOUT           <= #flop_delay sinit_val;
+        end else if (regce_i) begin
+           DOUT         <= #flop_delay
+                        out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH];
+        end
+
+      if (en_i) begin
+        out_regs <= #flop_delay
+                    (out_regs << C_DATA_WIDTH) | DIN;
+      end
+    end
+  end
+  endgenerate
+endmodule
+
+module BLK_MEM_GEN_V2_1
+  #(parameter C_ADDRA_WIDTH             = 5,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_ALGORITHM               = 2,
+    parameter C_BYTE_SIZE               = 8,
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0,
+    parameter C_FAMILY                  = "virtex4",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_MEM_OUTPUT_REGS     = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS     = 0,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_HAS_SSRA                = 0,
+    parameter C_HAS_SSRB                = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_MEM_TYPE                = 2,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_SINITA_VAL              = "0",
+    parameter C_SINITB_VAL              = "0",
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_CORENAME                = "blk_mem_gen_v2_1")
+  (input                       CLKA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input                       SSRA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input                       SSRB,
+   output [C_READ_WIDTH_B-1:0] DOUTB);
+
+  // constants for the core behavior
+  //================================
+  // file handles for logging
+  //------------------------------------------------------
+  localparam addrfile           = 32'h8000_0001; // stdout for addr out of range
+  localparam collfile           = 32'h8000_0001; // stdout for coll detection
+  localparam errfile            = 32'h8000_0001; // stdout for file I/O errors
+
+  // other constants
+  //------------------------------------------------------
+  localparam coll_delay         = 2000;  // 2 ns
+
+  // locally derived parameters to determine memory shape
+  //-----------------------------------------------------
+  localparam min_width_a = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
+             C_WRITE_WIDTH_A : C_READ_WIDTH_A;
+  localparam min_width_b = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
+             C_WRITE_WIDTH_B : C_READ_WIDTH_B;
+  localparam min_width = (min_width_a < min_width_b) ?
+             min_width_a : min_width_b;
+
+  localparam max_width_a = (C_WRITE_WIDTH_A > C_READ_WIDTH_A) ?
+             C_WRITE_WIDTH_A : C_READ_WIDTH_A;
+  localparam max_width_b = (C_WRITE_WIDTH_B > C_READ_WIDTH_B) ?
+             C_WRITE_WIDTH_B : C_READ_WIDTH_B;
+  localparam max_width = (max_width_a > max_width_b) ?
+             max_width_a : max_width_b;
+
+  localparam max_depth_a = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
+             C_WRITE_DEPTH_A : C_READ_DEPTH_A;
+  localparam max_depth_b = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
+             C_WRITE_DEPTH_B : C_READ_DEPTH_B;
+  localparam max_depth = (max_depth_a > max_depth_b) ?
+             max_depth_a : max_depth_b;
+
+  // locally derived parameters to assist memory access
+  //----------------------------------------------------
+  localparam write_width_ratio_a = C_WRITE_WIDTH_A/min_width;
+  localparam read_width_ratio_a  = C_READ_WIDTH_A/min_width;
+  localparam write_width_ratio_b = C_WRITE_WIDTH_B/min_width;
+  localparam read_width_ratio_b  = C_READ_WIDTH_B/min_width;
+
+  // To modify the LSBs of the 'wider' data to the actual
+  //    address value
+  //----------------------------------------------------
+  localparam write_addr_a_div  = C_WRITE_WIDTH_A/min_width_a;
+  localparam read_addr_a_div   = C_READ_WIDTH_A/min_width_a;
+  localparam write_addr_b_div  = C_WRITE_WIDTH_B/min_width_b;
+  localparam read_addr_b_div   = C_READ_WIDTH_B/min_width_b;
+
+  // If byte writes aren't being used, make sure byte_size is not
+  // wider than the memory elements to avoid compilation warnings
+  localparam byte_size   = (C_BYTE_SIZE < min_width) ? C_BYTE_SIZE : min_width;
+
+  // the memory
+  reg [min_width-1:0]      memory [0:max_depth-1];
+  // memory output 'latches'
+  reg [C_READ_WIDTH_A-1:0] memory_out_a;
+  reg [C_READ_WIDTH_B-1:0] memory_out_b;
+  // reset values
+  reg [C_READ_WIDTH_A-1:0] sinita_val;
+  reg [C_READ_WIDTH_B-1:0] sinitb_val;
+
+  // collision detect
+  reg                      is_collision;
+  reg                      is_collision_a, is_collision_delay_a;
+  reg                      is_collision_b, is_collision_delay_b;
+
+  // temporary variables for initialization
+  //---------------------------------------
+  integer                  status;
+  reg [639:0]              err_str;
+  integer                  initfile;
+  // data input buffer
+  reg [C_WRITE_WIDTH_A-1:0]    mif_data;
+  // string values in hex
+  reg [C_READ_WIDTH_A*8-1:0]   sinita_str       = C_SINITA_VAL;
+  reg [C_READ_WIDTH_B*8-1:0]   sinitb_str       = C_SINITB_VAL;
+  reg [C_WRITE_WIDTH_A*8-1:0]  default_data_str = C_DEFAULT_DATA;
+  // initialization filename
+  reg [1023*8-1:0]             init_file_str    = C_INIT_FILE_NAME;
+
+  // internal configuration parameters
+  //---------------------------------------------
+  localparam flop_delay  = 100;  // 100 ps
+  localparam single_port = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
+  localparam is_rom      = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
+  localparam has_a_write = (!is_rom);
+  localparam has_b_write = (C_MEM_TYPE==2);
+  localparam has_a_read  = (C_MEM_TYPE!=1);
+  localparam has_b_read  = (!single_port);
+  localparam has_b_port  = (has_b_read || has_b_write);
+  localparam num_output_stages = C_HAS_MEM_OUTPUT_REGS +
+                                 C_HAS_MUX_OUTPUT_REGS;
+
+  wire                   ena_i;
+  wire                   enb_i;
+  wire                   reseta_i;
+  wire                   resetb_i;
+  wire [C_WEA_WIDTH-1:0] wea_i;
+  wire [C_WEB_WIDTH-1:0] web_i;
+  wire                   rea_i;
+  wire                   reb_i;
+  assign ena_i  = (C_HAS_ENA==0) || ENA;
+  assign enb_i  = ((C_HAS_ENB==0) || ENB) && has_b_port;
+  assign reseta_i = (C_HAS_SSRA==1) && SSRA && ena_i &&
+                    (num_output_stages==0);
+  assign resetb_i = (C_HAS_SSRB==1) && SSRB && enb_i &&
+                    (num_output_stages==0);
+  assign wea_i = (has_a_write && ena_i) ? WEA : 'b0;
+  assign web_i = (has_b_write && enb_i) ? WEB : 'b0;
+  assign rea_i = (has_a_read)  ? ena_i : 'b0;
+  assign reb_i = (has_b_read)  ? enb_i : 'b0;
+
+  // tasks to access the memory
+  //---------------------------
+  task write_a
+    (input  reg [C_ADDRA_WIDTH-1:0]   addr,
+     input  reg [C_WEA_WIDTH-1:0]     byte_en,
+     input  reg [C_WRITE_WIDTH_A-1:0] data);
+    reg [C_WRITE_WIDTH_A-1:0] current_contents;
+    reg [C_ADDRA_WIDTH-1:0] address;
+    integer i;
+    begin
+      // Shift the address by the ratio
+      address = (addr/write_addr_a_div);
+      if (address >= C_WRITE_DEPTH_A) begin
+        if (!C_DISABLE_WARN_BHV_RANGE) begin
+          $fdisplay(addrfile,
+                    "%0s WARNING: Address %0h is outside range for A Write",
+                    C_CORENAME, addr);
+        end
+
+      // valid address
+      end else begin
+
+        // Combine w/ byte writes
+        if (C_USE_BYTE_WEA) begin
+
+          // Get the current memory contents
+          if (write_width_ratio_a == 1) begin
+            // Workaround for IUS 5.5 part-select issue
+            current_contents = memory[address];
+          end else begin
+            for (i = 0; i < write_width_ratio_a; i = i + 1) begin
+              current_contents[min_width*i+:min_width]
+                = memory[address*write_width_ratio_a + i];
+            end
+          end
+
+          // Apply incoming bytes
+          if (C_WEA_WIDTH == 1) begin
+            // Workaround for IUS 5.5 part-select issue
+            if (byte_en[0]) begin
+              current_contents = data;
+            end
+          end else begin
+            for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
+              if (byte_en[i]) begin
+                current_contents[byte_size*i+:byte_size]
+                  = data[byte_size*i+:byte_size];
+              end
+            end
+          end
+
+        // No byte-writes, overwrite the whole word
+        end else begin
+          current_contents = data;
+        end
+
+        // Write data to memory
+        if (write_width_ratio_a == 1) begin
+          // Workaround for IUS 5.5 part-select issue
+          memory[address*write_width_ratio_a] = current_contents;
+        end else begin
+          for (i = 0; i < write_width_ratio_a; i = i + 1) begin
+            memory[address*write_width_ratio_a + i]
+              = current_contents[min_width*i+:min_width];
+          end
+        end
+
+      end
+    end
+  endtask
+
+  task write_b
+    (input  reg [C_ADDRB_WIDTH-1:0]   addr,
+     input  reg [C_WEB_WIDTH-1:0]     byte_en,
+     input  reg [C_WRITE_WIDTH_B-1:0] data);
+    reg [C_WRITE_WIDTH_B-1:0] current_contents;
+    reg [C_ADDRB_WIDTH-1:0]   address;
+    integer i;
+    begin
+      // Shift the address by the ratio
+      address = (addr/write_addr_b_div);
+      if (address >= C_WRITE_DEPTH_B) begin
+        if (!C_DISABLE_WARN_BHV_RANGE) begin
+          $fdisplay(addrfile,
+                    "%0s WARNING: Address %0h is outside range for B Write",
+                    C_CORENAME, addr);
+        end
+
+      // valid address
+      end else begin
+
+        // Combine w/ byte writes
+        if (C_USE_BYTE_WEB) begin
+
+          // Get the current memory contents
+          if (write_width_ratio_b == 1) begin
+            // Workaround for IUS 5.5 part-select issue
+            current_contents = memory[address];
+          end else begin
+            for (i = 0; i < write_width_ratio_b; i = i + 1) begin
+              current_contents[min_width*i+:min_width]
+                = memory[address*write_width_ratio_b + i];
+            end
+          end
+
+          // Apply incoming bytes
+          if (C_WEB_WIDTH == 1) begin
+            // Workaround for IUS 5.5 part-select issue
+            if (byte_en[0]) begin
+              current_contents = data;
+            end
+          end else begin
+            for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
+              if (byte_en[i]) begin
+                current_contents[byte_size*i+:byte_size]
+                  = data[byte_size*i+:byte_size];
+              end
+            end
+          end
+
+        // No byte-writes, overwrite the whole word
+        end else begin
+          current_contents = data;
+        end
+
+        // Write data to memory
+        if (write_width_ratio_b == 1) begin
+          // Workaround for IUS 5.5 part-select issue
+          memory[address*write_width_ratio_b] = current_contents;
+        end else begin
+          for (i = 0; i < write_width_ratio_b; i = i + 1) begin
+            memory[address*write_width_ratio_b + i]
+              = current_contents[min_width*i+:min_width];
+          end
+        end
+      end
+    end
+  endtask
+
+  task read_a
+    (input reg [C_ADDRA_WIDTH-1:0] addr,
+     input reg reset);
+    reg [C_ADDRA_WIDTH-1:0] address;
+    integer i;
+    begin
+
+      if (reset) begin
+        memory_out_a <= #flop_delay sinita_val;
+      end else begin
+        // Shift the address by the ratio
+        address = (addr/read_addr_a_div);
+        if (address >= C_READ_DEPTH_A) begin
+          if (!C_DISABLE_WARN_BHV_RANGE) begin
+            $fdisplay(addrfile,
+                      "%0s WARNING: Address %0h is outside range for A Read",
+                      C_CORENAME, addr);
+          end
+
+          // valid address
+        end else begin
+
+          if (read_width_ratio_a==1) begin
+            memory_out_a <= #flop_delay memory[address*read_width_ratio_a];
+          end else begin
+            // Increment through the 'partial' words in the memory
+            for (i = 0; i < read_width_ratio_a; i = i + 1) begin
+              memory_out_a[min_width*i+:min_width]
+                <= #flop_delay memory[address*read_width_ratio_a + i];
+            end
+          end
+
+        end
+      end
+    end
+  endtask
+
+  task read_b
+    (input reg [C_ADDRB_WIDTH-1:0] addr,
+     input reg reset);
+    reg [C_ADDRB_WIDTH-1:0] address;
+    integer i;
+    begin
+
+      if (reset) begin
+        memory_out_b <= #flop_delay sinitb_val;
+      end else begin
+        // Shift the address
+        address = (addr/read_addr_b_div);
+        if (address >= C_READ_DEPTH_B) begin
+          if (!C_DISABLE_WARN_BHV_RANGE) begin
+            $fdisplay(addrfile,
+                      "%0s WARNING: Address %0h is outside range for B Read",
+                      C_CORENAME, addr);
+          end
+
+          // valid address
+        end else begin
+
+          if (read_width_ratio_b==1) begin
+            memory_out_b <= #flop_delay memory[address*read_width_ratio_b];
+          end else begin
+            // Increment through the 'partial' words in the memory
+            for (i = 0; i < read_width_ratio_b; i = i + 1) begin
+              memory_out_b[min_width*i+:min_width]
+                <= #flop_delay memory[address*read_width_ratio_b + i];
+            end
+          end
+
+        end
+      end
+    end
+  endtask
+
+  task init_memory;
+    integer i, addr_step;
+    integer status;
+    reg [C_WRITE_WIDTH_A-1:0] default_data;
+    begin
+      default_data = 0;
+
+      // Convert the default to hex
+      if (C_USE_DEFAULT_DATA) begin
+        if (default_data_str == "") begin
+          $fdisplay(errfile, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
+          $finish;
+        end else begin
+          status = $sscanf(default_data_str, "%h", default_data);
+          if (status == 0) begin
+            $fdisplay(errfile, {"%0s ERROR: Unsuccessful hexadecimal read",
+                                "from C_DEFAULT_DATA: %0s"},
+                      C_CORENAME, C_DEFAULT_DATA);
+            $finish;
+          end
+        end
+      end
+
+      // Step by write_addr_a_div through the memory via the
+      // Port A write interface to hit every location once
+      addr_step = write_addr_a_div;
+
+      // 'write' to every location with default (or 0)
+      for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
+        write_a(i, {C_WEA_WIDTH{1'b1}}, default_data);
+      end
+
+      // Get specialized data from the MIF file
+      if (C_LOAD_INIT_FILE) begin
+        if (init_file_str == "") begin
+          $fdisplay(errfile, "%0s ERROR: C_INIT_FILE_NAME is empty!",
+                    C_CORENAME);
+          $finish;
+        end else begin
+          initfile = $fopen(init_file_str, "r");
+          if (initfile == 0) begin
+            $fdisplay(errfile, {"%0s, ERROR: Problem opening",
+                                "C_INIT_FILE_NAME: %0s!"},
+                      C_CORENAME, init_file_str);
+            $finish;
+          end else begin
+            // loop through the mif file, loading in the data
+            for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
+              status = $fscanf(initfile, "%b", mif_data);
+              if (status > 0) begin
+                write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data);
+              end
+            end
+            $fclose(initfile);
+          end
+        end
+      end
+    end
+  endtask
+
+  function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
+                                    input integer iswrite_a,
+                                    input reg [C_ADDRB_WIDTH-1:0] addr_b,
+                                    input integer iswrite_b);
+    reg [C_ADDRA_WIDTH-1:0] base_addr_a;
+    reg [C_ADDRB_WIDTH-1:0] base_addr_b;
+    integer ratio_a, ratio_b;
+    integer lo_addr_wider,  hi_addr_wider;
+    integer lo_addr_narrow, hi_addr_narrow;
+    begin
+      // Convert the input addresses in base and offsets for our
+      //   memory array. Ignore LSBs for asymmetric ports
+      if (iswrite_a) begin
+        base_addr_a = (addr_a/write_addr_a_div) * write_addr_a_div;
+        ratio_a     = write_width_ratio_a;
+      end else begin
+        base_addr_a = (addr_a/read_addr_a_div) *  read_addr_a_div;
+        ratio_a     = read_width_ratio_a;
+      end
+      if (iswrite_b) begin
+        base_addr_b = (addr_b/write_addr_b_div) * write_addr_b_div;
+        ratio_b     = write_width_ratio_b;
+      end else begin
+        base_addr_b = (addr_b/read_addr_b_div) *  read_addr_b_div;
+        ratio_b     = read_width_ratio_b;
+      end
+
+      // Determine the wider port, and normalized ranges
+      if (ratio_a >= ratio_b) begin
+        lo_addr_wider  = base_addr_a * ratio_a;
+        hi_addr_wider  = lo_addr_wider  + ratio_a;
+        lo_addr_narrow = base_addr_b * ratio_b;
+        hi_addr_narrow = lo_addr_narrow + ratio_b;
+      end else begin
+        lo_addr_wider  = base_addr_b * ratio_b;
+        hi_addr_wider  = lo_addr_wider  + ratio_b;
+        lo_addr_narrow = base_addr_a * ratio_a;
+        hi_addr_narrow = lo_addr_narrow + ratio_a;
+      end
+
+      // compare the two ranges of address (narrow inside wider)
+      if ((lo_addr_narrow >= lo_addr_wider) &&
+          (hi_addr_narrow <= hi_addr_wider)) begin
+        collision_check = 1;
+      end else begin
+        collision_check = 0;
+      end
+
+    end
+  endfunction
+
+  // power on values
+  //-----------------------------
+  initial begin
+    // Load up the memory
+    init_memory;
+    // Load up the output registers and latches
+    if ($sscanf(sinita_str, "%h", sinita_val)) begin
+      memory_out_a = sinita_val;
+    end else begin
+      memory_out_a = 0;
+    end
+    if ($sscanf(sinitb_str, "%h", sinitb_val)) begin
+      memory_out_b = sinitb_val;
+    end else begin
+      memory_out_b = 0;
+    end
+
+    $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
+
+  end
+
+  //-------------------------------------------------------------------------
+  // These are the main blocks which schedule read and write operations
+  //-------------------------------------------------------------------------
+
+  generate if (C_COMMON_CLK) begin : common_clk_scheduling
+      // Synchronous clocks: schedule port operations with respect to
+      // both write operating modes
+      always @(posedge CLKA) begin
+        case ({C_WRITE_MODE_A, C_WRITE_MODE_B})
+          {"WRITE_FIRST","WRITE_FIRST"}: begin
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if (web_i) write_b(ADDRB, web_i, DINB);
+            if (rea_i) read_a(ADDRA, reseta_i);
+            if (reb_i) read_b(ADDRB, resetb_i);
+          end
+          {"READ_FIRST", "WRITE_FIRST"}: begin
+            if (web_i) write_b(ADDRB, web_i, DINB);
+            if (reb_i) read_b(ADDRB, resetb_i);
+            if (rea_i) read_a(ADDRA, reseta_i);
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+          end
+          {"WRITE_FIRST","READ_FIRST"}: begin
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if (rea_i) read_a(ADDRA, reseta_i);
+            if (reb_i) read_b(ADDRB, resetb_i);
+            if (web_i) write_b(ADDRB, web_i, DINB);
+          end
+          {"READ_FIRST", "READ_FIRST"}: begin
+            if (rea_i) read_a(ADDRA, reseta_i);
+            if (reb_i) read_b(ADDRB, resetb_i);
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if (web_i) write_b(ADDRB, web_i, DINB);
+          end
+          {"WRITE_FIRST","NO_CHANGE"}: begin
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if (rea_i) read_a(ADDRA, reseta_i);
+            if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i);
+            if (web_i) write_b(ADDRB, web_i, DINB);
+          end
+          {"READ_FIRST", "NO_CHANGE"}: begin
+            if (rea_i) read_a(ADDRA, reseta_i);
+            if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i);
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if (web_i) write_b(ADDRB, web_i, DINB);
+          end
+          {"NO_CHANGE",  "WRITE_FIRST"}: begin
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if (web_i) write_b(ADDRB, web_i, DINB);
+            if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i);
+            if (reb_i) read_b(ADDRB, resetb_i);
+          end
+          {"NO_CHANGE",  "READ_FIRST"}: begin
+            if (reb_i) read_b(ADDRB, resetb_i);
+            if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i);
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if (web_i) write_b(ADDRB, web_i, DINB);
+          end
+          {"NO_CHANGE",  "NO_CHANGE"}: begin
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if (web_i) write_b(ADDRB, web_i, DINB);
+            if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i);
+            if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i);
+          end
+          default: begin
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if (web_i) write_b(ADDRB, web_i, DINB);
+            if (rea_i) read_a(ADDRA, reseta_i);
+            if (reb_i) read_b(ADDRB, resetb_i);
+          end
+        endcase
+      end
+
+  end else begin : asynch_clk_scheduling
+      // Asynchronous clocks: port operation is independent
+      always @(posedge CLKA) begin
+        case (C_WRITE_MODE_A)
+          "WRITE_FIRST": begin
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if (rea_i) read_a(ADDRA, reseta_i);
+          end
+          "READ_FIRST": begin
+            if (rea_i) read_a(ADDRA, reseta_i);
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+          end
+          "NO_CHANGE": begin
+            if (wea_i) write_a(ADDRA, wea_i, DINA);
+            if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i);
+          end
+        endcase
+      end
+
+      always @(posedge CLKB) begin
+        case (C_WRITE_MODE_B)
+          "WRITE_FIRST": begin
+            if (web_i) write_b(ADDRB, web_i, DINB);
+            if (reb_i) read_b(ADDRB, resetb_i);
+          end
+          "READ_FIRST": begin
+            if (reb_i) read_b(ADDRB, resetb_i);
+            if (web_i) write_b(ADDRB, web_i, DINB);
+          end
+          "NO_CHANGE": begin
+            if (web_i) write_b(ADDRB, web_i, DINB);
+            if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i);
+          end
+        endcase
+      end
+  end
+  endgenerate
+
+  // Variable depth output stage
+  BLK_MEM_GEN_V2_1_output_stage
+    #(.C_DATA_WIDTH (C_READ_WIDTH_A),
+      .C_HAS_SSR    (C_HAS_SSRA),
+      .C_SINIT_VAL  (C_SINITA_VAL),
+      .C_HAS_REGCE  (C_HAS_REGCEA),
+      .C_HAS_EN     (C_HAS_ENA),
+      .C_FAMILY     (C_FAMILY),
+      .num_stages   (num_output_stages),
+      .flop_delay   (flop_delay))
+      reg_a
+        (.CLK   (CLKA),
+         .SSR   (SSRA),
+         .REGCE (REGCEA),
+         .EN    (ENA),
+         .DIN   (memory_out_a),
+         .DOUT  (DOUTA));
+
+  BLK_MEM_GEN_V2_1_output_stage
+    #(.C_DATA_WIDTH (C_READ_WIDTH_B),
+      .C_HAS_SSR    (C_HAS_SSRB),
+      .C_SINIT_VAL  (C_SINITB_VAL),
+      .C_HAS_REGCE  (C_HAS_REGCEB),
+      .C_HAS_EN     (C_HAS_ENB),
+      .C_FAMILY     (C_FAMILY),
+      .num_stages   (num_output_stages),
+      .flop_delay   (flop_delay))
+      reg_b
+        (.CLK   (CLKB),
+         .SSR   (SSRB),
+         .REGCE (REGCEB),
+         .EN    (ENB),
+         .DIN   (memory_out_b),
+         .DOUT  (DOUTB));
+
+  // Synchronous collision checks
+  generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
+    always @(posedge CLKA) begin
+      // Possible collision if both are enabled and the addresses match
+      if (ena_i && enb_i) begin
+        is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
+      end else begin
+        is_collision = 0;
+      end
+
+      // If the write port is in READ_FIRST mode, there is no collision
+      if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
+        is_collision = 0;
+      end
+      if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
+        is_collision = 0;
+      end
+
+      // Only flag if one of the accesses is a write
+      if (is_collision && (wea_i || web_i)) begin
+        $fwrite(collfile, "%0s collision detected at time: %0d, ",
+                C_CORENAME, $time);
+        $fwrite(collfile, "A %0s address: %0h, B %0s address: %0h\n",
+                wea_i ? "write" : "read", ADDRA,
+                web_i ? "write" : "read", ADDRB);
+      end
+    end
+
+  // Asynchronous collision checks
+  end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
+
+    // Delay A and B addresses in order to mimic setup/hold times
+    wire [C_ADDRA_WIDTH-1:0]  #coll_delay addra_delay = ADDRA;
+    wire [0:0]                #coll_delay wea_delay   = wea_i;
+    wire                      #coll_delay ena_delay   = ena_i;
+    wire [C_ADDRB_WIDTH-1:0]  #coll_delay addrb_delay = ADDRB;
+    wire [0:0]                #coll_delay web_delay   = web_i;
+    wire                      #coll_delay enb_delay   = enb_i;
+
+    // Do the checks w/rt A
+    always @(posedge CLKA) begin
+      // Possible collision if both are enabled and the addresses match
+      if (ena_i && enb_i) begin
+        is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
+      end else begin
+        is_collision_a = 0;
+      end
+      if (ena_i && enb_delay) begin
+        is_collision_delay_a = collision_check(ADDRA, wea_i,
+                                               addrb_delay, web_delay);
+      end else begin
+        is_collision_delay_a = 0;
+      end
+
+
+      // Only flag if B access is a write
+      if (is_collision_a && web_i) begin
+        $fwrite(collfile, "%0s collision detected at time: %0d, ",
+                C_CORENAME, $time);
+        $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n",
+                wea_i ? "write" : "read", ADDRA, ADDRB);
+
+      end else if (is_collision_delay_a && web_delay) begin
+        $fwrite(collfile, "%0s collision detected at time: %0d, ",
+                C_CORENAME, $time);
+        $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n",
+                wea_i ? "write" : "read", ADDRA, addrb_delay);
+      end
+
+    end
+
+    // Do the checks w/rt B
+    always @(posedge CLKB) begin
+
+      // Possible collision if both are enabled and the addresses match
+      if (ena_i && enb_i) begin
+        is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
+      end else begin
+        is_collision_b = 0;
+      end
+      if (ena_delay && enb_i) begin
+        is_collision_delay_b = collision_check(addra_delay, wea_delay,
+                                               ADDRB, web_i);
+      end else begin
+        is_collision_delay_b = 0;
+      end
+
+
+      // Only flag if A access is a write
+      if (is_collision_b && wea_i) begin
+        $fwrite(collfile, "%0s collision detected at time: %0d, ",
+                C_CORENAME, $time);
+        $fwrite(collfile, "A write address: %0h, B %s address: %0h\n",
+                ADDRA, web_i ? "write" : "read", ADDRB);
+
+      end else if (is_collision_delay_b && wea_delay) begin
+        $fwrite(collfile, "%0s collision detected at time: %0d, ",
+                C_CORENAME, $time);
+        $fwrite(collfile, "A write address: %0h, B %s address: %0h\n",
+                addra_delay, web_i ? "write" : "read", ADDRB);
+      end
+
+    end
+  end
+  endgenerate
+
+endmodule

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_1_xst.v

@@ -0,0 +1,183 @@
+/******************************************************************************
+ *
+ * Block Memory Generator Core - Block Memory Behavioral Model
+ *
+ * Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
+ * This text/file contains proprietary, confidential
+ * information of Xilinx, Inc., is distributed under
+ * license from Xilinx, Inc., and may be used, copied
+ * and/or disclosed only pursuant to the terms of a valid
+ * license agreement with Xilinx, Inc. Xilinx hereby
+ * grants you a license to use this text/file solely for
+ * design, simulation, implementation and creation of
+ * design files limited to Xilinx devices or technologies.
+ * Use with non-Xilinx devices or technologies is expressly
+ * prohibited and immediately terminates your license unless
+ * covered by a separate agreement.
+ *
+ * Xilinx is providing this design, code, or information
+ * "as-is" solely for use in developing programs and
+ * solutions for Xilinx devices, with no obligation on the
+ * part of Xilinx to provide support. By providing this design,
+ * code, or information as one possible implementation of
+ * this feature, application or standard, Xilinx is making no
+ * representation that this implementation is free from any
+ * claims of infringement. You are responsible for obtaining
+ * any rights you may require for your implementation.
+ * Xilinx expressly disclaims any warranty whatsoever with
+ * respect to the adequacy of the implementation, including
+ * but not limited to any warranties or representations that this
+ * implementation is free from claims of infringement, implied
+ * warranties of merchantability or fitness for a particular
+ * purpose.
+ *
+ * Xilinx products are not intended for use in life support
+ * appliances, devices, or systems. Use in such applications is
+ * expressly prohibited.
+ *
+ * Any modifications that are made to the Source Code are
+ * done at the user's sole risk and will be unsupported.
+ * The Xilinx Support Hotline does not have access to source
+ * code and therefore cannot answer specific questions related
+ * to source HDL. The Xilinx Hotline support of original source
+ * code IP shall only address issues and questions related
+ * to the standard Netlist version of the core (and thus
+ * indirectly, the original core source).
+ *
+ * This copyright and support notice must be retained as part
+ * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc.
+ * All rights reserved.
+ *
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V2_1.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V2_1_xst
+  #(parameter C_ADDRA_WIDTH             = 5,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_ALGORITHM               = 1,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0,
+    parameter C_FAMILY                  = "virtex5",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_MEM_OUTPUT_REGS     = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS     = 0,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_HAS_SSRA                = 0,
+    parameter C_HAS_SSRB                = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_MEM_TYPE                = 2,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_SINITA_VAL              = "0",
+    parameter C_SINITB_VAL              = "0",
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_WRITE_WIDTH_B           = 32)
+  (input                       CLKA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input                       SSRA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input                       SSRB,
+   output [C_READ_WIDTH_B-1:0] DOUTB);
+
+  BLK_MEM_GEN_V2_1
+  #(.C_FAMILY                  (C_FAMILY),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_HAS_MEM_OUTPUT_REGS     (C_HAS_MEM_OUTPUT_REGS),
+    .C_HAS_MUX_OUTPUT_REGS     (C_HAS_MUX_OUTPUT_REGS),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_HAS_SSRA                (C_HAS_SSRA),
+    .C_SINITA_VAL              (C_SINITA_VAL),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_HAS_SSRB                (C_HAS_SSRB),
+    .C_SINITB_VAL              (C_SINITB_VAL),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_WEB_WIDTH               (C_WEB_WIDTH)
+    ) blk_mem_gen_v2_1_dut (
+    .DINA       (DINA),
+    .DINB       (DINB),
+    .ADDRA      (ADDRA),
+    .ADDRB      (ADDRB),
+    .ENA        (ENA),
+    .ENB        (ENB),
+    .REGCEA     (REGCEA),
+    .REGCEB     (REGCEB),
+    .WEA        (WEA),
+    .WEB        (WEB),
+    .SSRA       (SSRA),
+    .SSRB       (SSRB),
+    .CLKA       (CLKA),
+    .CLKB       (CLKB),
+    .DOUTA      (DOUTA),
+    .DOUTB      (DOUTB)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_2_xst.v

@@ -0,0 +1,189 @@
+/******************************************************************************
+ *
+ * Block Memory Generator Core - Block Memory Behavioral Model
+ *
+ * Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
+ * This text/file contains proprietary, confidential
+ * information of Xilinx, Inc., is distributed under
+ * license from Xilinx, Inc., and may be used, copied
+ * and/or disclosed only pursuant to the terms of a valid
+ * license agreement with Xilinx, Inc. Xilinx hereby
+ * grants you a license to use this text/file solely for
+ * design, simulation, implementation and creation of
+ * design files limited to Xilinx devices or technologies.
+ * Use with non-Xilinx devices or technologies is expressly
+ * prohibited and immediately terminates your license unless
+ * covered by a separate agreement.
+ *
+ * Xilinx is providing this design, code, or information
+ * "as-is" solely for use in developing programs and
+ * solutions for Xilinx devices, with no obligation on the
+ * part of Xilinx to provide support. By providing this design,
+ * code, or information as one possible implementation of
+ * this feature, application or standard, Xilinx is making no
+ * representation that this implementation is free from any
+ * claims of infringement. You are responsible for obtaining
+ * any rights you may require for your implementation.
+ * Xilinx expressly disclaims any warranty whatsoever with
+ * respect to the adequacy of the implementation, including
+ * but not limited to any warranties or representations that this
+ * implementation is free from claims of infringement, implied
+ * warranties of merchantability or fitness for a particular
+ * purpose.
+ *
+ * Xilinx products are not intended for use in life support
+ * appliances, devices, or systems. Use in such applications is
+ * expressly prohibited.
+ *
+ * Any modifications that are made to the Source Code are
+ * done at the user's sole risk and will be unsupported.
+ * The Xilinx Support Hotline does not have access to source
+ * code and therefore cannot answer specific questions related
+ * to source HDL. The Xilinx Hotline support of original source
+ * code IP shall only address issues and questions related
+ * to the standard Netlist version of the core (and thus
+ * indirectly, the original core source).
+ *
+ * This copyright and support notice must be retained as part
+ * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc.
+ * All rights reserved.
+ *
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V2_2.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V2_2_xst
+  #(parameter C_ADDRA_WIDTH             = 5,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_ALGORITHM               = 1,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0,
+    parameter C_FAMILY                  = "virtex5",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_MEM_OUTPUT_REGS     = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS     = 0,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_HAS_SSRA                = 0,
+    parameter C_HAS_SSRB                = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_MEM_TYPE                = 2,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_SINITA_VAL              = "0",
+    parameter C_SINITB_VAL              = "0",
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_WRITE_WIDTH_B           = 32)
+  (input                       CLKA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input                       SSRA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input                       SSRB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   output                      DBITERR,
+   output                      SBITERR);
+
+  BLK_MEM_GEN_V2_2
+  #(.C_FAMILY                  (C_FAMILY),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_USE_ECC                 (C_USE_ECC),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_HAS_MEM_OUTPUT_REGS     (C_HAS_MEM_OUTPUT_REGS),
+    .C_HAS_MUX_OUTPUT_REGS     (C_HAS_MUX_OUTPUT_REGS),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_HAS_SSRA                (C_HAS_SSRA),
+    .C_SINITA_VAL              (C_SINITA_VAL),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_HAS_SSRB                (C_HAS_SSRB),
+    .C_SINITB_VAL              (C_SINITB_VAL),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_WEB_WIDTH               (C_WEB_WIDTH)
+    ) blk_mem_gen_v2_2_dut (
+    .DINA       (DINA),
+    .DINB       (DINB),
+    .ADDRA      (ADDRA),
+    .ADDRB      (ADDRB),
+    .ENA        (ENA),
+    .ENB        (ENB),
+    .REGCEA     (REGCEA),
+    .REGCEB     (REGCEB),
+    .WEA        (WEA),
+    .WEB        (WEB),
+    .SSRA       (SSRA),
+    .SSRB       (SSRB),
+    .CLKA       (CLKA),
+    .CLKB       (CLKB),
+    .DOUTA      (DOUTA),
+    .DOUTB      (DOUTB),
+    .DBITERR    (DBITERR),
+    .SBITERR    (SBITERR)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4_xst.v

@@ -0,0 +1,195 @@
+/******************************************************************************
+ *
+ * Block Memory Generator Core - Block Memory Behavioral Model
+ *
+ * Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
+ * This text/file contains proprietary, confidential
+ * information of Xilinx, Inc., is distributed under
+ * license from Xilinx, Inc., and may be used, copied
+ * and/or disclosed only pursuant to the terms of a valid
+ * license agreement with Xilinx, Inc. Xilinx hereby
+ * grants you a license to use this text/file solely for
+ * design, simulation, implementation and creation of
+ * design files limited to Xilinx devices or technologies.
+ * Use with non-Xilinx devices or technologies is expressly
+ * prohibited and immediately terminates your license unless
+ * covered by a separate agreement.
+ *
+ * Xilinx is providing this design, code, or information
+ * "as-is" solely for use in developing programs and
+ * solutions for Xilinx devices, with no obligation on the
+ * part of Xilinx to provide support. By providing this design,
+ * code, or information as one possible implementation of
+ * this feature, application or standard, Xilinx is making no
+ * representation that this implementation is free from any
+ * claims of infringement. You are responsible for obtaining
+ * any rights you may require for your implementation.
+ * Xilinx expressly disclaims any warranty whatsoever with
+ * respect to the adequacy of the implementation, including
+ * but not limited to any warranties or representations that this
+ * implementation is free from claims of infringement, implied
+ * warranties of merchantability or fitness for a particular
+ * purpose.
+ *
+ * Xilinx products are not intended for use in life support
+ * appliances, devices, or systems. Use in such applications is
+ * expressly prohibited.
+ *
+ * Any modifications that are made to the Source Code are
+ * done at the user's sole risk and will be unsupported.
+ * The Xilinx Support Hotline does not have access to source
+ * code and therefore cannot answer specific questions related
+ * to source HDL. The Xilinx Hotline support of original source
+ * code IP shall only address issues and questions related
+ * to the standard Netlist version of the core (and thus
+ * indirectly, the original core source).
+ *
+ * This copyright and support notice must be retained as part
+ * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc.
+ * All rights reserved.
+ *
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V2_4.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V2_4_xst
+  #(parameter C_ADDRA_WIDTH             = 5,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_ALGORITHM               = 1,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0,
+    parameter C_FAMILY           = "virtex5",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_MEM_OUTPUT_REGS     = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS     = 0,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_HAS_SSRA                = 0,
+    parameter C_HAS_SSRB                = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_MEM_TYPE                = 2,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_SINITA_VAL              = "0",
+    parameter C_SINITB_VAL              = "0",
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_USE_RAMB16BWER_RST_BHV  = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_XDEVICEFAMILY           = "virtex5"
+)
+  (input                       CLKA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input                       SSRA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input                       SSRB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   output                      DBITERR,
+   output                      SBITERR);
+
+  BLK_MEM_GEN_V2_4
+  #(
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE),
+    .C_FAMILY                  (C_FAMILY),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_MEM_OUTPUT_REGS     (C_HAS_MEM_OUTPUT_REGS),
+    .C_HAS_MUX_OUTPUT_REGS     (C_HAS_MUX_OUTPUT_REGS),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_HAS_SSRA                (C_HAS_SSRA),
+    .C_HAS_SSRB                (C_HAS_SSRB),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_SINITA_VAL              (C_SINITA_VAL),
+    .C_SINITB_VAL              (C_SINITB_VAL),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_USE_ECC                 (C_USE_ECC),
+    .C_USE_RAMB16BWER_RST_BHV  (C_USE_RAMB16BWER_RST_BHV),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WEB_WIDTH               (C_WEB_WIDTH),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_XDEVICEFAMILY           (C_XDEVICEFAMILY)
+    ) blk_mem_gen_v2_4_dut (
+    .DINA       (DINA),
+    .DINB       (DINB),
+    .ADDRA      (ADDRA),
+    .ADDRB      (ADDRB),
+    .ENA        (ENA),
+    .ENB        (ENB),
+    .REGCEA     (REGCEA),
+    .REGCEB     (REGCEB),
+    .WEA        (WEA),
+    .WEB        (WEB),
+    .SSRA       (SSRA),
+    .SSRB       (SSRB),
+    .CLKA       (CLKA),
+    .CLKB       (CLKB),
+    .DOUTA      (DOUTA),
+    .DOUTB      (DOUTB),
+    .DBITERR    (DBITERR),
+    .SBITERR    (SBITERR)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_5_xst.v

@@ -0,0 +1,199 @@
+/******************************************************************************
+ *
+ * Block Memory Generator Core - Block Memory Behavioral Model
+ *
+ * Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
+ * This text/file contains proprietary, confidential
+ * information of Xilinx, Inc., is distributed under
+ * license from Xilinx, Inc., and may be used, copied
+ * and/or disclosed only pursuant to the terms of a valid
+ * license agreement with Xilinx, Inc. Xilinx hereby
+ * grants you a license to use this text/file solely for
+ * design, simulation, implementation and creation of
+ * design files limited to Xilinx devices or technologies.
+ * Use with non-Xilinx devices or technologies is expressly
+ * prohibited and immediately terminates your license unless
+ * covered by a separate agreement.
+ *
+ * Xilinx is providing this design, code, or information
+ * "as-is" solely for use in developing programs and
+ * solutions for Xilinx devices, with no obligation on the
+ * part of Xilinx to provide support. By providing this design,
+ * code, or information as one possible implementation of
+ * this feature, application or standard, Xilinx is making no
+ * representation that this implementation is free from any
+ * claims of infringement. You are responsible for obtaining
+ * any rights you may require for your implementation.
+ * Xilinx expressly disclaims any warranty whatsoever with
+ * respect to the adequacy of the implementation, including
+ * but not limited to any warranties or representations that this
+ * implementation is free from claims of infringement, implied
+ * warranties of merchantability or fitness for a particular
+ * purpose.
+ *
+ * Xilinx products are not intended for use in life support
+ * appliances, devices, or systems. Use in such applications is
+ * expressly prohibited.
+ *
+ * Any modifications that are made to the Source Code are
+ * done at the user's sole risk and will be unsupported.
+ * The Xilinx Support Hotline does not have access to source
+ * code and therefore cannot answer specific questions related
+ * to source HDL. The Xilinx Hotline support of original source
+ * code IP shall only address issues and questions related
+ * to the standard Netlist version of the core (and thus
+ * indirectly, the original core source).
+ *
+ * This copyright and support notice must be retained as part
+ * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc.
+ * All rights reserved.
+ *
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V2_5.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V2_5_xst
+  #(parameter C_ADDRA_WIDTH             = 5,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_ALGORITHM               = 1,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0,
+    parameter C_FAMILY           = "virtex5",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_HAS_SSRA                = 0,
+    parameter C_HAS_SSRB                = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_MEM_TYPE                = 2,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_SINITA_VAL              = "0",
+    parameter C_SINITB_VAL              = "0",
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_USE_RAMB16BWER_RST_BHV  = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_XDEVICEFAMILY           = "virtex5"
+)
+  (input                       CLKA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input                       SSRA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input                       SSRB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   output                      DBITERR,
+   output                      SBITERR);
+
+  BLK_MEM_GEN_V2_5
+  #(
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE),
+    .C_FAMILY                  (C_FAMILY),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_MEM_OUTPUT_REGS_A   (C_HAS_MEM_OUTPUT_REGS_A),
+    .C_HAS_MEM_OUTPUT_REGS_B   (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A   (C_HAS_MUX_OUTPUT_REGS_A),
+    .C_HAS_MUX_OUTPUT_REGS_B   (C_HAS_MUX_OUTPUT_REGS_B),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_HAS_SSRA                (C_HAS_SSRA),
+    .C_HAS_SSRB                (C_HAS_SSRB),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_SINITA_VAL              (C_SINITA_VAL),
+    .C_SINITB_VAL              (C_SINITB_VAL),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_USE_ECC                 (C_USE_ECC),
+    .C_USE_RAMB16BWER_RST_BHV  (C_USE_RAMB16BWER_RST_BHV),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WEB_WIDTH               (C_WEB_WIDTH),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_XDEVICEFAMILY           (C_XDEVICEFAMILY)
+    ) blk_mem_gen_v2_5_dut (
+    .DINA       (DINA),
+    .DINB       (DINB),
+    .ADDRA      (ADDRA),
+    .ADDRB      (ADDRB),
+    .ENA        (ENA),
+    .ENB        (ENB),
+    .REGCEA     (REGCEA),
+    .REGCEB     (REGCEB),
+    .WEA        (WEA),
+    .WEB        (WEB),
+    .SSRA       (SSRA),
+    .SSRB       (SSRB),
+    .CLKA       (CLKA),
+    .CLKB       (CLKB),
+    .DOUTA      (DOUTA),
+    .DOUTB      (DOUTB),
+    .DBITERR    (DBITERR),
+    .SBITERR    (SBITERR)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_6_xst.v

@@ -0,0 +1,201 @@
+/******************************************************************************
+ *
+ * Block Memory Generator Core - Block Memory Behavioral Model
+ *
+ * Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
+ * This text/file contains proprietary, confidential
+ * information of Xilinx, Inc., is distributed under
+ * license from Xilinx, Inc., and may be used, copied
+ * and/or disclosed only pursuant to the terms of a valid
+ * license agreement with Xilinx, Inc. Xilinx hereby
+ * grants you a license to use this text/file solely for
+ * design, simulation, implementation and creation of
+ * design files limited to Xilinx devices or technologies.
+ * Use with non-Xilinx devices or technologies is expressly
+ * prohibited and immediately terminates your license unless
+ * covered by a separate agreement.
+ *
+ * Xilinx is providing this design, code, or information
+ * "as-is" solely for use in developing programs and
+ * solutions for Xilinx devices, with no obligation on the
+ * part of Xilinx to provide support. By providing this design,
+ * code, or information as one possible implementation of
+ * this feature, application or standard, Xilinx is making no
+ * representation that this implementation is free from any
+ * claims of infringement. You are responsible for obtaining
+ * any rights you may require for your implementation.
+ * Xilinx expressly disclaims any warranty whatsoever with
+ * respect to the adequacy of the implementation, including
+ * but not limited to any warranties or representations that this
+ * implementation is free from claims of infringement, implied
+ * warranties of merchantability or fitness for a particular
+ * purpose.
+ *
+ * Xilinx products are not intended for use in life support
+ * appliances, devices, or systems. Use in such applications is
+ * expressly prohibited.
+ *
+ * Any modifications that are made to the Source Code are
+ * done at the user's sole risk and will be unsupported.
+ * The Xilinx Support Hotline does not have access to source
+ * code and therefore cannot answer specific questions related
+ * to source HDL. The Xilinx Hotline support of original source
+ * code IP shall only address issues and questions related
+ * to the standard Netlist version of the core (and thus
+ * indirectly, the original core source).
+ *
+ * This copyright and support notice must be retained as part
+ * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc.
+ * All rights reserved.
+ *
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V2_6.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V2_6_xst
+  #(parameter C_ADDRA_WIDTH             = 5,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_ALGORITHM               = 1,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0,
+    parameter C_FAMILY           = "virtex5",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,
+    parameter C_MUX_PIPELINE_STAGES     = 0,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_HAS_SSRA                = 0,
+    parameter C_HAS_SSRB                = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_MEM_TYPE                = 2,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_SINITA_VAL              = "0",
+    parameter C_SINITB_VAL              = "0",
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_USE_RAMB16BWER_RST_BHV  = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_XDEVICEFAMILY           = "virtex5"
+)
+  (input                       CLKA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input                       SSRA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input                       SSRB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   output                      DBITERR,
+   output                      SBITERR);
+
+  BLK_MEM_GEN_V2_6
+  #(
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE),
+    .C_FAMILY                  (C_FAMILY),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_MEM_OUTPUT_REGS_A   (C_HAS_MEM_OUTPUT_REGS_A),
+    .C_HAS_MEM_OUTPUT_REGS_B   (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A   (C_HAS_MUX_OUTPUT_REGS_A),
+    .C_HAS_MUX_OUTPUT_REGS_B   (C_HAS_MUX_OUTPUT_REGS_B),
+    .C_MUX_PIPELINE_STAGES     (C_MUX_PIPELINE_STAGES),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_HAS_SSRA                (C_HAS_SSRA),
+    .C_HAS_SSRB                (C_HAS_SSRB),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_SINITA_VAL              (C_SINITA_VAL),
+    .C_SINITB_VAL              (C_SINITB_VAL),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_USE_ECC                 (C_USE_ECC),
+    .C_USE_RAMB16BWER_RST_BHV  (C_USE_RAMB16BWER_RST_BHV),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WEB_WIDTH               (C_WEB_WIDTH),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_XDEVICEFAMILY           (C_XDEVICEFAMILY)
+    ) blk_mem_gen_v2_6_dut (
+    .DINA       (DINA),
+    .DINB       (DINB),
+    .ADDRA      (ADDRA),
+    .ADDRB      (ADDRB),
+    .ENA        (ENA),
+    .ENB        (ENB),
+    .REGCEA     (REGCEA),
+    .REGCEB     (REGCEB),
+    .WEA        (WEA),
+    .WEB        (WEB),
+    .SSRA       (SSRA),
+    .SSRB       (SSRB),
+    .CLKA       (CLKA),
+    .CLKB       (CLKB),
+    .DOUTA      (DOUTA),
+    .DOUTB      (DOUTB),
+    .DBITERR    (DBITERR),
+    .SBITERR    (SBITERR)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_7_xst.v

@@ -0,0 +1,209 @@
+/******************************************************************************
+ *
+ * Block Memory Generator Core - Block Memory Behavioral Model
+ *
+ * Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
+ * This text/file contains proprietary, confidential
+ * information of Xilinx, Inc., is distributed under
+ * license from Xilinx, Inc., and may be used, copied
+ * and/or disclosed only pursuant to the terms of a valid
+ * license agreement with Xilinx, Inc. Xilinx hereby
+ * grants you a license to use this text/file solely for
+ * design, simulation, implementation and creation of
+ * design files limited to Xilinx devices or technologies.
+ * Use with non-Xilinx devices or technologies is expressly
+ * prohibited and immediately terminates your license unless
+ * covered by a separate agreement.
+ *
+ * Xilinx is providing this design, code, or information
+ * "as-is" solely for use in developing programs and
+ * solutions for Xilinx devices, with no obligation on the
+ * part of Xilinx to provide support. By providing this design,
+ * code, or information as one possible implementation of
+ * this feature, application or standard, Xilinx is making no
+ * representation that this implementation is free from any
+ * claims of infringement. You are responsible for obtaining
+ * any rights you may require for your implementation.
+ * Xilinx expressly disclaims any warranty whatsoever with
+ * respect to the adequacy of the implementation, including
+ * but not limited to any warranties or representations that this
+ * implementation is free from claims of infringement, implied
+ * warranties of merchantability or fitness for a particular
+ * purpose.
+ *
+ * Xilinx products are not intended for use in life support
+ * appliances, devices, or systems. Use in such applications is
+ * expressly prohibited.
+ *
+ * Any modifications that are made to the Source Code are
+ * done at the user's sole risk and will be unsupported.
+ * The Xilinx Support Hotline does not have access to source
+ * code and therefore cannot answer specific questions related
+ * to source HDL. The Xilinx Hotline support of original source
+ * code IP shall only address issues and questions related
+ * to the standard Netlist version of the core (and thus
+ * indirectly, the original core source).
+ *
+ * This copyright and support notice must be retained as part
+ * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc.
+ * All rights reserved.
+ *
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V2_7.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V2_7_xst
+  #(parameter C_ADDRA_WIDTH             = 5,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_ALGORITHM               = 1,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0,
+    parameter C_FAMILY           = "virtex5",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,
+    parameter C_MUX_PIPELINE_STAGES     = 0,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_HAS_SSRA                = 0,
+    parameter C_HAS_SSRB                = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_MEM_TYPE                = 2,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_SINITA_VAL              = "0",
+    parameter C_SINITB_VAL              = "0",
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_USE_RAMB16BWER_RST_BHV  = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_XDEVICEFAMILY           = "virtex5",
+    parameter C_ELABORATION_DIR         = ""
+)
+  (input                       CLKA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input                       SSRA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input                       SSRB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   output                      DBITERR,
+   output                      SBITERR);
+
+
+// Note: C_ELABORATION_DIR parameter is only used in synthesis 
+// (and doesn't get mentioned in the instantiation template Coregen generates). 
+// This wrapper file has to work both in simulation and synthesis. So, this 
+// parameter exists. It is not used by the behavioral model 
+// (BLK_MEM_GEN_V2_7.vhd)
+  
+  BLK_MEM_GEN_V2_7
+  #(
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE),
+    .C_FAMILY                  (C_FAMILY),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_MEM_OUTPUT_REGS_A   (C_HAS_MEM_OUTPUT_REGS_A),
+    .C_HAS_MEM_OUTPUT_REGS_B   (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A   (C_HAS_MUX_OUTPUT_REGS_A),
+    .C_HAS_MUX_OUTPUT_REGS_B   (C_HAS_MUX_OUTPUT_REGS_B),
+    .C_MUX_PIPELINE_STAGES     (C_MUX_PIPELINE_STAGES),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_HAS_SSRA                (C_HAS_SSRA),
+    .C_HAS_SSRB                (C_HAS_SSRB),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_SINITA_VAL              (C_SINITA_VAL),
+    .C_SINITB_VAL              (C_SINITB_VAL),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_USE_ECC                 (C_USE_ECC),
+    .C_USE_RAMB16BWER_RST_BHV  (C_USE_RAMB16BWER_RST_BHV),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WEB_WIDTH               (C_WEB_WIDTH),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_XDEVICEFAMILY           (C_XDEVICEFAMILY)
+    ) blk_mem_gen_v2_7_dut (
+    .DINA       (DINA),
+    .DINB       (DINB),
+    .ADDRA      (ADDRA),
+    .ADDRB      (ADDRB),
+    .ENA        (ENA),
+    .ENB        (ENB),
+    .REGCEA     (REGCEA),
+    .REGCEB     (REGCEB),
+    .WEA        (WEA),
+    .WEB        (WEB),
+    .SSRA       (SSRA),
+    .SSRB       (SSRB),
+    .CLKA       (CLKA),
+    .CLKB       (CLKB),
+    .DOUTA      (DOUTA),
+    .DOUTB      (DOUTB),
+    .DBITERR    (DBITERR),
+    .SBITERR    (SBITERR)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_1_xst.v

@@ -0,0 +1,224 @@
+/******************************************************************************
+-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V3_1.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V3_1_xst
+  #(parameter C_FAMILY                  = "virtex5",
+    parameter C_XDEVICEFAMILY           = "virtex5",
+    parameter C_ELABORATION_DIR         = "",
+    parameter C_MEM_TYPE                = 2,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_ALGORITHM               = 1,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_RST_TYPE                = "SYNC",
+    parameter C_HAS_RSTA                = 0,
+    parameter C_RST_PRIORITY_A          = "CE",
+    parameter C_RSTRAM_A                = 0,
+    parameter C_INITA_VAL              = "0",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_ADDRA_WIDTH             = 5,
+    parameter C_HAS_RSTB                = 0,
+    parameter C_RST_PRIORITY_B          = "CE",
+    parameter C_RSTRAM_B                = 0,
+    parameter C_INITB_VAL              = "0",
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,
+    parameter C_MUX_PIPELINE_STAGES     = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_HAS_INJECTERR           = 0,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0
+)
+  (input                       CLKA,
+   input                       RSTA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input                       RSTB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   input                       INJECTSBITERR,
+   input                       INJECTDBITERR,
+   output                      SBITERR,
+   output                      DBITERR,
+   output [C_ADDRB_WIDTH-1:0]               RDADDRECC
+);
+
+
+// Note: C_ELABORATION_DIR parameter is only used in synthesis 
+// (and doesn't get mentioned in the instantiation template Coregen generates). 
+// This wrapper file has to work both in simulation and synthesis. So, this 
+// parameter exists. It is not used by the behavioral model 
+// (BLK_MEM_GEN_V3_1.vhd)
+  
+  BLK_MEM_GEN_V3_1
+  #(
+    .C_CORENAME                ("blk_mem_gen_v3_1"),
+    .C_FAMILY                  (C_FAMILY),
+    .C_XDEVICEFAMILY           (C_XDEVICEFAMILY),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_RST_TYPE                (C_RST_TYPE),
+    .C_HAS_RSTA                (C_HAS_RSTA),
+    .C_RST_PRIORITY_A          (C_RST_PRIORITY_A),
+    .C_RSTRAM_A                (C_RSTRAM_A),
+    .C_INITA_VAL               (C_INITA_VAL),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_HAS_RSTB                (C_HAS_RSTB),
+    .C_RST_PRIORITY_B          (C_RST_PRIORITY_B),
+    .C_RSTRAM_B                (C_RSTRAM_B),
+    .C_INITB_VAL               (C_INITB_VAL),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_WEB_WIDTH               (C_WEB_WIDTH),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_HAS_MEM_OUTPUT_REGS_A   (C_HAS_MEM_OUTPUT_REGS_A),
+    .C_HAS_MEM_OUTPUT_REGS_B   (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A   (C_HAS_MUX_OUTPUT_REGS_A),
+    .C_HAS_MUX_OUTPUT_REGS_B   (C_HAS_MUX_OUTPUT_REGS_B),
+    .C_MUX_PIPELINE_STAGES     (C_MUX_PIPELINE_STAGES),
+    .C_USE_ECC                 (C_USE_ECC),
+    .C_HAS_INJECTERR           (C_HAS_INJECTERR),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE)
+    ) blk_mem_gen_v3_1_dut (
+    .CLKA          (CLKA),
+    .RSTA          (RSTA),
+    .ENA           (ENA),
+    .REGCEA        (REGCEA),
+    .WEA           (WEA),
+    .ADDRA         (ADDRA),
+    .DINA          (DINA),
+    .DOUTA         (DOUTA),
+    .CLKB          (CLKB),
+    .RSTB          (RSTB),
+    .ENB           (ENB),
+    .REGCEB        (REGCEB),
+    .WEB           (WEB),
+    .ADDRB         (ADDRB),
+    .DINB          (DINB),
+    .DOUTB         (DOUTB),
+    .INJECTSBITERR (INJECTSBITERR),
+    .INJECTDBITERR (INJECTDBITERR),
+    .SBITERR       (SBITERR),
+    .DBITERR       (DBITERR),
+    .RDADDRECC     (RDADDRECC)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_2_xst.v

@@ -0,0 +1,224 @@
+/******************************************************************************
+-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V3_2.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V3_2_xst
+  #(parameter C_FAMILY                  = "virtex5",
+    parameter C_XDEVICEFAMILY           = "virtex5",
+    parameter C_ELABORATION_DIR         = "",
+    parameter C_MEM_TYPE                = 2,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_ALGORITHM               = 1,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_RST_TYPE                = "SYNC",
+    parameter C_HAS_RSTA                = 0,
+    parameter C_RST_PRIORITY_A          = "CE",
+    parameter C_RSTRAM_A                = 0,
+    parameter C_INITA_VAL              = "0",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_ADDRA_WIDTH             = 5,
+    parameter C_HAS_RSTB                = 0,
+    parameter C_RST_PRIORITY_B          = "CE",
+    parameter C_RSTRAM_B                = 0,
+    parameter C_INITB_VAL              = "0",
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,
+    parameter C_MUX_PIPELINE_STAGES     = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_HAS_INJECTERR           = 0,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0
+)
+  (input                       CLKA,
+   input                       RSTA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input                       RSTB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   input                       INJECTSBITERR,
+   input                       INJECTDBITERR,
+   output                      SBITERR,
+   output                      DBITERR,
+   output [C_ADDRB_WIDTH-1:0]               RDADDRECC
+);
+
+
+// Note: C_ELABORATION_DIR parameter is only used in synthesis 
+// (and doesn't get mentioned in the instantiation template Coregen generates). 
+// This wrapper file has to work both in simulation and synthesis. So, this 
+// parameter exists. It is not used by the behavioral model 
+// (BLK_MEM_GEN_V3_2.vhd)
+  
+  BLK_MEM_GEN_V3_2
+  #(
+    .C_CORENAME                ("blk_mem_gen_v3_2"),
+    .C_FAMILY                  (C_FAMILY),
+    .C_XDEVICEFAMILY           (C_XDEVICEFAMILY),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_RST_TYPE                (C_RST_TYPE),
+    .C_HAS_RSTA                (C_HAS_RSTA),
+    .C_RST_PRIORITY_A          (C_RST_PRIORITY_A),
+    .C_RSTRAM_A                (C_RSTRAM_A),
+    .C_INITA_VAL               (C_INITA_VAL),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_HAS_RSTB                (C_HAS_RSTB),
+    .C_RST_PRIORITY_B          (C_RST_PRIORITY_B),
+    .C_RSTRAM_B                (C_RSTRAM_B),
+    .C_INITB_VAL               (C_INITB_VAL),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_WEB_WIDTH               (C_WEB_WIDTH),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_HAS_MEM_OUTPUT_REGS_A   (C_HAS_MEM_OUTPUT_REGS_A),
+    .C_HAS_MEM_OUTPUT_REGS_B   (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A   (C_HAS_MUX_OUTPUT_REGS_A),
+    .C_HAS_MUX_OUTPUT_REGS_B   (C_HAS_MUX_OUTPUT_REGS_B),
+    .C_MUX_PIPELINE_STAGES     (C_MUX_PIPELINE_STAGES),
+    .C_USE_ECC                 (C_USE_ECC),
+    .C_HAS_INJECTERR           (C_HAS_INJECTERR),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE)
+    ) blk_mem_gen_v3_2_dut (
+    .CLKA          (CLKA),
+    .RSTA          (RSTA),
+    .ENA           (ENA),
+    .REGCEA        (REGCEA),
+    .WEA           (WEA),
+    .ADDRA         (ADDRA),
+    .DINA          (DINA),
+    .DOUTA         (DOUTA),
+    .CLKB          (CLKB),
+    .RSTB          (RSTB),
+    .ENB           (ENB),
+    .REGCEB        (REGCEB),
+    .WEB           (WEB),
+    .ADDRB         (ADDRB),
+    .DINB          (DINB),
+    .DOUTB         (DOUTB),
+    .INJECTSBITERR (INJECTSBITERR),
+    .INJECTDBITERR (INJECTDBITERR),
+    .SBITERR       (SBITERR),
+    .DBITERR       (DBITERR),
+    .RDADDRECC     (RDADDRECC)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_3_xst.v

@@ -0,0 +1,224 @@
+/******************************************************************************
+-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V3_3.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V3_3_xst
+  #(parameter C_FAMILY                  = "virtex5",
+    parameter C_XDEVICEFAMILY           = "virtex5",
+    parameter C_ELABORATION_DIR         = "",
+    parameter C_MEM_TYPE                = 2,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_ALGORITHM               = 1,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_RST_TYPE                = "SYNC",
+    parameter C_HAS_RSTA                = 0,
+    parameter C_RST_PRIORITY_A          = "CE",
+    parameter C_RSTRAM_A                = 0,
+    parameter C_INITA_VAL              = "0",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_ADDRA_WIDTH             = 5,
+    parameter C_HAS_RSTB                = 0,
+    parameter C_RST_PRIORITY_B          = "CE",
+    parameter C_RSTRAM_B                = 0,
+    parameter C_INITB_VAL              = "0",
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,
+    parameter C_MUX_PIPELINE_STAGES     = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_HAS_INJECTERR           = 0,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0
+)
+  (input                       CLKA,
+   input                       RSTA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input                       RSTB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   input                       INJECTSBITERR,
+   input                       INJECTDBITERR,
+   output                      SBITERR,
+   output                      DBITERR,
+   output [C_ADDRB_WIDTH-1:0]               RDADDRECC
+);
+
+
+// Note: C_ELABORATION_DIR parameter is only used in synthesis 
+// (and doesn't get mentioned in the instantiation template Coregen generates). 
+// This wrapper file has to work both in simulation and synthesis. So, this 
+// parameter exists. It is not used by the behavioral model 
+// (BLK_MEM_GEN_V3_3.vhd)
+  
+  BLK_MEM_GEN_V3_3
+  #(
+    .C_CORENAME                ("blk_mem_gen_v3_3"),
+    .C_FAMILY                  (C_FAMILY),
+    .C_XDEVICEFAMILY           (C_XDEVICEFAMILY),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_RST_TYPE                (C_RST_TYPE),
+    .C_HAS_RSTA                (C_HAS_RSTA),
+    .C_RST_PRIORITY_A          (C_RST_PRIORITY_A),
+    .C_RSTRAM_A                (C_RSTRAM_A),
+    .C_INITA_VAL               (C_INITA_VAL),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_HAS_RSTB                (C_HAS_RSTB),
+    .C_RST_PRIORITY_B          (C_RST_PRIORITY_B),
+    .C_RSTRAM_B                (C_RSTRAM_B),
+    .C_INITB_VAL               (C_INITB_VAL),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_WEB_WIDTH               (C_WEB_WIDTH),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_HAS_MEM_OUTPUT_REGS_A   (C_HAS_MEM_OUTPUT_REGS_A),
+    .C_HAS_MEM_OUTPUT_REGS_B   (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A   (C_HAS_MUX_OUTPUT_REGS_A),
+    .C_HAS_MUX_OUTPUT_REGS_B   (C_HAS_MUX_OUTPUT_REGS_B),
+    .C_MUX_PIPELINE_STAGES     (C_MUX_PIPELINE_STAGES),
+    .C_USE_ECC                 (C_USE_ECC),
+    .C_HAS_INJECTERR           (C_HAS_INJECTERR),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE)
+    ) blk_mem_gen_v3_3_dut (
+    .CLKA          (CLKA),
+    .RSTA          (RSTA),
+    .ENA           (ENA),
+    .REGCEA        (REGCEA),
+    .WEA           (WEA),
+    .ADDRA         (ADDRA),
+    .DINA          (DINA),
+    .DOUTA         (DOUTA),
+    .CLKB          (CLKB),
+    .RSTB          (RSTB),
+    .ENB           (ENB),
+    .REGCEB        (REGCEB),
+    .WEB           (WEB),
+    .ADDRB         (ADDRB),
+    .DINB          (DINB),
+    .DOUTB         (DOUTB),
+    .INJECTSBITERR (INJECTSBITERR),
+    .INJECTDBITERR (INJECTDBITERR),
+    .SBITERR       (SBITERR),
+    .DBITERR       (DBITERR),
+    .RDADDRECC     (RDADDRECC)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_1_xst.v

@@ -0,0 +1,238 @@
+/******************************************************************************
+-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V4_1.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V4_1_xst
+  #(parameter C_FAMILY                  = "virtex5",
+    parameter C_XDEVICEFAMILY           = "virtex5",
+    parameter C_ELABORATION_DIR         = "",
+    parameter C_MEM_TYPE                = 2,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_ALGORITHM               = 1,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_RST_TYPE                = "SYNC",
+    parameter C_HAS_RSTA                = 0,
+    parameter C_RST_PRIORITY_A          = "CE",
+    parameter C_RSTRAM_A                = 0,
+    parameter C_INITA_VAL              = "0",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_ADDRA_WIDTH             = 5,
+    parameter C_HAS_RSTB                = 0,
+    parameter C_RST_PRIORITY_B          = "CE",
+    parameter C_RSTRAM_B                = 0,
+    parameter C_INITB_VAL              = "0",
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
+    parameter C_HAS_SOFTECC_INPUT_REGS_B = 0,
+    parameter C_HAS_SOFTECC_OUTPUT_REGS_A= 0,
+    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
+    parameter C_MUX_PIPELINE_STAGES     = 0,
+    parameter C_USE_SOFTECC             = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_HAS_INJECTERR           = 0,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0
+)
+  (input                       CLKA,
+   input                       RSTA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input                       RSTB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   input                       INJECTSBITERR,
+   input                       INJECTDBITERR,
+   output                      SBITERR,
+   output                      DBITERR,
+   output [C_ADDRB_WIDTH-1:0]               RDADDRECC
+);
+
+
+// Note: C_ELABORATION_DIR parameter is only used in synthesis 
+// (and doesn't get mentioned in the instantiation template Coregen generates). 
+// This wrapper file has to work both in simulation and synthesis. So, this 
+// parameter exists. It is not used by the behavioral model 
+// (BLK_MEM_GEN_V4_1.vhd)
+
+    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY=="virtex6l" ? "virtex6" : (C_FAMILY=="spartan6l" ? "spartan6" : (C_FAMILY=="aspartan6" ? "spartan6" : C_FAMILY)));
+  
+  BLK_MEM_GEN_V4_1
+  #(
+    .C_CORENAME                ("blk_mem_gen_v4_1"),
+//    .C_FAMILY                  (C_FAMILY),
+//    .C_FAMILY                  (C_FAMILY=="virtex6l" ? virtex6 : (C_FAMILY=="spartan6l" ? spartan6 : (C_FAMILY=="aspartan6" ? spartan6 : C_FAMILY))),
+    .C_FAMILY                  (C_FAMILY_LOCALPARAM),
+    .C_XDEVICEFAMILY           (C_XDEVICEFAMILY),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_RST_TYPE                (C_RST_TYPE),
+    .C_HAS_RSTA                (C_HAS_RSTA),
+    .C_RST_PRIORITY_A          (C_RST_PRIORITY_A),
+    .C_RSTRAM_A                (C_RSTRAM_A),
+    .C_INITA_VAL               (C_INITA_VAL),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_HAS_RSTB                (C_HAS_RSTB),
+    .C_RST_PRIORITY_B          (C_RST_PRIORITY_B),
+    .C_RSTRAM_B                (C_RSTRAM_B),
+    .C_INITB_VAL               (C_INITB_VAL),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_WEB_WIDTH               (C_WEB_WIDTH),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_HAS_MEM_OUTPUT_REGS_A   (C_HAS_MEM_OUTPUT_REGS_A),
+    .C_HAS_MEM_OUTPUT_REGS_B   (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A   (C_HAS_MUX_OUTPUT_REGS_A),
+    .C_HAS_MUX_OUTPUT_REGS_B   (C_HAS_MUX_OUTPUT_REGS_B),
+    .C_HAS_SOFTECC_INPUT_REGS_A   (C_HAS_SOFTECC_INPUT_REGS_A),
+    .C_HAS_SOFTECC_INPUT_REGS_B   (C_HAS_SOFTECC_INPUT_REGS_B),
+    .C_HAS_SOFTECC_OUTPUT_REGS_A  (C_HAS_SOFTECC_OUTPUT_REGS_A),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),
+    .C_MUX_PIPELINE_STAGES     (C_MUX_PIPELINE_STAGES),
+    .C_USE_SOFTECC             (C_USE_SOFTECC),
+    .C_USE_ECC                 (C_USE_ECC),
+    .C_HAS_INJECTERR           (C_HAS_INJECTERR),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE)
+    ) blk_mem_gen_v4_1_dut (
+    .CLKA          (CLKA),
+    .RSTA          (RSTA),
+    .ENA           (ENA),
+    .REGCEA        (REGCEA),
+    .WEA           (WEA),
+    .ADDRA         (ADDRA),
+    .DINA          (DINA),
+    .DOUTA         (DOUTA),
+    .CLKB          (CLKB),
+    .RSTB          (RSTB),
+    .ENB           (ENB),
+    .REGCEB        (REGCEB),
+    .WEB           (WEB),
+    .ADDRB         (ADDRB),
+    .DINB          (DINB),
+    .DOUTB         (DOUTB),
+    .INJECTSBITERR (INJECTSBITERR),
+    .INJECTDBITERR (INJECTDBITERR),
+    .SBITERR       (SBITERR),
+    .DBITERR       (DBITERR),
+    .RDADDRECC     (RDADDRECC)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_2_xst.v

@@ -0,0 +1,234 @@
+/******************************************************************************
+-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+ *****************************************************************************
+ *
+ * Filename: BLK_MEM_GEN_V4_2.v
+ *
+ * Description:
+ *   This file is the Verilog behvarial model for the
+ *       Block Memory Generator Core.
+ *
+ *****************************************************************************
+ * Author: Xilinx
+ *
+ * History: September 6, 2005 Initial revision
+ *****************************************************************************/
+`timescale 1ps/1ps
+
+module BLK_MEM_GEN_V4_2_xst
+  #(parameter C_FAMILY                  = "virtex5",
+    parameter C_XDEVICEFAMILY           = "virtex5",
+    parameter C_ELABORATION_DIR         = "",
+    parameter C_MEM_TYPE                = 2,
+    parameter C_BYTE_SIZE               = 9,
+    parameter C_ALGORITHM               = 1,
+    parameter C_PRIM_TYPE               = 3,
+    parameter C_LOAD_INIT_FILE          = 0,
+    parameter C_INIT_FILE_NAME          = "",
+    parameter C_USE_DEFAULT_DATA        = 0,
+    parameter C_DEFAULT_DATA            = "0",
+    parameter C_RST_TYPE                = "SYNC",
+    parameter C_HAS_RSTA                = 0,
+    parameter C_RST_PRIORITY_A          = "CE",
+    parameter C_RSTRAM_A                = 0,
+    parameter C_INITA_VAL              = "0",
+    parameter C_HAS_ENA                 = 1,
+    parameter C_HAS_REGCEA              = 0,
+    parameter C_USE_BYTE_WEA            = 0,
+    parameter C_WEA_WIDTH               = 1,
+    parameter C_WRITE_MODE_A            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_A           = 32,
+    parameter C_READ_WIDTH_A            = 32,
+    parameter C_WRITE_DEPTH_A           = 64,
+    parameter C_READ_DEPTH_A            = 64,
+    parameter C_ADDRA_WIDTH             = 5,
+    parameter C_HAS_RSTB                = 0,
+    parameter C_RST_PRIORITY_B          = "CE",
+    parameter C_RSTRAM_B                = 0,
+    parameter C_INITB_VAL              = "0",
+    parameter C_HAS_ENB                 = 1,
+    parameter C_HAS_REGCEB              = 0,
+    parameter C_USE_BYTE_WEB            = 0,
+    parameter C_WEB_WIDTH               = 1,
+    parameter C_WRITE_MODE_B            = "WRITE_FIRST",
+    parameter C_WRITE_WIDTH_B           = 32,
+    parameter C_READ_WIDTH_B            = 32,
+    parameter C_WRITE_DEPTH_B           = 64,
+    parameter C_READ_DEPTH_B            = 64,
+    parameter C_ADDRB_WIDTH             = 5,
+    parameter C_HAS_MEM_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MEM_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_A   = 0,
+    parameter C_HAS_MUX_OUTPUT_REGS_B   = 0,
+    parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
+    parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
+    parameter C_MUX_PIPELINE_STAGES     = 0,
+    parameter C_USE_SOFTECC             = 0,
+    parameter C_USE_ECC                 = 0,
+    parameter C_HAS_INJECTERR           = 0,
+    parameter C_SIM_COLLISION_CHECK     = "NONE",
+    parameter C_COMMON_CLK              = 1,
+    parameter C_DISABLE_WARN_BHV_COLL   = 0,
+    parameter C_DISABLE_WARN_BHV_RANGE  = 0
+)
+  (input                       CLKA,
+   input                       RSTA,
+   input                       ENA,
+   input                       REGCEA,
+   input [C_WEA_WIDTH-1:0]     WEA,
+   input [C_ADDRA_WIDTH-1:0]   ADDRA,
+   input [C_WRITE_WIDTH_A-1:0] DINA,
+   output [C_READ_WIDTH_A-1:0] DOUTA,
+   input                       CLKB,
+   input                       RSTB,
+   input                       ENB,
+   input                       REGCEB,
+   input [C_WEB_WIDTH-1:0]     WEB,
+   input [C_ADDRB_WIDTH-1:0]   ADDRB,
+   input [C_WRITE_WIDTH_B-1:0] DINB,
+   output [C_READ_WIDTH_B-1:0] DOUTB,
+   input                       INJECTSBITERR,
+   input                       INJECTDBITERR,
+   output                      SBITERR,
+   output                      DBITERR,
+   output [C_ADDRB_WIDTH-1:0]               RDADDRECC
+);
+
+
+// Note: C_ELABORATION_DIR parameter is only used in synthesis 
+// (and doesn't get mentioned in the instantiation template Coregen generates). 
+// This wrapper file has to work both in simulation and synthesis. So, this 
+// parameter exists. It is not used by the behavioral model 
+// (BLK_MEM_GEN_V4_2.vhd)
+
+    localparam C_FAMILY_LOCALPARAM =      (C_FAMILY=="virtex6l" ? "virtex6" : (C_FAMILY=="spartan6l" ? "spartan6" : (C_FAMILY=="aspartan6" ? "spartan6" : C_FAMILY)));
+  
+  BLK_MEM_GEN_V4_2
+  #(
+    .C_CORENAME                ("blk_mem_gen_v4_2"),
+//    .C_FAMILY                  (C_FAMILY),
+//    .C_FAMILY                  (C_FAMILY=="virtex6l" ? virtex6 : (C_FAMILY=="spartan6l" ? spartan6 : (C_FAMILY=="aspartan6" ? spartan6 : C_FAMILY))),
+    .C_FAMILY                  (C_FAMILY_LOCALPARAM),
+    .C_XDEVICEFAMILY           (C_XDEVICEFAMILY),
+    .C_MEM_TYPE                (C_MEM_TYPE),
+    .C_BYTE_SIZE               (C_BYTE_SIZE),
+    .C_ALGORITHM               (C_ALGORITHM),
+    .C_PRIM_TYPE               (C_PRIM_TYPE),
+    .C_LOAD_INIT_FILE          (C_LOAD_INIT_FILE),
+    .C_INIT_FILE_NAME          (C_INIT_FILE_NAME),
+    .C_USE_DEFAULT_DATA        (C_USE_DEFAULT_DATA),
+    .C_DEFAULT_DATA            (C_DEFAULT_DATA),
+    .C_RST_TYPE                (C_RST_TYPE),
+    .C_HAS_RSTA                (C_HAS_RSTA),
+    .C_RST_PRIORITY_A          (C_RST_PRIORITY_A),
+    .C_RSTRAM_A                (C_RSTRAM_A),
+    .C_INITA_VAL               (C_INITA_VAL),
+    .C_HAS_ENA                 (C_HAS_ENA),
+    .C_HAS_REGCEA              (C_HAS_REGCEA),
+    .C_USE_BYTE_WEA            (C_USE_BYTE_WEA),
+    .C_WEA_WIDTH               (C_WEA_WIDTH),
+    .C_WRITE_MODE_A            (C_WRITE_MODE_A),
+    .C_WRITE_WIDTH_A           (C_WRITE_WIDTH_A),
+    .C_READ_WIDTH_A            (C_READ_WIDTH_A),
+    .C_WRITE_DEPTH_A           (C_WRITE_DEPTH_A),
+    .C_READ_DEPTH_A            (C_READ_DEPTH_A),
+    .C_ADDRA_WIDTH             (C_ADDRA_WIDTH),
+    .C_HAS_RSTB                (C_HAS_RSTB),
+    .C_RST_PRIORITY_B          (C_RST_PRIORITY_B),
+    .C_RSTRAM_B                (C_RSTRAM_B),
+    .C_INITB_VAL               (C_INITB_VAL),
+    .C_HAS_ENB                 (C_HAS_ENB),
+    .C_HAS_REGCEB              (C_HAS_REGCEB),
+    .C_USE_BYTE_WEB            (C_USE_BYTE_WEB),
+    .C_WEB_WIDTH               (C_WEB_WIDTH),
+    .C_WRITE_MODE_B            (C_WRITE_MODE_B),
+    .C_WRITE_WIDTH_B           (C_WRITE_WIDTH_B),
+    .C_READ_WIDTH_B            (C_READ_WIDTH_B),
+    .C_WRITE_DEPTH_B           (C_WRITE_DEPTH_B),
+    .C_READ_DEPTH_B            (C_READ_DEPTH_B),
+    .C_ADDRB_WIDTH             (C_ADDRB_WIDTH),
+    .C_HAS_MEM_OUTPUT_REGS_A   (C_HAS_MEM_OUTPUT_REGS_A),
+    .C_HAS_MEM_OUTPUT_REGS_B   (C_HAS_MEM_OUTPUT_REGS_B),
+    .C_HAS_MUX_OUTPUT_REGS_A   (C_HAS_MUX_OUTPUT_REGS_A),
+    .C_HAS_MUX_OUTPUT_REGS_B   (C_HAS_MUX_OUTPUT_REGS_B),
+    .C_HAS_SOFTECC_INPUT_REGS_A   (C_HAS_SOFTECC_INPUT_REGS_A),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B  (C_HAS_SOFTECC_OUTPUT_REGS_B),
+    .C_MUX_PIPELINE_STAGES     (C_MUX_PIPELINE_STAGES),
+    .C_USE_SOFTECC             (C_USE_SOFTECC),
+    .C_USE_ECC                 (C_USE_ECC),
+    .C_HAS_INJECTERR           (C_HAS_INJECTERR),
+    .C_SIM_COLLISION_CHECK     (C_SIM_COLLISION_CHECK),
+    .C_COMMON_CLK              (C_COMMON_CLK),
+    .C_DISABLE_WARN_BHV_COLL   (C_DISABLE_WARN_BHV_COLL),
+    .C_DISABLE_WARN_BHV_RANGE  (C_DISABLE_WARN_BHV_RANGE)
+    ) blk_mem_gen_v4_2_dut (
+    .CLKA          (CLKA),
+    .RSTA          (RSTA),
+    .ENA           (ENA),
+    .REGCEA        (REGCEA),
+    .WEA           (WEA),
+    .ADDRA         (ADDRA),
+    .DINA          (DINA),
+    .DOUTA         (DOUTA),
+    .CLKB          (CLKB),
+    .RSTB          (RSTB),
+    .ENB           (ENB),
+    .REGCEB        (REGCEB),
+    .WEB           (WEB),
+    .ADDRB         (ADDRB),
+    .DINB          (DINB),
+    .DOUTB         (DOUTB),
+    .INJECTSBITERR (INJECTSBITERR),
+    .INJECTDBITERR (INJECTDBITERR),
+    .SBITERR       (SBITERR),
+    .DBITERR       (DBITERR),
+    .RDADDRECC     (RDADDRECC)
+);
+
+endmodule
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V4_0.v

@@ -0,0 +1,629 @@
+/* $Id: C_ACCUM_V4_0.v,v 1.11 2008/09/08 20:05:45 akennedy Exp $
+--
+-- Filename - C_ACCUM_V4_0.v
+-- Author - Xilinx
+-- Creation - 15 July 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_ACCUM_V4_0 module
+*/
+
+
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_add 0
+`define c_sub 1
+`define c_add_sub 2
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}}
+
+module C_ACCUM_V4_0 (B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT,
+					  SCLR, SSET, SINIT, B_SIGNED, OVFL, C_OUT, B_OUT,
+					  Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q);
+
+	parameter C_ADD_MODE 		= `c_add;
+	parameter C_AINIT_VAL 		= "";
+	parameter C_BYPASS_ENABLE 	= `c_override;
+	parameter C_BYPASS_LOW 		= 0;
+	parameter C_B_CONSTANT 		= 0;
+	parameter C_B_TYPE 			= `c_unsigned;
+	parameter C_B_VALUE 		= "";
+	parameter C_B_WIDTH 		= 16;
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_ADD 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_BYPASS 		= 0;
+	parameter C_HAS_B_IN 		= 1;
+	parameter C_HAS_B_OUT 		= 0;
+	parameter C_HAS_B_SIGNED 	= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_C_IN 		= 1;
+	parameter C_HAS_C_OUT 		= 0;
+	parameter C_HAS_OVFL 		= 0;
+	parameter C_HAS_Q_B_OUT 	= 0;
+	parameter C_HAS_Q_C_OUT 	= 0;
+	parameter C_HAS_Q_OVFL 		= 0;
+	parameter C_HAS_S 			= 0; 
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HIGH_BIT 		= 15;
+	parameter C_LOW_BIT 		= 0;
+	parameter C_OUT_WIDTH 		= 16;
+	parameter C_PIPE_STAGES 	= 1;
+	parameter C_SATURATE		= 0;
+	parameter C_SCALE			= 0;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+	
+	// Only for internal consumption (prob with MTI otherwise)
+	parameter outwidth_min_one = C_OUT_WIDTH-1;
+	parameter bwidth_min_one = C_B_WIDTH-1;
+	
+	input [C_B_WIDTH-1 : 0] B;
+	input CLK;
+	input ADD;
+	input C_IN;
+	input B_IN;
+	input CE;
+	input BYPASS;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input B_SIGNED;
+	output OVFL;
+	output C_OUT;
+	output B_OUT;
+	output Q_OVFL;
+	output Q_C_OUT;
+	output Q_B_OUT;
+	output [C_HIGH_BIT : C_LOW_BIT] S;
+	output [C_HIGH_BIT : C_LOW_BIT] Q;
+	
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_OUT_WIDTH-1 : 0] intS;
+	wire [C_OUT_WIDTH-1 : 0] intS_sat0;
+	wire [C_OUT_WIDTH-1 : 0] intS_unsat1;
+	wire [C_OUT_WIDTH-1 : 0] intS_sinsat1;
+	wire [C_OUT_WIDTH-1 : 0] intFB;
+	wire [C_OUT_WIDTH-1 : 0] intFBq;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_sat0;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_unsat1;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_sinsat1;
+	wire intSCLR;
+	wire intSSET;
+	wire intSCLR_TO_ADDER;
+	wire intSSET_TO_ADDER;
+	wire intSCLR_TO_MSB;
+	wire intSSET_TO_MSB;
+	wire intSCLR_TO_REST;
+	wire intSSET_TO_REST;
+	wire intB_SIGNED;
+	wire intBYPASSbar;
+	wire intC_OUT;
+	wire intB_OUT;
+	wire Q_C_OUT;
+	wire Q_B_OUT;
+	wire OVFL;
+	wire Q_OVFL;
+	wire intC_OUT_sat0;
+	wire intB_OUT_sat0;
+	wire Q_C_OUT_sat0;
+	wire Q_B_OUT_sat0;
+	wire OVFL_sat0;
+	wire Q_OVFL_sat0;
+	wire intC_OUT_unsat1;
+	wire intB_OUT_unsat1;
+	wire Q_C_OUT_unsat1;
+	wire Q_B_OUT_unsat1;
+	wire OVFL_unsat1;
+	wire Q_OVFL_unsat1;
+	wire intC_OUT_sinsat1;
+	wire intB_OUT_sinsat1;
+	wire Q_C_OUT_sinsat1;
+	wire Q_B_OUT_sinsat1;
+	wire OVFL_sinsat1;
+	wire Q_OVFL_sinsat1;
+	
+	wire tmpsetsatlogic_un00;
+	wire tmpsetsatlogic_un01;
+	wire tmpsetsatlogic_un10;
+	wire tmpsetsatlogic_un11c;
+	wire tmpsetsatlogic_un11s;
+	
+	wire tmpclrsatlogic_un00;
+	wire tmpclrsatlogic_un01;
+	wire tmpclrsatlogic_un10;
+	wire tmpclrsatlogic_un11c;
+	wire tmpclrsatlogic_un11s;
+	
+	wire tmpsetsatlogicmsb_sg00;
+	wire tmpsetsatlogicmsb_sg01;
+	wire tmpsetsatlogicmsb_sg10;
+	wire tmpsetsatlogicmsb_sg11c;
+	wire tmpsetsatlogicmsb_sg11s;
+	
+	wire tmpsetsatlogicrest_sg00;
+	wire tmpsetsatlogicrest_sg01;
+	wire tmpsetsatlogicrest_sg10;
+	wire tmpsetsatlogicrest_sg11c;
+	wire tmpsetsatlogicrest_sg11s;
+	
+	wire tmpclrsatlogicmsb_sg00;
+	wire tmpclrsatlogicmsb_sg01;
+	wire tmpclrsatlogicmsb_sg10;
+	wire tmpclrsatlogicmsb_sg11c;
+	wire tmpclrsatlogicmsb_sg11s;
+	
+	wire tmpclrsatlogicrest_sg00;
+	wire tmpclrsatlogicrest_sg01;
+	wire tmpclrsatlogicrest_sg10;
+	wire tmpclrsatlogicrest_sg11c;
+	wire tmpclrsatlogicrest_sg11s;
+
+    wire addsetBaseSig ;
+	wire subsetBaseSig ;
+	wire addsubsetBaseSig ;
+	wire addclrBaseSig ;
+	wire subclrBaseSig ;
+	wire addsubclrBaseSig ;
+
+	wire addsetBasePin ;
+	wire subsetBasePin ;
+	wire addsubsetBasePin ;
+	wire addclrBasePin ;
+	wire subclrBasePin ;
+	wire addsubclrBasePin ;
+
+	wire addsetBase ;
+	wire subsetBase ;
+	wire addsubsetBase ;
+	wire addclrBase ;
+	wire subclrBase ;
+	wire addsubclrBase ;
+
+	wire intCE ;
+	wire intB ;
+	
+	wire [C_HIGH_BIT : C_LOW_BIT] Q = intFBq;
+	wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs);
+	wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx);
+	wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx);
+	
+	
+	// Sort out default values for missing ports
+	
+	assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0);
+	assign intBYPASSbar = (C_BYPASS_LOW == 1 ? BYPASS : ~BYPASS);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	
+	// Now make up the design from other baseblox
+	// An addsub for when no saturation logic is required...
+	C_ADDSUB_V4_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					(C_B_TYPE == `c_pin )? `c_signed : C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					C_HAS_ACLR,
+					C_HAS_ADD,
+					C_HAS_AINIT,
+					C_HAS_ASET,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+					C_HAS_B_IN,
+					C_HAS_B_OUT,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					C_HAS_C_OUT,
+					C_HAS_OVFL,
+					1,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					C_HAS_S,
+					C_HAS_SCLR,
+					C_HAS_SINIT,
+					C_HAS_SSET,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		sat0_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_sat0), .C_OUT(intC_OUT_sat0), 
+					.B_OUT(intB_OUT_sat0), .Q_OVFL(Q_OVFL_sat0),
+					.Q_C_OUT(Q_C_OUT_sat0), .Q_B_OUT(Q_B_OUT_sat0),
+					.S(intS_sat0), .Q(intFBq_sat0));
+					
+					
+	// Another addsub for when saturation logic IS required, but only for unsigned data				
+	C_ADDSUB_V4_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					0,
+					C_HAS_ADD,
+					0,
+					0,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+					C_HAS_B_IN,
+					1,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					1,
+					C_HAS_OVFL,
+					1,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					C_HAS_S,
+					1,
+					0,
+					1,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		unsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_TO_ADDER), .SSET(intSSET_TO_ADDER), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_unsat1), .C_OUT(intC_OUT_unsat1), 
+					.B_OUT(intB_OUT_unsat1), .Q_OVFL(Q_OVFL_unsat1),
+					.Q_C_OUT(Q_C_OUT_unsat1), .Q_B_OUT(Q_B_OUT_unsat1),
+					.S(intS_unsat1), .Q(intFBq_unsat1));
+					
+	// Another addsub for when saturation logic IS required, but for signed data				
+	C_ADDSUB_V4_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					C_HAS_ACLR,
+					C_HAS_ADD,
+					C_HAS_AINIT,
+					C_HAS_ASET,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+					C_HAS_B_IN,
+					1,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					1,
+					C_HAS_OVFL,
+					0,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					1,
+					C_HAS_SCLR,
+					C_HAS_SINIT,
+					C_HAS_SSET,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		sinsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_sinsat1), .C_OUT(intC_OUT_sinsat1), 
+					.B_OUT(intB_OUT_sinsat1), .Q_OVFL(Q_OVFL_sinsat1),
+					.Q_C_OUT(Q_C_OUT_sinsat1), .Q_B_OUT(Q_B_OUT_sinsat1),
+					.S(intS_sinsat1));
+					
+	// Registers for output of the last addsub
+	C_REG_FD_V4_0 #(C_AINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8],
+					C_ENABLE_RLOCS,
+					0,
+					0,
+					0,
+					C_HAS_CE,
+					1,
+					0,
+					1,
+					C_SINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8],
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY,
+					1)
+			msb_reg(.D(intS_sinsat1[outwidth_min_one]), .CLK(CLK),
+					.CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_TO_MSB), .SSET(intSSET_TO_MSB),
+					.SINIT(SINIT), .Q(intFBq_sinsat1[outwidth_min_one]));
+						
+	// Need the ?: on the value of C_B_WIDTH in case it == 1
+	C_REG_FD_V4_0 #(C_AINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0],
+					C_ENABLE_RLOCS,
+					0,
+					0,
+					0,
+					C_HAS_CE,
+					1,
+					0,
+					1,
+					C_SINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0],
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY,
+					(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)
+			rest_reg(.D(intS_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]), .CLK(CLK),
+					 .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					 .SCLR((C_B_WIDTH == 1 ? intSCLR_TO_MSB : intSCLR_TO_REST)), .SSET((C_B_WIDTH == 1 ? intSSET_TO_MSB : intSSET_TO_REST)),
+					 .SINIT(SINIT), .Q(intFBq_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]));
+						
+	
+	// Sort out the choices from all these output signals...
+	assign intCE = (C_SATURATE == 0 ? CE : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 1)) ? ((C_BYPASS_ENABLE == `c_no_override) ? (~BYPASS | CE) : CE) : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 0)) ? ((C_BYPASS_ENABLE == `c_no_override) ? (BYPASS | CE) : CE) : CE))) ;
+	assign intC_OUT = (C_SATURATE == 0 ? intC_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intC_OUT_unsat1 : intC_OUT_sinsat1));	
+	assign intB_OUT = (C_SATURATE == 0 ? intB_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intB_OUT_unsat1 : intB_OUT_sinsat1));	
+	assign OVFL = (C_SATURATE == 0 ? OVFL_sat0 : (C_B_TYPE == `c_unsigned ? OVFL_unsat1 : OVFL_sinsat1));
+	assign Q_C_OUT = (C_SATURATE == 0 ? Q_C_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_C_OUT_unsat1 : Q_C_OUT_sinsat1));	
+	assign Q_B_OUT = (C_SATURATE == 0 ? Q_B_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_B_OUT_unsat1 : Q_B_OUT_sinsat1));	
+	assign Q_OVFL = (C_SATURATE == 0 ? Q_OVFL_sat0 : (C_B_TYPE == `c_unsigned ? Q_OVFL_unsat1 : Q_OVFL_sinsat1));
+	assign intS = (C_SATURATE == 0 ? intS_sat0 : (C_B_TYPE == `c_unsigned ? intS_unsat1 : intS_sinsat1));
+	assign intFBq = (C_SATURATE == 0 ? intFBq_sat0 : (C_B_TYPE == `c_unsigned ? intFBq_unsat1 : intFBq_sinsat1));
+	
+
+	// COMPLEX decisions on what to feed to the local control sigs...
+	// The signal name suffices denote: un = unsigned, sg = signed, 00 = has neither sset nor sclr, 01 = has sclr only etc
+	// 11c = has bot sset and sclr and sclr dominates, 11s = sset dominates, etc
+	
+	// Unsigned version first
+	assign tmpsetsatlogic_un00 = (C_ADD_MODE == `c_add ? intC_OUT : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ADD)));
+	assign tmpsetsatlogic_un01 = (C_ADD_MODE == `c_add ? (intC_OUT & ~intSCLR) : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ~intSCLR & ADD)));
+	assign tmpsetsatlogic_un10 = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((intC_OUT & ADD) | intSSET)));
+	assign tmpsetsatlogic_un11c = (C_ADD_MODE == `c_add ? (~intSCLR & (intC_OUT | intSSET)) : (C_ADD_MODE == `c_sub ? (~intSCLR & intSSET) : ((~intSCLR & intC_OUT & ADD) | (intSSET & ~intSCLR))));
+	assign tmpsetsatlogic_un11s = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((~intSCLR & intC_OUT & ADD) | intSSET)));
+	
+	assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? ~intB_OUT : (~intC_OUT & ~ADD)));
+	assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT | intSCLR) : (intSCLR | (~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT & ~intSSET) : (~intSSET & ~intC_OUT & ~ADD)));
+	assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (intSCLR | (~intB_OUT & ~intSSET)) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (~intSSET & (intSCLR | ~intB_OUT)) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD))));
+	
+	assign intSSET_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogic_un00 : tmpsetsatlogic_un01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogic_un10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogic_un11c : tmpsetsatlogic_un11s)));
+										
+	assign intSCLR_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogic_un00 : tmpclrsatlogic_un01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogic_un10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogic_un11c : tmpclrsatlogic_un11s)));
+										
+	// Now all the signals for the signed version
+	assign intB = (C_B_CONSTANT == 1 ? (C_B_VALUE[(C_B_WIDTH*8)-1 : (C_B_WIDTH-1)*8] == "0" ? 1'b0 : 1'b1) : B[C_B_WIDTH-1]) ;
+	assign addclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)) ;
+	assign addsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB) ;
+	assign subclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB) ;
+	assign subsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB)) ;
+	assign addsubclrBaseSig = ((~ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB)) | (ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)))) ;
+	assign addsubsetBaseSig = ((~ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB))) | (ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB))) ;
+
+	assign addclrBasePin = (~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB));
+	assign addsetBasePin = (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & intB) ;
+	assign subclrBasePin = (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB);
+	assign subsetBasePin = (~(intB_SIGNED) & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & ~(intB));
+	assign addsubclrBasePin = (~(ADD) & (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB)) | (ADD & ((~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)))) ;
+	assign addsubsetBasePin = (~(ADD) & ((~intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & ~intB))) | (ADD & intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & intB) ;
+
+    assign addclrBase = (C_HAS_B_SIGNED == 0 ? addclrBaseSig : addclrBasePin);
+	assign addsetBase = (C_HAS_B_SIGNED == 0 ? addsetBaseSig : addsetBasePin);
+	assign subclrBase = (C_HAS_B_SIGNED == 0 ? subclrBaseSig : subclrBasePin);
+	assign subsetBase = (C_HAS_B_SIGNED == 0 ? subsetBaseSig : subsetBasePin);
+	assign addsubclrBase = (C_HAS_B_SIGNED == 0 ? addsubclrBaseSig : addsubclrBasePin);
+	assign addsubsetBase = (C_HAS_B_SIGNED == 0 ? addsubsetBaseSig : addsubsetBasePin);
+
+	assign tmpsetsatlogicmsb_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addsetBase & intBYPASSbar : addsetBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subsetBase & intBYPASSbar : subsetBase) : (C_HAS_BYPASS == 1 ? addsubsetBase & intBYPASSbar : addsubsetBase) ));							 
+	assign tmpsetsatlogicmsb_sg01 = tmpsetsatlogicmsb_sg00 & ~intSCLR ;							 
+	assign tmpsetsatlogicmsb_sg10 = tmpsetsatlogicmsb_sg00 | intSSET ;								 
+	assign tmpsetsatlogicmsb_sg11c = (tmpsetsatlogicmsb_sg00 | intSSET) & ~intSCLR ;
+	assign tmpsetsatlogicmsb_sg11s = tmpsetsatlogicmsb_sg00 | intSSET ;
+	
+	assign tmpsetsatlogicrest_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addclrBase & intBYPASSbar : addclrBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subclrBase & intBYPASSbar : subclrBase) : (C_HAS_BYPASS == 1 ? addsubclrBase & intBYPASSbar : addsubclrBase) ));									 
+	assign tmpsetsatlogicrest_sg01 = tmpsetsatlogicrest_sg00 & ~intSCLR ;							 
+	assign tmpsetsatlogicrest_sg10 = tmpsetsatlogicrest_sg00 | intSSET ;							 
+	assign tmpsetsatlogicrest_sg11c = (tmpsetsatlogicrest_sg00 | intSSET) & ~intSCLR ;  						  
+	assign tmpsetsatlogicrest_sg11s = tmpsetsatlogicrest_sg00 | intSSET ;  						  
+	
+	assign tmpclrsatlogicmsb_sg00 = tmpsetsatlogicrest_sg00 ;							 
+	assign tmpclrsatlogicmsb_sg01 = tmpsetsatlogicrest_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicmsb_sg10 = tmpsetsatlogicrest_sg00 & ~intSSET ;							 
+	assign tmpclrsatlogicmsb_sg11c = tmpsetsatlogicrest_sg00 | intSCLR ; 						  
+	assign tmpclrsatlogicmsb_sg11s = (tmpsetsatlogicrest_sg00 | intSCLR) & ~intSSET ;  						  
+	
+	assign tmpclrsatlogicrest_sg00 = tmpsetsatlogicmsb_sg00 ;							 
+	assign tmpclrsatlogicrest_sg01 = tmpsetsatlogicmsb_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicrest_sg10 = tmpsetsatlogicmsb_sg00 & ~intSSET ;							 
+	assign tmpclrsatlogicrest_sg11c = tmpsetsatlogicmsb_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicrest_sg11s = (tmpsetsatlogicmsb_sg00 | intSCLR) & ~intSSET ;					 
+	
+	assign intSSET_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg00 : tmpsetsatlogicmsb_sg01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicmsb_sg11c : tmpsetsatlogicmsb_sg11s)));
+										
+	assign intSCLR_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg00 : tmpclrsatlogicmsb_sg01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicmsb_sg11c : tmpclrsatlogicmsb_sg11s)));
+										
+	assign intSSET_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg00 : tmpsetsatlogicrest_sg01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicrest_sg11c : tmpsetsatlogicrest_sg11s)));
+										
+	assign intSCLR_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg00 : tmpclrsatlogicrest_sg01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicrest_sg11c : tmpclrsatlogicrest_sg11s)));
+
+	// Finally we are ready to scale the feedback signal...
+	// If the scaling factor results in NO bits being fed back to the input then we need to handle this!
+	// This is the case if C_SCALE >= C_OUT_WIDTH
+	assign intFB[C_OUT_WIDTH-1-(C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE) : 0] = (C_SCALE >= C_OUT_WIDTH ? {C_OUT_WIDTH{1'b0}} : intFBq[C_OUT_WIDTH-1 : (C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE)]);
+	//assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1'b1)) ?
+	//						{C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}}));
+	assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || C_B_TYPE == `c_pin) ?
+							{C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}}));
+
+							
+	
+											
+	initial
+	begin
+		#1;
+	end
+	
+	
+/* helper functions */
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+		
+	function [C_B_WIDTH - 1 : 0] to_bitsB;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_B_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+				to_bitsB[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bitsB[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bitsB[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bitsB[i-1] = 0;
+				else
+				begin
+					$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+	function max;
+	input a;
+	input b;
+	begin
+		max = (a > b) ? a : b;
+	end
+	endfunction
+		
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_add
+`undef c_sub
+`undef c_add_sub
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef allUKs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V5_0.v

@@ -0,0 +1,654 @@
+/* $Id: C_ACCUM_V5_0.v,v 1.17 2008/09/08 20:05:55 akennedy Exp $
+--
+-- Filename - C_ACCUM_V5_0.v
+-- Author - Xilinx
+-- Creation - 15 July 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_ACCUM_V5_0 module
+*/
+
+`timescale 1 ns/10 ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_add 0
+`define c_sub 1
+`define c_add_sub 2
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}}
+
+module C_ACCUM_V5_0 (B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT,
+					  SCLR, SSET, SINIT, B_SIGNED, OVFL, C_OUT, B_OUT,
+					  Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q);
+
+	parameter C_ADD_MODE 		= `c_add;
+	parameter C_AINIT_VAL 		= "0000000000000000";
+	parameter C_BYPASS_ENABLE 	= `c_override;
+	parameter C_BYPASS_LOW 		= 0;
+	parameter C_B_CONSTANT 		= 0;
+	parameter C_B_TYPE 			= `c_unsigned;
+	parameter C_B_VALUE 		= "0000000000000000";
+	parameter C_B_WIDTH 		= 16;
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 1;
+	parameter C_HAS_ADD 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_BYPASS 		= 0;
+	parameter C_HAS_BYPASS_WITH_CIN = 0;
+    parameter C_HAS_B_IN 		= 1;
+	parameter C_HAS_B_OUT 		= 0;
+	parameter C_HAS_B_SIGNED 	= 0;
+	parameter C_HAS_CE 			= 1;
+	parameter C_HAS_C_IN 		= 1;
+	parameter C_HAS_C_OUT 		= 0;
+	parameter C_HAS_OVFL 		= 0;
+	parameter C_HAS_Q_B_OUT 	= 0;
+	parameter C_HAS_Q_C_OUT 	= 0;
+	parameter C_HAS_Q_OVFL 		= 0;
+	parameter C_HAS_S 			= 1; 
+	parameter C_HAS_SCLR 		= 1;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HIGH_BIT 		= 15;
+	parameter C_LOW_BIT 		= 0;
+	parameter C_OUT_WIDTH 		= 16;
+	parameter C_PIPE_STAGES 	= 1;
+	parameter C_SATURATE		= 0;
+	parameter C_SCALE			= 1;
+	parameter C_SINIT_VAL 		= "0000000000000000";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+	
+	// Only for internal consumption (prob with MTI otherwise)
+	parameter outwidth_min_one = C_OUT_WIDTH-1;
+	parameter bwidth_min_one = C_B_WIDTH-1;
+
+    parameter tempSyncEnable = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? 1 : C_SYNC_ENABLE);   
+	
+	input [C_B_WIDTH-1 : 0] B;
+	input CLK;
+	input ADD;
+	input C_IN;
+	input B_IN;
+	input CE;
+	input BYPASS;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input B_SIGNED;
+	output OVFL;
+	output C_OUT;
+	output B_OUT;
+	output Q_OVFL;
+	output Q_C_OUT;
+	output Q_B_OUT;
+	output [C_HIGH_BIT : C_LOW_BIT] S;
+	output [C_HIGH_BIT : C_LOW_BIT] Q;
+	
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_OUT_WIDTH-1 : 0] intS;
+	wire [C_OUT_WIDTH-1 : 0] intS_sat0;
+	wire [C_OUT_WIDTH-1 : 0] intS_unsat1;
+	wire [C_OUT_WIDTH-1 : 0] intS_sinsat1;
+	wire [C_OUT_WIDTH-1 : 0] intFB;
+	wire [C_OUT_WIDTH-1 : 0] intFBq;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_sat0;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_unsat1;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_sinsat1;
+	wire intSCLR;
+	wire intSSET;
+	wire intSCLR_TO_ADDER;
+	wire intSSET_TO_ADDER;
+	wire intSCLR_TO_MSB;
+	wire intSSET_TO_MSB;
+	wire intSCLR_TO_REST;
+	wire intSSET_TO_REST;
+	wire intB_SIGNED;
+	wire intBYPASSbar;
+	wire intC_OUT;
+	wire intB_OUT;
+	wire Q_C_OUT;
+	wire Q_B_OUT;
+	wire OVFL;
+	wire Q_OVFL;
+	wire intC_OUT_sat0;
+	wire intB_OUT_sat0;
+	wire Q_C_OUT_sat0;
+	wire Q_B_OUT_sat0;
+	wire OVFL_sat0;
+	wire Q_OVFL_sat0;
+	wire intC_OUT_unsat1;
+	wire intB_OUT_unsat1;
+	wire Q_C_OUT_unsat1;
+	wire Q_B_OUT_unsat1;
+	wire OVFL_unsat1;
+	wire Q_OVFL_unsat1;
+	wire intC_OUT_sinsat1;
+	wire intB_OUT_sinsat1;
+	wire Q_C_OUT_sinsat1;
+	wire Q_B_OUT_sinsat1;
+	wire OVFL_sinsat1;
+	wire Q_OVFL_sinsat1;
+    wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode
+	wire tempCE;
+
+	
+	wire tmpsetsatlogic_un00;
+	wire tmpsetsatlogic_un01;
+	wire tmpsetsatlogic_un10;
+	wire tmpsetsatlogic_un11c;
+	wire tmpsetsatlogic_un11s;
+	
+	wire tmpclrsatlogic_un00;
+	wire tmpclrsatlogic_un01;
+	wire tmpclrsatlogic_un10;
+	wire tmpclrsatlogic_un11c;
+	wire tmpclrsatlogic_un11s;
+	
+	wire tmpsetsatlogicmsb_sg00;
+	wire tmpsetsatlogicmsb_sg01;
+	wire tmpsetsatlogicmsb_sg10;
+	wire tmpsetsatlogicmsb_sg11c;
+	wire tmpsetsatlogicmsb_sg11s;
+	
+	wire tmpsetsatlogicrest_sg00;
+	wire tmpsetsatlogicrest_sg01;
+	wire tmpsetsatlogicrest_sg10;
+	wire tmpsetsatlogicrest_sg11c;
+	wire tmpsetsatlogicrest_sg11s;
+	
+	wire tmpclrsatlogicmsb_sg00;
+	wire tmpclrsatlogicmsb_sg01;
+	wire tmpclrsatlogicmsb_sg10;
+	wire tmpclrsatlogicmsb_sg11c;
+	wire tmpclrsatlogicmsb_sg11s;
+	
+	wire tmpclrsatlogicrest_sg00;
+	wire tmpclrsatlogicrest_sg01;
+	wire tmpclrsatlogicrest_sg10;
+	wire tmpclrsatlogicrest_sg11c;
+	wire tmpclrsatlogicrest_sg11s;
+
+    wire addsetBaseSig ;
+	wire subsetBaseSig ;
+	wire addsubsetBaseSig ;
+	wire addclrBaseSig ;
+	wire subclrBaseSig ;
+	wire addsubclrBaseSig ;
+
+	wire addsetBasePin ;
+	wire subsetBasePin ;
+	wire addsubsetBasePin ;
+	wire addclrBasePin ;
+	wire subclrBasePin ;
+	wire addsubclrBasePin ;
+
+	wire addsetBase ;
+	wire subsetBase ;
+	wire addsubsetBase ;
+	wire addclrBase ;
+	wire subclrBase ;
+	wire addsubclrBase ;
+
+	wire intCE ;
+	wire intB ;
+    wire [C_B_WIDTH : 0] intBconst;
+    
+	wire [C_HIGH_BIT : C_LOW_BIT] Q = intFBq;
+	wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs);
+	wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx);
+	wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx);
+	
+	
+	// Sort out default values for missing ports
+	
+	assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0);
+	assign intBYPASSbar = (C_BYPASS_LOW == 1 ? BYPASS : ~BYPASS);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+    assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; //assign new c_has_bypass_with_cin parameter to internal wire
+    assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B;
+	
+    // Now make up the design from other baseblox
+	// An addsub for when no saturation logic is required...
+	C_ADDSUB_V5_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					(C_B_TYPE == `c_pin )? `c_signed : C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					C_HAS_ACLR,
+					C_HAS_ADD,
+					C_HAS_AINIT,
+					C_HAS_ASET,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+                    C_HAS_B_IN,
+					C_HAS_B_OUT,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					C_HAS_C_OUT,
+					C_HAS_OVFL,
+					1,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					C_HAS_S,
+					C_HAS_SCLR,
+					C_HAS_SINIT,
+					C_HAS_SSET,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		sat0_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_sat0), .C_OUT(intC_OUT_sat0), 
+					.B_OUT(intB_OUT_sat0), .Q_OVFL(Q_OVFL_sat0),
+					.Q_C_OUT(Q_C_OUT_sat0), .Q_B_OUT(Q_B_OUT_sat0),
+					.S(intS_sat0), .Q(intFBq_sat0));
+					
+					
+	// Another addsub for when saturation logic IS required, but only for unsigned data				
+	C_ADDSUB_V5_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					0,
+					C_HAS_ADD,
+					0,
+					0,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+					C_HAS_B_IN,
+					1,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					1,
+					C_HAS_OVFL,
+					1,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					C_HAS_S,
+					1,
+					0,
+					1,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					tempSyncEnable,
+					C_SYNC_PRIORITY)
+		unsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_TO_ADDER), .SSET(intSSET_TO_ADDER), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_unsat1), .C_OUT(intC_OUT_unsat1), 
+					.B_OUT(intB_OUT_unsat1), .Q_OVFL(Q_OVFL_unsat1),
+					.Q_C_OUT(Q_C_OUT_unsat1), .Q_B_OUT(Q_B_OUT_unsat1),
+					.S(intS_unsat1), .Q(intFBq_unsat1));
+					
+	// Another addsub for when saturation logic IS required, but for signed data				
+	C_ADDSUB_V5_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					C_HAS_ACLR,
+					C_HAS_ADD,
+					C_HAS_AINIT,
+					C_HAS_ASET,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+					C_HAS_B_IN,
+					1,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					1,
+					C_HAS_OVFL,
+					0,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					1,
+					C_HAS_SCLR,
+					C_HAS_SINIT,
+					C_HAS_SSET,
+					outwidth_min_one,
+			        1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					tempSyncEnable, // wasC_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		sinsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_sinsat1), .C_OUT(intC_OUT_sinsat1), 
+					.B_OUT(intB_OUT_sinsat1), .Q_OVFL(Q_OVFL_sinsat1),
+					.Q_C_OUT(Q_C_OUT_sinsat1), .Q_B_OUT(Q_B_OUT_sinsat1),
+					.S(intS_sinsat1), .Q());
+					
+	// Registers for output of the last addsub
+	C_REG_FD_V5_0 #(C_AINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8],
+					C_ENABLE_RLOCS,
+					0,
+					0,
+					0,
+					C_HAS_CE,
+					1,
+					0,
+					1,
+					C_SINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8],
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY,
+					1)
+			msb_reg(.D(intS_sinsat1[outwidth_min_one]), .CLK(CLK),
+					.CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_TO_MSB), .SSET(intSSET_TO_MSB),
+					.SINIT(SINIT), .Q(intFBq_sinsat1[outwidth_min_one]));
+						
+	// Need the ?: on the value of C_B_WIDTH in case it == 1
+	C_REG_FD_V5_0 #(C_AINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0],
+					C_ENABLE_RLOCS,
+					0,
+					0,
+					0,
+					C_HAS_CE,
+					1,
+					0,
+					1,
+					C_SINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0],
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY,
+					(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)
+			rest_reg(.D(intS_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]), .CLK(CLK),
+					 .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					 .SCLR((C_B_WIDTH == 1 ? intSCLR_TO_MSB : intSCLR_TO_REST)), .SSET((C_B_WIDTH == 1 ? intSSET_TO_MSB : intSSET_TO_REST)),
+					 .SINIT(SINIT), .Q(intFBq_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]));
+						
+	
+	// Sort out the choices from all these output signals...
+	assign tempCE = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? (CE | intSSET | intSCLR) : CE);
+    assign intCE = (C_SATURATE == 0 ? CE : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 1)) ? ((C_BYPASS_ENABLE == `c_override) ?  (~BYPASS | tempCE) : tempCE) : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 0)) ? ((C_BYPASS_ENABLE == `c_override) ? (BYPASS | tempCE) : tempCE) : tempCE))) ;
+    
+	assign intC_OUT = (C_SATURATE == 0 ? intC_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intC_OUT_unsat1 : intC_OUT_sinsat1));	
+	assign intB_OUT = (C_SATURATE == 0 ? intB_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intB_OUT_unsat1 : intB_OUT_sinsat1));	
+	assign OVFL = (C_SATURATE == 0 ? OVFL_sat0 : (C_B_TYPE == `c_unsigned ? OVFL_unsat1 : OVFL_sinsat1));
+	assign Q_C_OUT = (C_SATURATE == 0 ? Q_C_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_C_OUT_unsat1 : Q_C_OUT_sinsat1));	
+	assign Q_B_OUT = (C_SATURATE == 0 ? Q_B_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_B_OUT_unsat1 : Q_B_OUT_sinsat1));	
+	assign Q_OVFL = (C_SATURATE == 0 ? Q_OVFL_sat0 : (C_B_TYPE == `c_unsigned ? Q_OVFL_unsat1 : Q_OVFL_sinsat1));
+	assign intS = (C_SATURATE == 0 ? intS_sat0 : (C_B_TYPE == `c_unsigned ? intS_unsat1 : intS_sinsat1));
+	assign intFBq = (C_SATURATE == 0 ? intFBq_sat0 : (C_B_TYPE == `c_unsigned ? intFBq_unsat1 : intFBq_sinsat1));
+	
+
+	// COMPLEX decisions on what to feed to the local control sigs...
+	// The signal name suffices denote: un = unsigned, sg = signed, 00 = has neither sset nor sclr, 01 = has sclr only etc
+	// 11c = has bot sset and sclr and sclr dominates, 11s = sset dominates, etc
+	
+	// Unsigned version first
+	assign tmpsetsatlogic_un00 = (C_ADD_MODE == `c_add ? intC_OUT : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ADD)));
+	assign tmpsetsatlogic_un01 = (C_ADD_MODE == `c_add ? (intC_OUT & ~intSCLR) : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ~intSCLR & ADD)));
+	assign tmpsetsatlogic_un10 = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((intC_OUT & ADD) | intSSET)));
+	assign tmpsetsatlogic_un11c = (C_ADD_MODE == `c_add ? (~intSCLR & (intC_OUT | intSSET)) : (C_ADD_MODE == `c_sub ? (~intSCLR & intSSET) : ((~intSCLR & intC_OUT & ADD) | (intSSET & ~intSCLR))));
+	assign tmpsetsatlogic_un11s = (C_ADD_MODE == `c_add ? ((~intSCLR && intC_OUT) | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((~intSCLR & intC_OUT & ADD) | intSSET)));
+	
+//	assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? ~intB_OUT : (~intC_OUT & ~ADD)));
+    assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intB_OUT & BYPASS) : (~intB_OUT & ~BYPASS)): ~intB_OUT) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1  ? ((~intC_OUT & ~ADD) & BYPASS) : ((~intC_OUT & ~ADD) & ~BYPASS)) : (~intC_OUT & ~ADD))));
+//  assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT | intSCLR) : (intSCLR | (~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) | intSCLR) : ((~intB_OUT & ~BYPASS) | intSCLR)) : (~intB_OUT | intSCLR)) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1  ? (intSCLR | ((~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intC_OUT & ~ADD)))));
+//	assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT & ~intSSET) : (~intSSET & ~intC_OUT & ~ADD)));
+  	assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) & ~intSSET) : ((~intB_OUT & ~BYPASS) & ~intSSET)): (~intB_OUT & ~intSSET)) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (~intSSET & (~intC_OUT & ~ADD) & BYPASS) : (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS))) : (~intSSET & ~intC_OUT & ~ADD)))));
+//	assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (intSCLR | (~intB_OUT & ~intSSET)) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (intSCLR | ((~intB_OUT & BYPASS) & ~intSSET)) : (intSCLR | ((~intB_OUT & ~BYPASS) & ~intSSET))) : (intSCLR | (~intB_OUT & ~intSSET))) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))))));
+//	assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (~intSSET & (intSCLR | ~intB_OUT)) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intSSET & (intSCLR | (~intB_OUT & BYPASS))) : (~intSSET & (intSCLR | (~intB_OUT & ~BYPASS)))) : (~intSSET & (intSCLR | ~intB_OUT))) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & BYPASS))):  ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS)))) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD)))));
+	
+	assign intSSET_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogic_un00 : tmpsetsatlogic_un01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogic_un10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogic_un11c : tmpsetsatlogic_un11s)));
+										
+	assign intSCLR_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogic_un00 : tmpclrsatlogic_un01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogic_un10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogic_un11c : tmpclrsatlogic_un11s)));
+										
+	// Now all the signals for the signed version
+	 assign intB = intBconst[C_B_WIDTH-1];
+    //assign intB = (C_B_CONSTANT == 1 ? (C_B_VALUE[(C_B_WIDTH*8)-1 : (C_B_WIDTH-1)*8] == "0" ? 1'b0 : 1'b1) : B[C_B_WIDTH-1]) ;
+
+	assign addclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)) ;
+	assign addsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB) ;
+	assign subclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB) ;
+	assign subsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB)) ;
+	assign addsubclrBaseSig = ((~ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB)) | (ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)))) ;
+	assign addsubsetBaseSig = ((~ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB))) | (ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB))) ;
+
+	assign addclrBasePin = (~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB));
+	assign addsetBasePin = (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & intB) ;
+	assign subclrBasePin = (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB);
+	assign subsetBasePin = (~(intB_SIGNED) & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & ~(intB));
+	assign addsubclrBasePin = (~(ADD) & (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB)) | (ADD & ((~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)))) ;
+	assign addsubsetBasePin = (~(ADD) & ((~intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & ~intB))) | (ADD & intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & intB) ;
+
+    assign addclrBase = (C_HAS_B_SIGNED == 0 ? addclrBaseSig : addclrBasePin);
+	assign addsetBase = (C_HAS_B_SIGNED == 0 ? addsetBaseSig : addsetBasePin);
+	assign subclrBase = (C_HAS_B_SIGNED == 0 ? subclrBaseSig : subclrBasePin);
+	assign subsetBase = (C_HAS_B_SIGNED == 0 ? subsetBaseSig : subsetBasePin);
+	assign addsubclrBase = (C_HAS_B_SIGNED == 0 ? addsubclrBaseSig : addsubclrBasePin);
+	assign addsubsetBase = (C_HAS_B_SIGNED == 0 ? addsubsetBaseSig : addsubsetBasePin);
+
+	assign tmpsetsatlogicmsb_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addsetBase & intBYPASSbar : addsetBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subsetBase & intBYPASSbar : subsetBase) : (C_HAS_BYPASS == 1 ? addsubsetBase & intBYPASSbar : addsubsetBase) ));							 
+	assign tmpsetsatlogicmsb_sg01 = tmpsetsatlogicmsb_sg00 & ~intSCLR ;							 
+	assign tmpsetsatlogicmsb_sg10 = tmpsetsatlogicmsb_sg00 | intSSET ;								 
+	assign tmpsetsatlogicmsb_sg11c = (tmpsetsatlogicmsb_sg00 | intSSET) & ~intSCLR ;
+	assign tmpsetsatlogicmsb_sg11s = tmpsetsatlogicmsb_sg00 | intSSET ;
+	
+	assign tmpsetsatlogicrest_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addclrBase & intBYPASSbar : addclrBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subclrBase & intBYPASSbar : subclrBase) : (C_HAS_BYPASS == 1 ? addsubclrBase & intBYPASSbar : addsubclrBase) ));									 
+	assign tmpsetsatlogicrest_sg01 = tmpsetsatlogicrest_sg00 & ~intSCLR ;							 
+	assign tmpsetsatlogicrest_sg10 = tmpsetsatlogicrest_sg00 | intSSET ;							 
+	assign tmpsetsatlogicrest_sg11c = (tmpsetsatlogicrest_sg00 | intSSET) & ~intSCLR ;  						  
+	assign tmpsetsatlogicrest_sg11s = tmpsetsatlogicrest_sg00 | intSSET ;  						  
+	
+	assign tmpclrsatlogicmsb_sg00 = tmpsetsatlogicrest_sg00 ;							 
+	assign tmpclrsatlogicmsb_sg01 = tmpsetsatlogicrest_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicmsb_sg10 = tmpsetsatlogicrest_sg00 & ~intSSET ;							 
+	assign tmpclrsatlogicmsb_sg11c = tmpsetsatlogicrest_sg00 | intSCLR ; 						  
+	assign tmpclrsatlogicmsb_sg11s = (tmpsetsatlogicrest_sg00 | intSCLR) & ~intSSET ;  						  
+	
+	assign tmpclrsatlogicrest_sg00 = tmpsetsatlogicmsb_sg00 ;							 
+	assign tmpclrsatlogicrest_sg01 = tmpsetsatlogicmsb_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicrest_sg10 = tmpsetsatlogicmsb_sg00 & ~intSSET ;							 
+	assign tmpclrsatlogicrest_sg11c = tmpsetsatlogicmsb_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicrest_sg11s = (tmpsetsatlogicmsb_sg00 | intSCLR) & ~intSSET ;					 
+	
+	assign intSSET_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg00 : tmpsetsatlogicmsb_sg01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicmsb_sg11c : tmpsetsatlogicmsb_sg11s)));
+										
+	assign intSCLR_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg00 : tmpclrsatlogicmsb_sg01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicmsb_sg11c : tmpclrsatlogicmsb_sg11s)));
+										
+	assign intSSET_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg00 : tmpsetsatlogicrest_sg01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicrest_sg11c : tmpsetsatlogicrest_sg11s)));
+										
+	assign intSCLR_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg00 : tmpclrsatlogicrest_sg01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicrest_sg11c : tmpclrsatlogicrest_sg11s)));
+
+	// Finally we are ready to scale the feedback signal...
+	// If the scaling factor results in NO bits being fed back to the input then we need to handle this!
+	// This is the case if C_SCALE >= C_OUT_WIDTH
+	assign intFB[C_OUT_WIDTH-1-(C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE) : 0] = (C_SCALE >= C_OUT_WIDTH ? {C_OUT_WIDTH{1'b0}} : intFBq[C_OUT_WIDTH-1 : (C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE)]);
+	//assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1'b1)) ?
+	//						{C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}}));
+	assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || C_B_TYPE == `c_pin) ?
+							{C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}}));
+
+							
+	
+											
+	initial
+	begin
+		#1;
+	end
+				
+/* helper functions */
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+		
+	function [C_B_WIDTH - 1 : 0] to_bitsB;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_B_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+				to_bitsB[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bitsB[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bitsB[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bitsB[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+	function max;
+	input a;
+	input b;
+	begin
+		max = (a > b) ? a : b;
+	end
+	endfunction
+		
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_add
+`undef c_sub
+`undef c_add_sub
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef allUKs
+
+
+
+
+
+
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V5_1.v

@@ -0,0 +1,655 @@
+/* $Id: C_ACCUM_V5_1.v,v 1.15 2008/09/08 20:05:55 akennedy Exp $
+--
+-- Filename - C_ACCUM_V5_1.v
+-- Author - Xilinx
+-- Creation - 15 July 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_ACCUM_V5_1 module
+*/
+
+`timescale 1 ns/10 ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_add 0
+`define c_sub 1
+`define c_add_sub 2
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}}
+
+module C_ACCUM_V5_1 (B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT,
+					  SCLR, SSET, SINIT, B_SIGNED, OVFL, C_OUT, B_OUT,
+					  Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q);
+
+	parameter C_ADD_MODE 		= `c_add;
+	parameter C_AINIT_VAL 		= "0000000000000000";
+	parameter C_BYPASS_ENABLE 	= `c_override;
+	parameter C_BYPASS_LOW 		= 0;
+	parameter C_B_CONSTANT 		= 0;
+	parameter C_B_TYPE 			= `c_unsigned;
+	parameter C_B_VALUE 		= "0000000000000000";
+	parameter C_B_WIDTH 		= 16;
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 1;
+	parameter C_HAS_ADD 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_BYPASS 		= 0;
+	parameter C_HAS_BYPASS_WITH_CIN = 0;
+    parameter C_HAS_B_IN 		= 1;
+	parameter C_HAS_B_OUT 		= 0;
+	parameter C_HAS_B_SIGNED 	= 0;
+	parameter C_HAS_CE 			= 1;
+	parameter C_HAS_C_IN 		= 1;
+	parameter C_HAS_C_OUT 		= 0;
+	parameter C_HAS_OVFL 		= 0;
+	parameter C_HAS_Q_B_OUT 	= 0;
+	parameter C_HAS_Q_C_OUT 	= 0;
+	parameter C_HAS_Q_OVFL 		= 0;
+	parameter C_HAS_S 			= 1; 
+	parameter C_HAS_SCLR 		= 1;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HIGH_BIT 		= 15;
+	parameter C_LOW_BIT 		= 0;
+	parameter C_OUT_WIDTH 		= 16;
+	parameter C_PIPE_STAGES 	= 1;
+	parameter C_SATURATE		= 0;
+	parameter C_SCALE			= 1;
+	parameter C_SINIT_VAL 		= "0000000000000000";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+	
+	// Only for internal consumption (prob with MTI otherwise)
+	parameter outwidth_min_one = C_OUT_WIDTH-1;
+	parameter bwidth_min_one = C_B_WIDTH-1;
+
+    parameter tempSyncEnable = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? 1 : C_SYNC_ENABLE);   
+	
+	input [C_B_WIDTH-1 : 0] B;
+	input CLK;
+	input ADD;
+	input C_IN;
+	input B_IN;
+	input CE;
+	input BYPASS;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input B_SIGNED;
+	output OVFL;
+	output C_OUT;
+	output B_OUT;
+	output Q_OVFL;
+	output Q_C_OUT;
+	output Q_B_OUT;
+	output [C_HIGH_BIT : C_LOW_BIT] S;
+	output [C_HIGH_BIT : C_LOW_BIT] Q;
+	
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_OUT_WIDTH-1 : 0] intS;
+	wire [C_OUT_WIDTH-1 : 0] intS_sat0;
+	wire [C_OUT_WIDTH-1 : 0] intS_unsat1;
+	wire [C_OUT_WIDTH-1 : 0] intS_sinsat1;
+	wire [C_OUT_WIDTH-1 : 0] intFB;
+	wire [C_OUT_WIDTH-1 : 0] intFBq;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_sat0;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_unsat1;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_sinsat1;
+	wire intSCLR;
+	wire intSSET;
+	wire intSCLR_TO_ADDER;
+	wire intSSET_TO_ADDER;
+	wire intSCLR_TO_MSB;
+	wire intSSET_TO_MSB;
+	wire intSCLR_TO_REST;
+	wire intSSET_TO_REST;
+	wire intB_SIGNED;
+	wire intBYPASSbar;
+	wire intC_OUT;
+	wire intB_OUT;
+	wire Q_C_OUT;
+	wire Q_B_OUT;
+	wire OVFL;
+	wire Q_OVFL;
+	wire intC_OUT_sat0;
+	wire intB_OUT_sat0;
+	wire Q_C_OUT_sat0;
+	wire Q_B_OUT_sat0;
+	wire OVFL_sat0;
+	wire Q_OVFL_sat0;
+	wire intC_OUT_unsat1;
+	wire intB_OUT_unsat1;
+	wire Q_C_OUT_unsat1;
+	wire Q_B_OUT_unsat1;
+	wire OVFL_unsat1;
+	wire Q_OVFL_unsat1;
+	wire intC_OUT_sinsat1;
+	wire intB_OUT_sinsat1;
+	wire Q_C_OUT_sinsat1;
+	wire Q_B_OUT_sinsat1;
+	wire OVFL_sinsat1;
+	wire Q_OVFL_sinsat1;
+    wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode
+	wire tempCE;
+
+	
+	wire tmpsetsatlogic_un00;
+	wire tmpsetsatlogic_un01;
+	wire tmpsetsatlogic_un10;
+	wire tmpsetsatlogic_un11c;
+	wire tmpsetsatlogic_un11s;
+	
+	wire tmpclrsatlogic_un00;
+	wire tmpclrsatlogic_un01;
+	wire tmpclrsatlogic_un10;
+	wire tmpclrsatlogic_un11c;
+	wire tmpclrsatlogic_un11s;
+	
+	wire tmpsetsatlogicmsb_sg00;
+	wire tmpsetsatlogicmsb_sg01;
+	wire tmpsetsatlogicmsb_sg10;
+	wire tmpsetsatlogicmsb_sg11c;
+	wire tmpsetsatlogicmsb_sg11s;
+	
+	wire tmpsetsatlogicrest_sg00;
+	wire tmpsetsatlogicrest_sg01;
+	wire tmpsetsatlogicrest_sg10;
+	wire tmpsetsatlogicrest_sg11c;
+	wire tmpsetsatlogicrest_sg11s;
+	
+	wire tmpclrsatlogicmsb_sg00;
+	wire tmpclrsatlogicmsb_sg01;
+	wire tmpclrsatlogicmsb_sg10;
+	wire tmpclrsatlogicmsb_sg11c;
+	wire tmpclrsatlogicmsb_sg11s;
+	
+	wire tmpclrsatlogicrest_sg00;
+	wire tmpclrsatlogicrest_sg01;
+	wire tmpclrsatlogicrest_sg10;
+	wire tmpclrsatlogicrest_sg11c;
+	wire tmpclrsatlogicrest_sg11s;
+
+    wire addsetBaseSig ;
+	wire subsetBaseSig ;
+	wire addsubsetBaseSig ;
+	wire addclrBaseSig ;
+	wire subclrBaseSig ;
+	wire addsubclrBaseSig ;
+
+	wire addsetBasePin ;
+	wire subsetBasePin ;
+	wire addsubsetBasePin ;
+	wire addclrBasePin ;
+	wire subclrBasePin ;
+	wire addsubclrBasePin ;
+
+	wire addsetBase ;
+	wire subsetBase ;
+	wire addsubsetBase ;
+	wire addclrBase ;
+	wire subclrBase ;
+	wire addsubclrBase ;
+
+	wire intCE ;
+	wire intB ;
+    wire [C_B_WIDTH : 0] intBconst;
+    
+	wire [C_HIGH_BIT : C_LOW_BIT] Q = intFBq;
+	wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs);
+	wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx);
+	wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx);
+	
+	
+	// Sort out default values for missing ports
+	
+	assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0);
+	assign intBYPASSbar = (C_BYPASS_LOW == 1 ? BYPASS : ~BYPASS);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+    assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; //assign new c_has_bypass_with_cin parameter to internal wire
+    assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B;
+	
+    // Now make up the design from other baseblox
+	// An addsub for when no saturation logic is required...
+	C_ADDSUB_V5_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					(C_B_TYPE == `c_pin )? `c_signed : C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					C_HAS_ACLR,
+					C_HAS_ADD,
+					C_HAS_AINIT,
+					C_HAS_ASET,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+                    C_HAS_B_IN,
+					C_HAS_B_OUT,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					C_HAS_C_OUT,
+					C_HAS_OVFL,
+					1,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					C_HAS_S,
+					C_HAS_SCLR,
+					C_HAS_SINIT,
+					C_HAS_SSET,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		sat0_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_sat0), .C_OUT(intC_OUT_sat0), 
+					.B_OUT(intB_OUT_sat0), .Q_OVFL(Q_OVFL_sat0),
+					.Q_C_OUT(Q_C_OUT_sat0), .Q_B_OUT(Q_B_OUT_sat0),
+					.S(intS_sat0), .Q(intFBq_sat0));
+					
+					
+	// Another addsub for when saturation logic IS required, but only for unsigned data				
+	C_ADDSUB_V5_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					0,
+					C_HAS_ADD,
+					0,
+					0,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+					C_HAS_B_IN,
+					1,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					1,
+					C_HAS_OVFL,
+					1,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					C_HAS_S,
+					1,
+					0,
+					1,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					tempSyncEnable,
+					C_SYNC_PRIORITY)
+		unsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_TO_ADDER), .SSET(intSSET_TO_ADDER), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_unsat1), .C_OUT(intC_OUT_unsat1), 
+					.B_OUT(intB_OUT_unsat1), .Q_OVFL(Q_OVFL_unsat1),
+					.Q_C_OUT(Q_C_OUT_unsat1), .Q_B_OUT(Q_B_OUT_unsat1),
+					.S(intS_unsat1), .Q(intFBq_unsat1));
+					
+	// Another addsub for when saturation logic IS required, but for signed data				
+	C_ADDSUB_V5_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					C_HAS_ACLR,
+					C_HAS_ADD,
+					C_HAS_AINIT,
+					C_HAS_ASET,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+					C_HAS_B_IN,
+					1,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					1,
+					C_HAS_OVFL,
+					0,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					1,
+					C_HAS_SCLR,
+					C_HAS_SINIT,
+					C_HAS_SSET,
+					outwidth_min_one,
+			        1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					tempSyncEnable, // wasC_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		sinsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_sinsat1), .C_OUT(intC_OUT_sinsat1), 
+					.B_OUT(intB_OUT_sinsat1), .Q_OVFL(Q_OVFL_sinsat1),
+					.Q_C_OUT(Q_C_OUT_sinsat1), .Q_B_OUT(Q_B_OUT_sinsat1),
+					.S(intS_sinsat1), .Q());
+					
+	// Registers for output of the last addsub
+	C_REG_FD_V5_0 #(C_AINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8],
+					C_ENABLE_RLOCS,
+					0,
+					0,
+					0,
+					C_HAS_CE,
+					1,
+					0,
+					1,
+					C_SINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8],
+					tempSyncEnable, //C_SYNC_ENABLE,
+					C_SYNC_PRIORITY,
+					1)
+			msb_reg(.D(intS_sinsat1[outwidth_min_one]), .CLK(CLK),
+					.CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_TO_MSB), .SSET(intSSET_TO_MSB),
+					.SINIT(SINIT), .Q(intFBq_sinsat1[outwidth_min_one]));
+						
+	// Need the ?: on the value of C_B_WIDTH in case it == 1
+	C_REG_FD_V5_0 #(C_AINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0],
+					C_ENABLE_RLOCS,
+					0,
+					0,
+					0,
+					C_HAS_CE,
+					1,
+					0,
+					1,
+					C_SINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0],
+					tempSyncEnable, //C_SYNC_ENABLE,
+					C_SYNC_PRIORITY,
+					(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)
+			rest_reg(.D(intS_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]), .CLK(CLK),
+					 .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					 .SCLR((C_B_WIDTH == 1 ? intSCLR_TO_MSB : intSCLR_TO_REST)), .SSET((C_B_WIDTH == 1 ? intSSET_TO_MSB : intSSET_TO_REST)),
+					 .SINIT(SINIT), .Q(intFBq_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]));
+						
+	
+	// Sort out the choices from all these output signals...
+	assign tempCE = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? (CE | intSSET | intSCLR) : CE);
+    assign intCE = (C_SATURATE == 0 ? CE : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 1)) ? ((C_BYPASS_ENABLE == `c_override) ?  (~BYPASS | tempCE) : tempCE) : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 0)) ? ((C_BYPASS_ENABLE == `c_override) ? (BYPASS | tempCE) : tempCE) : tempCE))) ;
+    
+	assign intC_OUT = (C_SATURATE == 0 ? intC_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intC_OUT_unsat1 : intC_OUT_sinsat1));	
+	assign intB_OUT = (C_SATURATE == 0 ? intB_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intB_OUT_unsat1 : intB_OUT_sinsat1));	
+	assign OVFL = (C_SATURATE == 0 ? OVFL_sat0 : (C_B_TYPE == `c_unsigned ? OVFL_unsat1 : OVFL_sinsat1));
+	assign Q_C_OUT = (C_SATURATE == 0 ? Q_C_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_C_OUT_unsat1 : Q_C_OUT_sinsat1));	
+	assign Q_B_OUT = (C_SATURATE == 0 ? Q_B_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_B_OUT_unsat1 : Q_B_OUT_sinsat1));	
+	assign Q_OVFL = (C_SATURATE == 0 ? Q_OVFL_sat0 : (C_B_TYPE == `c_unsigned ? Q_OVFL_unsat1 : Q_OVFL_sinsat1));
+	assign intS = (C_SATURATE == 0 ? intS_sat0 : (C_B_TYPE == `c_unsigned ? intS_unsat1 : intS_sinsat1));
+	assign intFBq = (C_SATURATE == 0 ? intFBq_sat0 : (C_B_TYPE == `c_unsigned ? intFBq_unsat1 : intFBq_sinsat1));
+	
+
+	// COMPLEX decisions on what to feed to the local control sigs...
+	// The signal name suffices denote: un = unsigned, sg = signed, 00 = has neither sset nor sclr, 01 = has sclr only etc
+	// 11c = has bot sset and sclr and sclr dominates, 11s = sset dominates, etc
+	
+	// Unsigned version first
+	assign tmpsetsatlogic_un00 = (C_ADD_MODE == `c_add ? intC_OUT : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ADD)));
+	assign tmpsetsatlogic_un01 = (C_ADD_MODE == `c_add ? (intC_OUT & ~intSCLR) : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ~intSCLR & ADD)));
+	assign tmpsetsatlogic_un10 = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((intC_OUT & ADD) | intSSET)));
+	assign tmpsetsatlogic_un11c = (C_ADD_MODE == `c_add ? (~intSCLR & (intC_OUT | intSSET)) : (C_ADD_MODE == `c_sub ? (~intSCLR & intSSET) : ((~intSCLR & intC_OUT & ADD) | (intSSET & ~intSCLR))));
+	assign tmpsetsatlogic_un11s = (C_ADD_MODE == `c_add ? ((~intSCLR && intC_OUT) | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((~intSCLR & intC_OUT & ADD) | intSSET)));
+	
+//	assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? ~intB_OUT : (~intC_OUT & ~ADD)));
+    assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intB_OUT & BYPASS) : (~intB_OUT & ~BYPASS)): ~intB_OUT) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1  ? ((~intC_OUT & ~ADD) & BYPASS) : ((~intC_OUT & ~ADD) & ~BYPASS)) : (~intC_OUT & ~ADD))));
+//  assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT | intSCLR) : (intSCLR | (~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) | intSCLR) : ((~intB_OUT & ~BYPASS) | intSCLR)) : (~intB_OUT | intSCLR)) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1  ? (intSCLR | ((~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intC_OUT & ~ADD)))));
+//	assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT & ~intSSET) : (~intSSET & ~intC_OUT & ~ADD)));
+  	assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) & ~intSSET) : ((~intB_OUT & ~BYPASS) & ~intSSET)): (~intB_OUT & ~intSSET)) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (~intSSET & (~intC_OUT & ~ADD) & BYPASS) : (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS))) : (~intSSET & ~intC_OUT & ~ADD)))));
+//	assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (intSCLR | (~intB_OUT & ~intSSET)) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (intSCLR | ((~intB_OUT & BYPASS) & ~intSSET)) : (intSCLR | ((~intB_OUT & ~BYPASS) & ~intSSET))) : (intSCLR | (~intB_OUT & ~intSSET))) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))))));
+//	assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (~intSSET & (intSCLR | ~intB_OUT)) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intSSET & (intSCLR | (~intB_OUT & BYPASS))) : (~intSSET & (intSCLR | (~intB_OUT & ~BYPASS)))) : (~intSSET & (intSCLR | ~intB_OUT))) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & BYPASS))):  ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS)))) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD)))));
+	
+	assign intSSET_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogic_un00 : tmpsetsatlogic_un01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogic_un10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogic_un11c : tmpsetsatlogic_un11s)));
+										
+	assign intSCLR_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogic_un00 : tmpclrsatlogic_un01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogic_un10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogic_un11c : tmpclrsatlogic_un11s)));
+										
+	// Now all the signals for the signed version
+	 assign intB = intBconst[C_B_WIDTH-1];
+    //assign intB = (C_B_CONSTANT == 1 ? (C_B_VALUE[(C_B_WIDTH*8)-1 : (C_B_WIDTH-1)*8] == "0" ? 1'b0 : 1'b1) : B[C_B_WIDTH-1]) ;
+
+	assign addclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)) ;
+	assign addsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB) ;
+	assign subclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB) ;
+	assign subsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB)) ;
+	assign addsubclrBaseSig = ((~ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB)) | (ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)))) ;
+	assign addsubsetBaseSig = ((~ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB))) | (ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB))) ;
+
+	assign addclrBasePin = (~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB));
+	assign addsetBasePin = (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & intB) ;
+	assign subclrBasePin = (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB);
+	assign subsetBasePin = (~(intB_SIGNED) & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & ~(intB));
+	assign addsubclrBasePin = (~(ADD) & (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB)) | (ADD & ((~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)))) ;
+	assign addsubsetBasePin = (~(ADD) & ((~intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & ~intB))) | (ADD & intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & intB) ;
+
+    assign addclrBase = (C_HAS_B_SIGNED == 0 ? addclrBaseSig : addclrBasePin);
+	assign addsetBase = (C_HAS_B_SIGNED == 0 ? addsetBaseSig : addsetBasePin);
+	assign subclrBase = (C_HAS_B_SIGNED == 0 ? subclrBaseSig : subclrBasePin);
+	assign subsetBase = (C_HAS_B_SIGNED == 0 ? subsetBaseSig : subsetBasePin);
+	assign addsubclrBase = (C_HAS_B_SIGNED == 0 ? addsubclrBaseSig : addsubclrBasePin);
+	assign addsubsetBase = (C_HAS_B_SIGNED == 0 ? addsubsetBaseSig : addsubsetBasePin);
+
+	assign tmpsetsatlogicmsb_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addsetBase & intBYPASSbar : addsetBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subsetBase & intBYPASSbar : subsetBase) : (C_HAS_BYPASS == 1 ? addsubsetBase & intBYPASSbar : addsubsetBase) ));							 
+	assign tmpsetsatlogicmsb_sg01 = tmpsetsatlogicmsb_sg00 & ~intSCLR ;							 
+	assign tmpsetsatlogicmsb_sg10 = tmpsetsatlogicmsb_sg00 | intSSET ;								 
+	assign tmpsetsatlogicmsb_sg11c = (tmpsetsatlogicmsb_sg00 | intSSET) & ~intSCLR ;
+	assign tmpsetsatlogicmsb_sg11s = tmpsetsatlogicmsb_sg00 | intSSET ;
+	
+	assign tmpsetsatlogicrest_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addclrBase & intBYPASSbar : addclrBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subclrBase & intBYPASSbar : subclrBase) : (C_HAS_BYPASS == 1 ? addsubclrBase & intBYPASSbar : addsubclrBase) ));									 
+	assign tmpsetsatlogicrest_sg01 = tmpsetsatlogicrest_sg00 & ~intSCLR ;							 
+	assign tmpsetsatlogicrest_sg10 = tmpsetsatlogicrest_sg00 | intSSET ;							 
+	assign tmpsetsatlogicrest_sg11c = (tmpsetsatlogicrest_sg00 | intSSET) & ~intSCLR ;  						  
+	assign tmpsetsatlogicrest_sg11s = tmpsetsatlogicrest_sg00 | intSSET ;  						  
+	
+	assign tmpclrsatlogicmsb_sg00 = tmpsetsatlogicrest_sg00 ;							 
+	assign tmpclrsatlogicmsb_sg01 = tmpsetsatlogicrest_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicmsb_sg10 = tmpsetsatlogicrest_sg00 & ~intSSET ;							 
+	assign tmpclrsatlogicmsb_sg11c = tmpsetsatlogicrest_sg00 | intSCLR ; 						  
+	assign tmpclrsatlogicmsb_sg11s = (tmpsetsatlogicrest_sg00 | intSCLR) & ~intSSET ;  						  
+	
+	assign tmpclrsatlogicrest_sg00 = tmpsetsatlogicmsb_sg00 ;							 
+	assign tmpclrsatlogicrest_sg01 = tmpsetsatlogicmsb_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicrest_sg10 = tmpsetsatlogicmsb_sg00 & ~intSSET ;							 
+	assign tmpclrsatlogicrest_sg11c = tmpsetsatlogicmsb_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicrest_sg11s = (tmpsetsatlogicmsb_sg00 | intSCLR) & ~intSSET ;					 
+	
+	assign intSSET_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg00 : tmpsetsatlogicmsb_sg01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicmsb_sg11c : tmpsetsatlogicmsb_sg11s)));
+										
+	assign intSCLR_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg00 : tmpclrsatlogicmsb_sg01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicmsb_sg11c : tmpclrsatlogicmsb_sg11s)));
+										
+	assign intSSET_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg00 : tmpsetsatlogicrest_sg01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicrest_sg11c : tmpsetsatlogicrest_sg11s)));
+										
+	assign intSCLR_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg00 : tmpclrsatlogicrest_sg01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicrest_sg11c : tmpclrsatlogicrest_sg11s)));
+
+	// Finally we are ready to scale the feedback signal...
+	// If the scaling factor results in NO bits being fed back to the input then we need to handle this!
+	// This is the case if C_SCALE >= C_OUT_WIDTH
+	assign intFB[C_OUT_WIDTH-1-(C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE) : 0] = (C_SCALE >= C_OUT_WIDTH ? {C_OUT_WIDTH{1'b0}} : intFBq[C_OUT_WIDTH-1 : (C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE)]);
+	//assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1'b1)) ?
+	//						{C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}}));
+	assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || C_B_TYPE == `c_pin) ?
+							{C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}}));
+
+							
+	
+											
+	initial
+	begin
+		#1;
+	end
+				
+/* helper functions */
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+		
+	function [C_B_WIDTH - 1 : 0] to_bitsB;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_B_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+				to_bitsB[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bitsB[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bitsB[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bitsB[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+	function max;
+	input a;
+	input b;
+	begin
+		max = (a > b) ? a : b;
+	end
+	endfunction
+		
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_add
+`undef c_sub
+`undef c_add_sub
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef allUKs
+
+
+
+
+
+
+
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V6_0.v

@@ -0,0 +1,663 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_ACCUM_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_ACCUM_V6_0.v
+-- Author - Xilinx
+-- Creation - 15 July 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_ACCUM_V6_0 module
+*/
+
+`timescale 1 ns/10 ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_add 0
+`define c_sub 1
+`define c_add_sub 2
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}}
+
+module C_ACCUM_V6_0 (B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT,
+					  SCLR, SSET, SINIT, B_SIGNED, OVFL, C_OUT, B_OUT,
+					  Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q);
+
+	parameter C_ADD_MODE 		= `c_add;
+	parameter C_AINIT_VAL 		= "0000000000000000";
+	parameter C_BYPASS_ENABLE 	= `c_no_override;
+	parameter C_BYPASS_LOW 		= 0;
+	parameter C_B_CONSTANT 		= 0;
+	parameter C_B_TYPE 			= `c_unsigned;
+	parameter C_B_VALUE 		= "0000000000000000";
+	parameter C_B_WIDTH 		= 16;
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_ADD 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_BYPASS 		= 0;
+	parameter C_HAS_BYPASS_WITH_CIN = 0;
+    parameter C_HAS_B_IN 		= 0;
+	parameter C_HAS_B_OUT 		= 0;
+	parameter C_HAS_B_SIGNED 	= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_C_IN 		= 1;
+	parameter C_HAS_C_OUT 		= 0;
+	parameter C_HAS_OVFL 		= 0;
+	parameter C_HAS_Q_B_OUT 	= 0;
+	parameter C_HAS_Q_C_OUT 	= 0;
+	parameter C_HAS_Q_OVFL 		= 0;
+	parameter C_HAS_S 			= 0; 
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HIGH_BIT 		= 15;
+	parameter C_LOW_BIT 		= 0;
+	parameter C_OUT_WIDTH 		= 16;
+	parameter C_PIPE_STAGES 	= 0;
+	parameter C_SATURATE		= 0;
+	parameter C_SCALE			= 0;
+	parameter C_SINIT_VAL 		= "0000000000000000";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+	
+	// Only for internal consumption (prob with MTI otherwise)
+	parameter outwidth_min_one = C_OUT_WIDTH-1;
+	parameter bwidth_min_one = C_B_WIDTH-1;
+
+    parameter tempSyncEnable = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? 1 : C_SYNC_ENABLE);   
+	
+	input [C_B_WIDTH-1 : 0] B;
+	input CLK;
+	input ADD;
+	input C_IN;
+	input B_IN;
+	input CE;
+	input BYPASS;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input B_SIGNED;
+	output OVFL;
+	output C_OUT;
+	output B_OUT;
+	output Q_OVFL;
+	output Q_C_OUT;
+	output Q_B_OUT;
+	output [C_HIGH_BIT : C_LOW_BIT] S;
+	output [C_HIGH_BIT : C_LOW_BIT] Q;
+	
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_OUT_WIDTH-1 : 0] intS;
+	wire [C_OUT_WIDTH-1 : 0] intS_sat0;
+	wire [C_OUT_WIDTH-1 : 0] intS_unsat1;
+	wire [C_OUT_WIDTH-1 : 0] intS_sinsat1;
+	wire [C_OUT_WIDTH-1 : 0] intFB;
+	wire [C_OUT_WIDTH-1 : 0] intFBq;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_sat0;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_unsat1;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_sinsat1;
+	wire intSCLR;
+	wire intSSET;
+	wire intSCLR_TO_ADDER;
+	wire intSSET_TO_ADDER;
+	wire intSCLR_TO_MSB;
+	wire intSSET_TO_MSB;
+	wire intSCLR_TO_REST;
+	wire intSSET_TO_REST;
+	wire intB_SIGNED;
+	wire intBYPASSbar;
+	wire intC_OUT;
+	wire intB_OUT;
+	wire Q_C_OUT;
+	wire Q_B_OUT;
+	wire OVFL;
+	wire Q_OVFL;
+	wire intC_OUT_sat0;
+	wire intB_OUT_sat0;
+	wire Q_C_OUT_sat0;
+	wire Q_B_OUT_sat0;
+	wire OVFL_sat0;
+	wire Q_OVFL_sat0;
+	wire intC_OUT_unsat1;
+	wire intB_OUT_unsat1;
+	wire Q_C_OUT_unsat1;
+	wire Q_B_OUT_unsat1;
+	wire OVFL_unsat1;
+	wire Q_OVFL_unsat1;
+	wire intC_OUT_sinsat1;
+	wire intB_OUT_sinsat1;
+	wire Q_C_OUT_sinsat1;
+	wire Q_B_OUT_sinsat1;
+	wire OVFL_sinsat1;
+	wire Q_OVFL_sinsat1;
+    wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode
+	wire tempCE;
+
+	
+	wire tmpsetsatlogic_un00;
+	wire tmpsetsatlogic_un01;
+	wire tmpsetsatlogic_un10;
+	wire tmpsetsatlogic_un11c;
+	wire tmpsetsatlogic_un11s;
+	
+	wire tmpclrsatlogic_un00;
+	wire tmpclrsatlogic_un01;
+	wire tmpclrsatlogic_un10;
+	wire tmpclrsatlogic_un11c;
+	wire tmpclrsatlogic_un11s;
+	
+	wire tmpsetsatlogicmsb_sg00;
+	wire tmpsetsatlogicmsb_sg01;
+	wire tmpsetsatlogicmsb_sg10;
+	wire tmpsetsatlogicmsb_sg11c;
+	wire tmpsetsatlogicmsb_sg11s;
+	
+	wire tmpsetsatlogicrest_sg00;
+	wire tmpsetsatlogicrest_sg01;
+	wire tmpsetsatlogicrest_sg10;
+	wire tmpsetsatlogicrest_sg11c;
+	wire tmpsetsatlogicrest_sg11s;
+	
+	wire tmpclrsatlogicmsb_sg00;
+	wire tmpclrsatlogicmsb_sg01;
+	wire tmpclrsatlogicmsb_sg10;
+	wire tmpclrsatlogicmsb_sg11c;
+	wire tmpclrsatlogicmsb_sg11s;
+	
+	wire tmpclrsatlogicrest_sg00;
+	wire tmpclrsatlogicrest_sg01;
+	wire tmpclrsatlogicrest_sg10;
+	wire tmpclrsatlogicrest_sg11c;
+	wire tmpclrsatlogicrest_sg11s;
+
+    wire addsetBaseSig ;
+	wire subsetBaseSig ;
+	wire addsubsetBaseSig ;
+	wire addclrBaseSig ;
+	wire subclrBaseSig ;
+	wire addsubclrBaseSig ;
+
+	wire addsetBasePin ;
+	wire subsetBasePin ;
+	wire addsubsetBasePin ;
+	wire addclrBasePin ;
+	wire subclrBasePin ;
+	wire addsubclrBasePin ;
+
+	wire addsetBase ;
+	wire subsetBase ;
+	wire addsubsetBase ;
+	wire addclrBase ;
+	wire subclrBase ;
+	wire addsubclrBase ;
+
+	wire intCE ;
+	wire intB ;
+    wire [C_B_WIDTH : 0] intBconst;
+    
+	wire [C_HIGH_BIT : C_LOW_BIT] Q = intFBq;
+	wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs);
+	wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx);
+	wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx);
+	parameter temp_C_SCALE = (C_SCALE == 0 ? 1'b1 : C_SCALE);
+	
+	
+	// Sort out default values for missing ports
+	
+	assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0);
+	assign intBYPASSbar = (C_BYPASS_LOW == 1 ? BYPASS : ~BYPASS);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+    assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; //assign new c_has_bypass_with_cin parameter to internal wire
+    assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B;
+	
+    // Now make up the design from other baseblox
+	// An addsub for when no saturation logic is required...
+	C_ADDSUB_V6_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					(C_B_TYPE == `c_pin )? `c_signed : C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					C_HAS_ACLR,
+					C_HAS_ADD,
+					C_HAS_AINIT,
+					C_HAS_ASET,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+                    C_HAS_B_IN,
+					C_HAS_B_OUT,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					C_HAS_C_OUT,
+					C_HAS_OVFL,
+					1,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					C_HAS_S,
+					C_HAS_SCLR,
+					C_HAS_SINIT,
+					C_HAS_SSET,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		sat0_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_sat0), .C_OUT(intC_OUT_sat0), 
+					.B_OUT(intB_OUT_sat0), .Q_OVFL(Q_OVFL_sat0),
+					.Q_C_OUT(Q_C_OUT_sat0), .Q_B_OUT(Q_B_OUT_sat0),
+					.S(intS_sat0), .Q(intFBq_sat0));
+					
+					
+	// Another addsub for when saturation logic IS required, but only for unsigned data				
+	C_ADDSUB_V6_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					0,
+					C_HAS_ADD,
+					0,
+					0,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+					C_HAS_B_IN,
+					1,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					1,
+					C_HAS_OVFL,
+					1,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					C_HAS_S,
+					1,
+					0,
+					1,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					tempSyncEnable,
+					C_SYNC_PRIORITY)
+		unsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_TO_ADDER), .SSET(intSSET_TO_ADDER), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_unsat1), .C_OUT(intC_OUT_unsat1), 
+					.B_OUT(intB_OUT_unsat1), .Q_OVFL(Q_OVFL_unsat1),
+					.Q_C_OUT(Q_C_OUT_unsat1), .Q_B_OUT(Q_B_OUT_unsat1),
+					.S(intS_unsat1), .Q(intFBq_unsat1));
+					
+	// Another addsub for when saturation logic IS required, but for signed data				
+	C_ADDSUB_V6_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					C_HAS_ACLR,
+					C_HAS_ADD,
+					C_HAS_AINIT,
+					C_HAS_ASET,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+					C_HAS_B_IN,
+					1,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					1,
+					C_HAS_OVFL,
+					0,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					1,
+					C_HAS_SCLR,
+					C_HAS_SINIT,
+					C_HAS_SSET,
+					outwidth_min_one,
+			        1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					tempSyncEnable, // wasC_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		sinsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_sinsat1), .C_OUT(intC_OUT_sinsat1), 
+					.B_OUT(intB_OUT_sinsat1), .Q_OVFL(Q_OVFL_sinsat1),
+					.Q_C_OUT(Q_C_OUT_sinsat1), .Q_B_OUT(Q_B_OUT_sinsat1),
+					.S(intS_sinsat1), .Q());
+					
+	// Registers for output of the last addsub
+	C_REG_FD_V6_0 #(00000000, //C_AINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8],
+					C_ENABLE_RLOCS,
+					0,
+					0,
+					0,
+					C_HAS_CE,
+					1,
+					0,
+					1,
+					00000000,//C_SINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8],
+					tempSyncEnable, //C_SYNC_ENABLE,
+					C_SYNC_PRIORITY,
+					1)
+			msb_reg(.D(intS_sinsat1[outwidth_min_one]), .CLK(CLK),
+					.CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_TO_MSB), .SSET(intSSET_TO_MSB),
+					.SINIT(SINIT), .Q(intFBq_sinsat1[outwidth_min_one]));
+						
+	// Need the ?: on the value of C_B_WIDTH in case it == 1
+	C_REG_FD_V6_0 #(00000000, // C_AINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0],
+					C_ENABLE_RLOCS,
+					0,
+					0,
+					0,
+					C_HAS_CE,
+					1,
+					0,
+					1,
+					00000000, //C_SINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0],
+					tempSyncEnable, //C_SYNC_ENABLE,
+					C_SYNC_PRIORITY,
+					(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)
+			rest_reg(.D(intS_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]), .CLK(CLK),
+					 .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					 .SCLR((C_B_WIDTH == 1 ? intSCLR_TO_MSB : intSCLR_TO_REST)), .SSET((C_B_WIDTH == 1 ? intSSET_TO_MSB : intSSET_TO_REST)),
+					 .SINIT(SINIT), .Q(intFBq_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]));
+						
+	
+	// Sort out the choices from all these output signals...
+	assign tempCE = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? (CE | intSSET | intSCLR) : CE);
+    assign intCE = (C_SATURATE == 0 ? CE : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 1)) ? ((C_BYPASS_ENABLE == `c_override) ?  (~BYPASS | tempCE) : tempCE) : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 0)) ? ((C_BYPASS_ENABLE == `c_override) ? (BYPASS | tempCE) : tempCE) : tempCE))) ;
+    
+	assign intC_OUT = (C_SATURATE == 0 ? intC_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intC_OUT_unsat1 : intC_OUT_sinsat1));	
+	assign intB_OUT = (C_SATURATE == 0 ? intB_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intB_OUT_unsat1 : intB_OUT_sinsat1));	
+	assign OVFL = (C_SATURATE == 0 ? OVFL_sat0 : (C_B_TYPE == `c_unsigned ? OVFL_unsat1 : OVFL_sinsat1));
+	assign Q_C_OUT = (C_SATURATE == 0 ? Q_C_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_C_OUT_unsat1 : Q_C_OUT_sinsat1));	
+	assign Q_B_OUT = (C_SATURATE == 0 ? Q_B_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_B_OUT_unsat1 : Q_B_OUT_sinsat1));	
+	assign Q_OVFL = (C_SATURATE == 0 ? Q_OVFL_sat0 : (C_B_TYPE == `c_unsigned ? Q_OVFL_unsat1 : Q_OVFL_sinsat1));
+	assign intS = (C_SATURATE == 0 ? intS_sat0 : (C_B_TYPE == `c_unsigned ? intS_unsat1 : intS_sinsat1));
+	assign intFBq = (C_SATURATE == 0 ? intFBq_sat0 : (C_B_TYPE == `c_unsigned ? intFBq_unsat1 : intFBq_sinsat1));
+	
+
+	// COMPLEX decisions on what to feed to the local control sigs...
+	// The signal name suffices denote: un = unsigned, sg = signed, 00 = has neither sset nor sclr, 01 = has sclr only etc
+	// 11c = has bot sset and sclr and sclr dominates, 11s = sset dominates, etc
+	
+	// Unsigned version first
+	assign tmpsetsatlogic_un00 = (C_ADD_MODE == `c_add ? intC_OUT : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ADD)));
+	assign tmpsetsatlogic_un01 = (C_ADD_MODE == `c_add ? (intC_OUT & ~intSCLR) : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ~intSCLR & ADD)));
+	assign tmpsetsatlogic_un10 = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((intC_OUT & ADD) | intSSET)));
+	assign tmpsetsatlogic_un11c = (C_ADD_MODE == `c_add ? (~intSCLR & (intC_OUT | intSSET)) : (C_ADD_MODE == `c_sub ? (~intSCLR & intSSET) : ((~intSCLR & intC_OUT & ADD) | (intSSET & ~intSCLR))));
+	assign tmpsetsatlogic_un11s = (C_ADD_MODE == `c_add ? ((~intSCLR && intC_OUT) | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((~intSCLR & intC_OUT & ADD) | intSSET)));
+	
+//	assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? ~intB_OUT : (~intC_OUT & ~ADD)));
+    assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intB_OUT & BYPASS) : (~intB_OUT & ~BYPASS)): ~intB_OUT) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1  ? ((~intC_OUT & ~ADD) & BYPASS) : ((~intC_OUT & ~ADD) & ~BYPASS)) : (~intC_OUT & ~ADD))));
+//  assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT | intSCLR) : (intSCLR | (~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) | intSCLR) : ((~intB_OUT & ~BYPASS) | intSCLR)) : (~intB_OUT | intSCLR)) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1  ? (intSCLR | ((~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intC_OUT & ~ADD)))));
+//	assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT & ~intSSET) : (~intSSET & ~intC_OUT & ~ADD)));
+  	assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) & ~intSSET) : ((~intB_OUT & ~BYPASS) & ~intSSET)): (~intB_OUT & ~intSSET)) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (~intSSET & (~intC_OUT & ~ADD) & BYPASS) : (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS))) : (~intSSET & ~intC_OUT & ~ADD)))));
+//	assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (intSCLR | (~intB_OUT & ~intSSET)) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (intSCLR | ((~intB_OUT & BYPASS) & ~intSSET)) : (intSCLR | ((~intB_OUT & ~BYPASS) & ~intSSET))) : (intSCLR | (~intB_OUT & ~intSSET))) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))))));//	assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (~intSSET & (intSCLR | ~intB_OUT)) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intSSET & (intSCLR | (~intB_OUT & BYPASS))) : (~intSSET & (intSCLR | (~intB_OUT & ~BYPASS)))) : (~intSSET & (intSCLR | ~intB_OUT))) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & BYPASS))):  ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS)))) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD)))));
+	
+	assign intSSET_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogic_un00 : tmpsetsatlogic_un01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogic_un10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogic_un11c : tmpsetsatlogic_un11s)));
+										
+	assign intSCLR_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogic_un00 : tmpclrsatlogic_un01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogic_un10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogic_un11c : tmpclrsatlogic_un11s)));
+										
+	// Now all the signals for the signed version
+	 assign intB = intBconst[C_B_WIDTH-1];
+    //assign intB = (C_B_CONSTANT == 1 ? (C_B_VALUE[(C_B_WIDTH*8)-1 : (C_B_WIDTH-1)*8] == "0" ? 1'b0 : 1'b1) : B[C_B_WIDTH-1]) ;
+
+	assign addclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)) ;
+	assign addsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB) ;
+	assign subclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB) ;
+	assign subsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB)) ;
+	assign addsubclrBaseSig = ((~ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB)) | (ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)))) ;
+	assign addsubsetBaseSig = ((~ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB))) | (ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB))) ;
+
+	assign addclrBasePin = (~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB));
+	assign addsetBasePin = (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & intB) ;
+	assign subclrBasePin = (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB);
+	assign subsetBasePin = (~(intB_SIGNED) & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & ~(intB));
+	assign addsubclrBasePin = (~(ADD) & (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB)) | (ADD & ((~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)))) ;
+	assign addsubsetBasePin = (~(ADD) & ((~intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & ~intB))) | (ADD & intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & intB) ;
+
+    assign addclrBase = (C_HAS_B_SIGNED == 0 ? addclrBaseSig : addclrBasePin);
+	assign addsetBase = (C_HAS_B_SIGNED == 0 ? addsetBaseSig : addsetBasePin);
+	assign subclrBase = (C_HAS_B_SIGNED == 0 ? subclrBaseSig : subclrBasePin);
+	assign subsetBase = (C_HAS_B_SIGNED == 0 ? subsetBaseSig : subsetBasePin);
+	assign addsubclrBase = (C_HAS_B_SIGNED == 0 ? addsubclrBaseSig : addsubclrBasePin);
+	assign addsubsetBase = (C_HAS_B_SIGNED == 0 ? addsubsetBaseSig : addsubsetBasePin);
+
+	assign tmpsetsatlogicmsb_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addsetBase & intBYPASSbar : addsetBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subsetBase & intBYPASSbar : subsetBase) : (C_HAS_BYPASS == 1 ? addsubsetBase & intBYPASSbar : addsubsetBase) ));							 
+	assign tmpsetsatlogicmsb_sg01 = tmpsetsatlogicmsb_sg00 & ~intSCLR ;							 
+	assign tmpsetsatlogicmsb_sg10 = tmpsetsatlogicmsb_sg00 | intSSET ;								 
+	assign tmpsetsatlogicmsb_sg11c = (tmpsetsatlogicmsb_sg00 | intSSET) & ~intSCLR ;
+	assign tmpsetsatlogicmsb_sg11s = (tmpsetsatlogicmsb_sg00 & ~intSCLR) | intSSET ;   //new code!!
+	
+	assign tmpsetsatlogicrest_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addclrBase & intBYPASSbar : addclrBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subclrBase & intBYPASSbar : subclrBase) : (C_HAS_BYPASS == 1 ? addsubclrBase & intBYPASSbar : addsubclrBase) ));									 
+	assign tmpsetsatlogicrest_sg01 = tmpsetsatlogicrest_sg00 & ~intSCLR ;							 
+	assign tmpsetsatlogicrest_sg10 = tmpsetsatlogicrest_sg00 | intSSET ;							 
+	assign tmpsetsatlogicrest_sg11c = (tmpsetsatlogicrest_sg00 | intSSET) & ~intSCLR ;  						  
+	assign tmpsetsatlogicrest_sg11s = (tmpsetsatlogicrest_sg00 & (~intSCLR)) | intSSET ;  						  
+	
+	assign tmpclrsatlogicmsb_sg00 = tmpsetsatlogicrest_sg00 ;							 
+	assign tmpclrsatlogicmsb_sg01 = tmpsetsatlogicrest_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicmsb_sg10 = tmpsetsatlogicrest_sg00 & ~intSSET ;							 
+	assign tmpclrsatlogicmsb_sg11c = (tmpsetsatlogicrest_sg00 & ~intSSET) | intSCLR ; // not sure about the intSSET in this one!						  
+	assign tmpclrsatlogicmsb_sg11s = (tmpsetsatlogicrest_sg00 | intSCLR) & ~intSSET ;  						  
+	
+	assign tmpclrsatlogicrest_sg00 = tmpsetsatlogicmsb_sg00 ;							 
+	assign tmpclrsatlogicrest_sg01 = tmpsetsatlogicmsb_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicrest_sg10 = tmpsetsatlogicmsb_sg00 & ~intSSET ;							 
+	assign tmpclrsatlogicrest_sg11c = (tmpsetsatlogicmsb_sg00 & ~intSSET) | intSCLR ; // added to fix reg override sync bug							 
+	assign tmpclrsatlogicrest_sg11s = (tmpsetsatlogicmsb_sg00 | intSCLR) & ~intSSET ;					 
+	
+	assign intSSET_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg00 : tmpsetsatlogicmsb_sg01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicmsb_sg11c : tmpsetsatlogicmsb_sg11s)));
+										
+	assign intSCLR_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg00 : tmpclrsatlogicmsb_sg01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicmsb_sg11c : tmpclrsatlogicmsb_sg11s)));
+										
+	assign intSSET_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg00 : tmpsetsatlogicrest_sg01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicrest_sg11c : tmpsetsatlogicrest_sg11s)));
+										
+	assign intSCLR_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg00 : tmpclrsatlogicrest_sg01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicrest_sg11c : tmpclrsatlogicrest_sg11s)));
+
+	// Finally we are ready to scale the feedback signal...
+	// If the scaling factor results in NO bits being fed back to the input then we need to handle this!
+	// This is the case if C_SCALE >= C_OUT_WIDTH
+	assign intFB[C_OUT_WIDTH-1-(C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE) : 0] = (C_SCALE >= C_OUT_WIDTH ? {C_OUT_WIDTH{1'b0}} : intFBq[C_OUT_WIDTH-1 : (C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE)]);
+	//assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1'b1)) ?
+	//						{C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}}));
+	assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || C_B_TYPE == `c_pin) ?
+							{temp_C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {temp_C_SCALE{1'b0}}));
+
+							
+	
+											
+	initial
+	begin
+		#1;
+	end
+				
+/* helper functions */
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+		
+	function [C_B_WIDTH - 1 : 0] to_bitsB;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_B_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+				to_bitsB[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bitsB[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bitsB[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bitsB[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+	function max;
+	input a;
+	input b;
+	begin
+		max = (a > b) ? a : b;
+	end
+	endfunction
+		
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_add
+`undef c_sub
+`undef c_add_sub
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef allUKs
+
+
+
+
+
+
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V7_0.v

@@ -0,0 +1,692 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Id: C_ACCUM_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_ACCUM_V7_0.v
+-- Author - Xilinx
+-- Creation - 15 July 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_ACCUM_V7_0 module
+*/
+
+`timescale 1 ns/10 ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_add 0
+`define c_sub 1
+`define c_add_sub 2
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}}
+
+module C_ACCUM_V7_0 (B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT,
+					  SCLR, SSET, SINIT, B_SIGNED, OVFL, C_OUT, B_OUT,
+					  Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q);
+
+	parameter C_ADD_MODE 		= `c_add;
+	parameter C_AINIT_VAL 		= "0000000000000000";
+	parameter C_BYPASS_ENABLE 	= `c_no_override;
+	parameter C_BYPASS_LOW 		= 0;
+	parameter C_B_CONSTANT 		= 0;
+	parameter C_B_TYPE 			= `c_unsigned;
+	parameter C_B_VALUE 		= "0000000000000000";
+	parameter C_B_WIDTH 		= 16;
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_ADD 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_BYPASS 		= 0;
+	parameter C_HAS_BYPASS_WITH_CIN = 0;
+    parameter C_HAS_B_IN 		= 0;
+	parameter C_HAS_B_OUT 		= 0;
+	parameter C_HAS_B_SIGNED 	= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_C_IN 		= 1;
+	parameter C_HAS_C_OUT 		= 0;
+	parameter C_HAS_OVFL 		= 0;
+	parameter C_HAS_Q_B_OUT 	= 0;
+	parameter C_HAS_Q_C_OUT 	= 0;
+	parameter C_HAS_Q_OVFL 		= 0;
+	parameter C_HAS_S 			= 0; 
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HIGH_BIT 		= 15;
+	parameter C_LOW_BIT 		= 0;
+	parameter C_OUT_WIDTH 		= 16;
+	parameter C_PIPE_STAGES 	= 0;
+	parameter C_SATURATE		= 0;
+	parameter C_SCALE			= 0;
+	parameter C_SINIT_VAL 		= "0000000000000000";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+	
+	// Only for internal consumption (prob with MTI otherwise)
+	parameter outwidth_min_one = C_OUT_WIDTH-1;
+	parameter bwidth_min_one = C_B_WIDTH-1;
+
+    parameter tempSyncEnable = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? 1 : C_SYNC_ENABLE);   
+	
+	input [C_B_WIDTH-1 : 0] B;
+	input CLK;
+	input ADD;
+	input C_IN;
+	input B_IN;
+	input CE;
+	input BYPASS;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input B_SIGNED;
+	output OVFL;
+	output C_OUT;
+	output B_OUT;
+	output Q_OVFL;
+	output Q_C_OUT;
+	output Q_B_OUT;
+	output [C_HIGH_BIT : C_LOW_BIT] S;
+	output [C_HIGH_BIT : C_LOW_BIT] Q;
+	
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_OUT_WIDTH-1 : 0] intS;
+	wire [C_OUT_WIDTH-1 : 0] intS_sat0;
+	wire [C_OUT_WIDTH-1 : 0] intS_unsat1;
+	wire [C_OUT_WIDTH-1 : 0] intS_sinsat1;
+	wire [C_OUT_WIDTH-1 : 0] intFB;
+	wire [C_OUT_WIDTH-1 : 0] intFBq;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_sat0;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_unsat1;
+	wire [C_OUT_WIDTH-1 : 0] intFBq_sinsat1;
+	wire intSCLR;
+	wire intSSET;
+	wire intSCLR_TO_ADDER;
+	wire intSSET_TO_ADDER;
+	wire intSCLR_TO_MSB;
+	wire intSSET_TO_MSB;
+	wire intSCLR_TO_REST;
+	wire intSSET_TO_REST;
+	wire intB_SIGNED;
+	wire intBYPASSbar;
+	wire intC_OUT;
+	wire intB_OUT;
+	wire Q_C_OUT;
+	wire Q_B_OUT;
+	wire OVFL;
+	wire Q_OVFL;
+	wire intC_OUT_sat0;
+	wire intB_OUT_sat0;
+	wire Q_C_OUT_sat0;
+	wire Q_B_OUT_sat0;
+	wire OVFL_sat0;
+	wire Q_OVFL_sat0;
+	wire intC_OUT_unsat1;
+	wire intB_OUT_unsat1;
+	wire Q_C_OUT_unsat1;
+	wire Q_B_OUT_unsat1;
+	wire OVFL_unsat1;
+	wire Q_OVFL_unsat1;
+	wire intC_OUT_sinsat1;
+	wire intB_OUT_sinsat1;
+	wire Q_C_OUT_sinsat1;
+	wire Q_B_OUT_sinsat1;
+	wire OVFL_sinsat1;
+	wire Q_OVFL_sinsat1;
+    wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode
+	wire tempCE;
+
+	
+	wire tmpsetsatlogic_un00;
+	wire tmpsetsatlogic_un01;
+	wire tmpsetsatlogic_un10;
+	wire tmpsetsatlogic_un11c;
+	wire tmpsetsatlogic_un11s;
+	
+	wire tmpclrsatlogic_un00;
+	wire tmpclrsatlogic_un01;
+	wire tmpclrsatlogic_un10;
+	wire tmpclrsatlogic_un11c;
+	wire tmpclrsatlogic_un11s;
+	
+	wire tmpsetsatlogicmsb_sg00;
+	wire tmpsetsatlogicmsb_sg01;
+	wire tmpsetsatlogicmsb_sg10;
+	wire tmpsetsatlogicmsb_sg11c;
+	wire tmpsetsatlogicmsb_sg11s;
+	
+	wire tmpsetsatlogicrest_sg00;
+	wire tmpsetsatlogicrest_sg01;
+	wire tmpsetsatlogicrest_sg10;
+	wire tmpsetsatlogicrest_sg11c;
+	wire tmpsetsatlogicrest_sg11s;
+	
+	wire tmpclrsatlogicmsb_sg00;
+	wire tmpclrsatlogicmsb_sg01;
+	wire tmpclrsatlogicmsb_sg10;
+	wire tmpclrsatlogicmsb_sg11c;
+	wire tmpclrsatlogicmsb_sg11s;
+	
+	wire tmpclrsatlogicrest_sg00;
+	wire tmpclrsatlogicrest_sg01;
+	wire tmpclrsatlogicrest_sg10;
+	wire tmpclrsatlogicrest_sg11c;
+	wire tmpclrsatlogicrest_sg11s;
+
+    wire addsetBaseSig ;
+	wire subsetBaseSig ;
+	wire addsubsetBaseSig ;
+	wire addclrBaseSig ;
+	wire subclrBaseSig ;
+	wire addsubclrBaseSig ;
+
+	wire addsetBasePin ;
+	wire subsetBasePin ;
+	wire addsubsetBasePin ;
+	wire addclrBasePin ;
+	wire subclrBasePin ;
+	wire addsubclrBasePin ;
+
+	wire addsetBase ;
+	wire subsetBase ;
+	wire addsubsetBase ;
+	wire addclrBase ;
+	wire subclrBase ;
+	wire addsubclrBase ;
+
+	wire intCE ;
+	wire intB ;
+    wire [C_B_WIDTH : 0] intBconst;
+    
+	wire [C_HIGH_BIT : C_LOW_BIT] Q = intFBq;
+	wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs);
+	wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx);
+	wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx);
+	parameter temp_C_SCALE = (C_SCALE == 0 ? 1'b1 : C_SCALE);
+	
+	
+	// Sort out default values for missing ports
+	
+	assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0);
+	assign intBYPASSbar = (C_BYPASS_LOW == 1 ? BYPASS : ~BYPASS);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+    assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; //assign new c_has_bypass_with_cin parameter to internal wire
+    assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B;
+	
+    // Now make up the design from other baseblox
+	// An addsub for when no saturation logic is required...
+	C_ADDSUB_V7_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					(C_B_TYPE == `c_pin )? `c_signed : C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					C_HAS_ACLR,
+					C_HAS_ADD,
+					C_HAS_AINIT,
+					C_HAS_ASET,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+                    C_HAS_B_IN,
+					C_HAS_B_OUT,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					C_HAS_C_OUT,
+					C_HAS_OVFL,
+					1,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					C_HAS_S,
+					C_HAS_SCLR,
+					C_HAS_SINIT,
+					C_HAS_SSET,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					C_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		sat0_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_sat0), .C_OUT(intC_OUT_sat0), 
+					.B_OUT(intB_OUT_sat0), .Q_OVFL(Q_OVFL_sat0),
+					.Q_C_OUT(Q_C_OUT_sat0), .Q_B_OUT(Q_B_OUT_sat0),
+					.S(intS_sat0), .Q(intFBq_sat0));
+					
+					
+	// Another addsub for when saturation logic IS required, but only for unsigned data				
+	C_ADDSUB_V7_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					0,
+					C_HAS_ADD,
+					0,
+					0,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+					C_HAS_B_IN,
+					1,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					1,
+					C_HAS_OVFL,
+					1,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					C_HAS_S,
+					1,
+					0,
+					1,
+					outwidth_min_one,
+			                1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					tempSyncEnable,
+					C_SYNC_PRIORITY)
+		unsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_TO_ADDER), .SSET(intSSET_TO_ADDER), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_unsat1), .C_OUT(intC_OUT_unsat1), 
+					.B_OUT(intB_OUT_unsat1), .Q_OVFL(Q_OVFL_unsat1),
+					.Q_C_OUT(Q_C_OUT_unsat1), .Q_B_OUT(Q_B_OUT_unsat1),
+					.S(intS_unsat1), .Q(intFBq_unsat1));
+					
+	// Another addsub for when saturation logic IS required, but for signed data				
+	C_ADDSUB_V7_0 #(C_ADD_MODE, 
+					C_AINIT_VAL, 
+					C_B_TYPE, 
+					C_OUT_WIDTH,
+					C_BYPASS_ENABLE,
+					C_BYPASS_LOW, 
+					C_B_CONSTANT,
+					C_B_TYPE,
+					C_B_VALUE,
+					C_B_WIDTH,
+					C_ENABLE_RLOCS,
+					C_HAS_ACLR,
+					C_HAS_ADD,
+					C_HAS_AINIT,
+					C_HAS_ASET,
+					C_HAS_B_SIGNED,
+					C_HAS_BYPASS,
+                    C_HAS_BYPASS_WITH_CIN,
+					C_HAS_B_IN,
+					1,
+					C_HAS_B_SIGNED,
+					C_HAS_CE,
+					C_HAS_C_IN,
+					1,
+					C_HAS_OVFL,
+					0,
+					C_HAS_Q_B_OUT,
+					C_HAS_Q_C_OUT,
+					C_HAS_Q_OVFL,
+					1,
+					C_HAS_SCLR,
+					C_HAS_SINIT,
+					C_HAS_SSET,
+					outwidth_min_one,
+			        1,
+					0,
+					C_OUT_WIDTH,
+					C_PIPE_STAGES,
+					C_SINIT_VAL,
+					tempSyncEnable, // wasC_SYNC_ENABLE,
+					C_SYNC_PRIORITY)
+		sinsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD),
+					.C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
+					.OVFL(OVFL_sinsat1), .C_OUT(intC_OUT_sinsat1), 
+					.B_OUT(intB_OUT_sinsat1), .Q_OVFL(Q_OVFL_sinsat1),
+					.Q_C_OUT(Q_C_OUT_sinsat1), .Q_B_OUT(Q_B_OUT_sinsat1),
+					.S(intS_sinsat1), .Q());
+					
+	// Registers for output of the last addsub
+	C_REG_FD_V7_0 #(00000000, //C_AINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8],
+					C_ENABLE_RLOCS,
+					0,
+					0,
+					0,
+					C_HAS_CE,
+					1,
+					0,
+					1,
+					00000000,//C_SINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8],
+					tempSyncEnable, //C_SYNC_ENABLE,
+					C_SYNC_PRIORITY,
+					1)
+			msb_reg(.D(intS_sinsat1[outwidth_min_one]), .CLK(CLK),
+					.CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_TO_MSB), .SSET(intSSET_TO_MSB),
+					.SINIT(SINIT), .Q(intFBq_sinsat1[outwidth_min_one]));
+						
+	// Need the ?: on the value of C_B_WIDTH in case it == 1
+	C_REG_FD_V7_0 #(00000000, // C_AINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0],
+					C_ENABLE_RLOCS,
+					0,
+					0,
+					0,
+					C_HAS_CE,
+					1,
+					0,
+					1,
+					00000000, //C_SINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0],
+					tempSyncEnable, //C_SYNC_ENABLE,
+					C_SYNC_PRIORITY,
+					(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)
+			rest_reg(.D(intS_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]), .CLK(CLK),
+					 .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					 .SCLR((C_B_WIDTH == 1 ? intSCLR_TO_MSB : intSCLR_TO_REST)), .SSET((C_B_WIDTH == 1 ? intSSET_TO_MSB : intSSET_TO_REST)),
+					 .SINIT(SINIT), .Q(intFBq_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]));
+						
+	
+	// Sort out the choices from all these output signals...
+	assign tempCE = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? (CE | intSSET | intSCLR) : CE);
+    assign intCE = (C_SATURATE == 0 ? CE : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 1)) ? ((C_BYPASS_ENABLE == `c_override) ?  (~BYPASS | tempCE) : tempCE) : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 0)) ? ((C_BYPASS_ENABLE == `c_override) ? (BYPASS | tempCE) : tempCE) : tempCE))) ;
+    
+	assign intC_OUT = (C_SATURATE == 0 ? intC_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intC_OUT_unsat1 : intC_OUT_sinsat1));	
+	assign intB_OUT = (C_SATURATE == 0 ? intB_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intB_OUT_unsat1 : intB_OUT_sinsat1));	
+	assign OVFL = (C_SATURATE == 0 ? OVFL_sat0 : (C_B_TYPE == `c_unsigned ? OVFL_unsat1 : OVFL_sinsat1));
+	assign Q_C_OUT = (C_SATURATE == 0 ? Q_C_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_C_OUT_unsat1 : Q_C_OUT_sinsat1));	
+	assign Q_B_OUT = (C_SATURATE == 0 ? Q_B_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_B_OUT_unsat1 : Q_B_OUT_sinsat1));	
+	assign Q_OVFL = (C_SATURATE == 0 ? Q_OVFL_sat0 : (C_B_TYPE == `c_unsigned ? Q_OVFL_unsat1 : Q_OVFL_sinsat1));
+	assign intS = (C_SATURATE == 0 ? intS_sat0 : (C_B_TYPE == `c_unsigned ? intS_unsat1 : intS_sinsat1));
+	assign intFBq = (C_SATURATE == 0 ? intFBq_sat0 : (C_B_TYPE == `c_unsigned ? intFBq_unsat1 : intFBq_sinsat1));
+	
+
+	// COMPLEX decisions on what to feed to the local control sigs...
+	// The signal name suffices denote: un = unsigned, sg = signed, 00 = has neither sset nor sclr, 01 = has sclr only etc
+	// 11c = has bot sset and sclr and sclr dominates, 11s = sset dominates, etc
+	
+	// Unsigned version first
+	assign tmpsetsatlogic_un00 = (C_ADD_MODE == `c_add ? intC_OUT : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ADD)));
+	assign tmpsetsatlogic_un01 = (C_ADD_MODE == `c_add ? (intC_OUT & ~intSCLR) : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ~intSCLR & ADD)));
+	assign tmpsetsatlogic_un10 = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((intC_OUT & ADD) | intSSET)));
+	assign tmpsetsatlogic_un11c = (C_ADD_MODE == `c_add ? (~intSCLR & (intC_OUT | intSSET)) : (C_ADD_MODE == `c_sub ? (~intSCLR & intSSET) : ((~intSCLR & intC_OUT & ADD) | (intSSET & ~intSCLR))));
+	assign tmpsetsatlogic_un11s = (C_ADD_MODE == `c_add ? ((~intSCLR && intC_OUT) | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((~intSCLR & intC_OUT & ADD) | intSSET)));
+	
+//	assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? ~intB_OUT : (~intC_OUT & ~ADD)));
+    assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intB_OUT & BYPASS) : (~intB_OUT & ~BYPASS)): ~intB_OUT) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1  ? ((~intC_OUT & ~ADD) & BYPASS) : ((~intC_OUT & ~ADD) & ~BYPASS)) : (~intC_OUT & ~ADD))));
+//  assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT | intSCLR) : (intSCLR | (~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) | intSCLR) : ((~intB_OUT & ~BYPASS) | intSCLR)) : (~intB_OUT | intSCLR)) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1  ? (intSCLR | ((~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intC_OUT & ~ADD)))));
+//	assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT & ~intSSET) : (~intSSET & ~intC_OUT & ~ADD)));
+  	assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) & ~intSSET) : ((~intB_OUT & ~BYPASS) & ~intSSET)): (~intB_OUT & ~intSSET)) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (~intSSET & (~intC_OUT & ~ADD) & BYPASS) : (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS))) : (~intSSET & ~intC_OUT & ~ADD)))));
+//	assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (intSCLR | (~intB_OUT & ~intSSET)) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (intSCLR | ((~intB_OUT & BYPASS) & ~intSSET)) : (intSCLR | ((~intB_OUT & ~BYPASS) & ~intSSET))) : (intSCLR | (~intB_OUT & ~intSSET))) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))))));//	assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (~intSSET & (intSCLR | ~intB_OUT)) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD))));
+	assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intSSET & (intSCLR | (~intB_OUT & BYPASS))) : (~intSSET & (intSCLR | (~intB_OUT & ~BYPASS)))) : (~intSSET & (intSCLR | ~intB_OUT))) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & BYPASS))):  ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS)))) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD)))));
+	
+	assign intSSET_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogic_un00 : tmpsetsatlogic_un01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogic_un10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogic_un11c : tmpsetsatlogic_un11s)));
+										
+	assign intSCLR_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogic_un00 : tmpclrsatlogic_un01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogic_un10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogic_un11c : tmpclrsatlogic_un11s)));
+										
+	// Now all the signals for the signed version
+	 assign intB = intBconst[C_B_WIDTH-1];
+    //assign intB = (C_B_CONSTANT == 1 ? (C_B_VALUE[(C_B_WIDTH*8)-1 : (C_B_WIDTH-1)*8] == "0" ? 1'b0 : 1'b1) : B[C_B_WIDTH-1]) ;
+
+	assign addclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)) ;
+	assign addsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB) ;
+	assign subclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB) ;
+	assign subsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB)) ;
+	assign addsubclrBaseSig = ((~ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB)) | (ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)))) ;
+	assign addsubsetBaseSig = ((~ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB))) | (ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB))) ;
+
+	assign addclrBasePin = (~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB));
+	assign addsetBasePin = (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & intB) ;
+	assign subclrBasePin = (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB);
+	assign subsetBasePin = (~(intB_SIGNED) & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & ~(intB));
+	assign addsubclrBasePin = (~(ADD) & (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB)) | (ADD & ((~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)))) ;
+	assign addsubsetBasePin = (~(ADD) & ((~intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & ~intB))) | (ADD & intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & intB) ;
+
+    assign addclrBase = (C_HAS_B_SIGNED == 0 ? addclrBaseSig : addclrBasePin);
+	assign addsetBase = (C_HAS_B_SIGNED == 0 ? addsetBaseSig : addsetBasePin);
+	assign subclrBase = (C_HAS_B_SIGNED == 0 ? subclrBaseSig : subclrBasePin);
+	assign subsetBase = (C_HAS_B_SIGNED == 0 ? subsetBaseSig : subsetBasePin);
+	assign addsubclrBase = (C_HAS_B_SIGNED == 0 ? addsubclrBaseSig : addsubclrBasePin);
+	assign addsubsetBase = (C_HAS_B_SIGNED == 0 ? addsubsetBaseSig : addsubsetBasePin);
+
+	assign tmpsetsatlogicmsb_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addsetBase & intBYPASSbar : addsetBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subsetBase & intBYPASSbar : subsetBase) : (C_HAS_BYPASS == 1 ? addsubsetBase & intBYPASSbar : addsubsetBase) ));							 
+	assign tmpsetsatlogicmsb_sg01 = tmpsetsatlogicmsb_sg00 & ~intSCLR ;							 
+	assign tmpsetsatlogicmsb_sg10 = tmpsetsatlogicmsb_sg00 | intSSET ;								 
+	assign tmpsetsatlogicmsb_sg11c = (tmpsetsatlogicmsb_sg00 | intSSET) & ~intSCLR ;
+	assign tmpsetsatlogicmsb_sg11s = (tmpsetsatlogicmsb_sg00 & ~intSCLR) | intSSET ;   //new code!!
+	
+	assign tmpsetsatlogicrest_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addclrBase & intBYPASSbar : addclrBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subclrBase & intBYPASSbar : subclrBase) : (C_HAS_BYPASS == 1 ? addsubclrBase & intBYPASSbar : addsubclrBase) ));									 
+	assign tmpsetsatlogicrest_sg01 = tmpsetsatlogicrest_sg00 & ~intSCLR ;							 
+	assign tmpsetsatlogicrest_sg10 = tmpsetsatlogicrest_sg00 | intSSET ;							 
+	assign tmpsetsatlogicrest_sg11c = (tmpsetsatlogicrest_sg00 | intSSET) & ~intSCLR ;  						  
+	assign tmpsetsatlogicrest_sg11s = (tmpsetsatlogicrest_sg00 & (~intSCLR)) | intSSET ;  						  
+	
+	assign tmpclrsatlogicmsb_sg00 = tmpsetsatlogicrest_sg00 ;							 
+	assign tmpclrsatlogicmsb_sg01 = tmpsetsatlogicrest_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicmsb_sg10 = tmpsetsatlogicrest_sg00 & ~intSSET ;							 
+	assign tmpclrsatlogicmsb_sg11c = (tmpsetsatlogicrest_sg00 & ~intSSET) | intSCLR ; // not sure about the intSSET in this one!						  
+	assign tmpclrsatlogicmsb_sg11s = (tmpsetsatlogicrest_sg00 | intSCLR) & ~intSSET ;  						  
+	
+	assign tmpclrsatlogicrest_sg00 = tmpsetsatlogicmsb_sg00 ;							 
+	assign tmpclrsatlogicrest_sg01 = tmpsetsatlogicmsb_sg00 | intSCLR ;							 
+	assign tmpclrsatlogicrest_sg10 = tmpsetsatlogicmsb_sg00 & ~intSSET ;							 
+	assign tmpclrsatlogicrest_sg11c = (tmpsetsatlogicmsb_sg00 & ~intSSET) | intSCLR ; // added to fix reg override sync bug							 
+	assign tmpclrsatlogicrest_sg11s = (tmpsetsatlogicmsb_sg00 | intSCLR) & ~intSSET ;					 
+	
+	assign intSSET_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg00 : tmpsetsatlogicmsb_sg01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicmsb_sg11c : tmpsetsatlogicmsb_sg11s)));
+										
+	assign intSCLR_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg00 : tmpclrsatlogicmsb_sg01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicmsb_sg11c : tmpclrsatlogicmsb_sg11s)));
+										
+	assign intSSET_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg00 : tmpsetsatlogicrest_sg01) :
+									(C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicrest_sg11c : tmpsetsatlogicrest_sg11s)));
+										
+	assign intSCLR_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg00 : tmpclrsatlogicrest_sg01) :
+									(C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg10 : 
+										(C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicrest_sg11c : tmpclrsatlogicrest_sg11s)));
+
+	// Finally we are ready to scale the feedback signal...
+	// If the scaling factor results in NO bits being fed back to the input then we need to handle this!
+	// This is the case if C_SCALE >= C_OUT_WIDTH
+	assign intFB[C_OUT_WIDTH-1-(C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE) : 0] = (C_SCALE >= C_OUT_WIDTH ? {C_OUT_WIDTH{1'b0}} : intFBq[C_OUT_WIDTH-1 : (C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE)]);
+	//assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1'b1)) ?
+	//						{C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}}));
+	assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || C_B_TYPE == `c_pin) ?
+							{temp_C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {temp_C_SCALE{1'b0}}));
+
+							
+	
+											
+	initial
+	begin
+		#1;
+	end
+				
+/* helper functions */
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+		
+	function [C_B_WIDTH - 1 : 0] to_bitsB;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_B_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+				to_bitsB[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bitsB[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bitsB[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bitsB[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+	function max;
+	input a;
+	input b;
+	begin
+		max = (a > b) ? a : b;
+	end
+	endfunction
+		
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_add
+`undef c_sub
+`undef c_add_sub
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef allUKs
+
+
+
+
+
+
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V4_0.v

@@ -0,0 +1,656 @@
+/* $Id: C_ADDSUB_V4_0.v,v 1.12 2008/09/08 20:05:45 akennedy Exp $
+--
+-- Filename - C_ADDSUB_V4_0.v
+-- Author - Xilinx
+-- Creation - 22 Mar 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_ADDSUB_V4_0 module
+*/
+
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_add 0
+`define c_sub 1
+`define c_add_sub 2
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}}
+
+module C_ADDSUB_V4_0 (A, B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT,
+					  SCLR, SSET, SINIT, A_SIGNED, B_SIGNED, OVFL, C_OUT, B_OUT,
+					  Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q);
+
+	parameter C_ADD_MODE 		= `c_add;
+	parameter C_AINIT_VAL 		= "";
+	parameter C_A_TYPE 			= `c_unsigned;
+	parameter C_A_WIDTH 		= 16;
+	parameter C_BYPASS_ENABLE 	= `c_override;
+	parameter C_BYPASS_LOW 		= 0;
+	parameter C_B_CONSTANT 		= 0;
+	parameter C_B_TYPE 			= `c_unsigned;
+	parameter C_B_VALUE 		= "";
+	parameter C_B_WIDTH 		= 16;
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_ADD 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_A_SIGNED 	= 0;
+	parameter C_HAS_BYPASS 		= 0;
+	parameter C_HAS_B_IN 		= 1;
+	parameter C_HAS_B_OUT 		= 0;
+	parameter C_HAS_B_SIGNED 	= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_C_IN 		= 1;
+	parameter C_HAS_C_OUT 		= 0;
+	parameter C_HAS_OVFL 		= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_Q_B_OUT 	= 0;
+	parameter C_HAS_Q_C_OUT 	= 0;
+	parameter C_HAS_Q_OVFL 		= 0;
+	parameter C_HAS_S 			= 0; 
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HIGH_BIT 		= 15;
+	parameter C_LATENCY	       	= 1;
+	parameter C_LOW_BIT 		= 0;
+	parameter C_OUT_WIDTH 		= 16;
+	parameter C_PIPE_STAGES 	= 1;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+	
+	// internal parameters (not to be set from instanciation)
+	parameter tmpWidth = (C_A_WIDTH > C_B_WIDTH) ? C_A_WIDTH + 2 : C_B_WIDTH + 2;
+	parameter output_reg_width = C_HIGH_BIT-C_LOW_BIT+1;
+
+	input [C_A_WIDTH-1 : 0] A;
+	input [C_B_WIDTH-1 : 0] B;
+	input CLK;
+	input ADD;
+	input C_IN;
+	input B_IN;
+	input CE;
+	input BYPASS;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input A_SIGNED;
+	input B_SIGNED;
+	output OVFL;
+	output C_OUT;
+	output B_OUT;
+	output Q_OVFL;
+	output Q_C_OUT;
+	output Q_B_OUT;
+	output [C_HIGH_BIT : C_LOW_BIT] S;
+	output [C_HIGH_BIT : C_LOW_BIT] Q;
+	
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_B_WIDTH-1 : 0] intBconst;
+	wire [C_B_WIDTH-1 : 0] intB;
+	wire intADD;
+	wire intBYPASS;
+	wire intC_IN;
+	wire intB_IN;
+	wire intCE;
+	wire intQCE;
+	wire intA_SIGNED;
+	wire intB_SIGNED;
+	reg intC_OUT;
+	reg intB_OUT;
+	reg intOVFL;
+	wire intQ_C_OUT;
+	wire intQ_B_OUT;
+	wire intQ_OVFL;
+	reg [C_HIGH_BIT : C_LOW_BIT ] intS;
+	wire [C_HIGH_BIT : C_LOW_BIT ] intQ;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	wire intACLR_INIT;
+	wire intSCLR_INIT;
+	reg lastCLK;
+	reg lastADD;
+	
+	reg [C_HIGH_BIT : C_LOW_BIT] intQpipe [C_LATENCY+2 : 0]; 
+	reg [C_LATENCY+2 : 0] intQ_C_OUTpipe; 
+	reg [C_LATENCY+2 : 0] intQ_B_OUTpipe; 
+	reg [C_LATENCY : 0] intQ_OVFLpipe; 
+
+	reg [C_HIGH_BIT : C_LOW_BIT] intQpipeend;
+	reg intQ_C_OUTpipeend;
+	reg intQ_B_OUTpipeend;
+	reg intQ_OVFLpipeend;
+	reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe1;
+	reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe2;
+	
+	 
+	wire [C_HIGH_BIT : C_LOW_BIT] Q = (C_HAS_Q == 1 ? intQ : `allUKs);
+	wire Q_C_OUT = (C_HAS_Q_C_OUT == 1 ? intQ_C_OUT : 1'bx);
+	wire Q_B_OUT = (C_HAS_Q_B_OUT == 1 ? intQ_B_OUT : 1'bx);
+	wire Q_OVFL = (C_HAS_Q_OVFL == 1 ? intQ_OVFL : 1'bx);
+	wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs);
+	wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx);
+	wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx);
+	wire OVFL = (C_HAS_OVFL == 1 ? intOVFL : 1'bx);
+	
+	// Sort out default values for missing ports
+	
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intACLR_INIT = (intACLR || intAINIT);
+	assign intSCLR_INIT = (intSCLR || intSINIT);
+	
+	assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B;
+	assign intADD = (C_HAS_ADD === 1) ? ADD : ((C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3)); // 3 is an illegal value since this is an illegal option!	
+	assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0;
+	assign intC_IN = ((C_HAS_C_IN === 1) ? C_IN : ((C_HAS_ADD === 1) ? ~intADD : 0));
+	assign intB_IN = defval(B_IN, C_HAS_B_IN, 1);
+	assign intA_SIGNED = defval(A_SIGNED, C_HAS_A_SIGNED, 0);
+	//assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0);
+	assign intB_SIGNED = ((C_HAS_B_SIGNED === 0) ? 0 : (((C_HAS_B_SIGNED === 1) && ~((C_B_CONSTANT === 1) && (C_HAS_BYPASS === 0) && (C_B_VALUE[((C_B_WIDTH*8)-1):((C_B_WIDTH-1)*8)] === "0")) ? B_SIGNED : 0))) ;
+	assign intB = (intBYPASS === 0 ? intBconst : B);
+	assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1);
+	
+	integer j, k;
+	integer pipe, pipe1;
+	integer i;
+	
+	reg [tmpWidth-1 : 0] tmpA;
+	reg [tmpWidth-1 : 0] tmpB;
+	reg [tmpWidth-1 : 0] tmpC;
+	reg [tmpWidth-1 : 0] tmpBC;
+	reg [tmpWidth-1 : 0] tmpABC;
+	reg [tmpWidth-2 : 0] tmpD;
+	reg [tmpWidth-2 : 0] tmpE;
+	reg [tmpWidth-2 : 0] tmpF;
+	
+	// Registers on outputs by default
+	C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, output_reg_width)
+		regq (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regcout (.D(intQ_C_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_C_OUT)); 
+
+	C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regbout (.D(intQ_B_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_B_OUT)); 
+
+	C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regovfl (.D(intQ_OVFLpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_OVFL)); 
+	
+	initial
+	begin
+	 	#1;
+		for(i = 0; i <= C_LATENCY+2; i = i + 1)
+		begin
+			intQpipe[i] = 'bx;
+			intQ_C_OUTpipe[i] = 1'bx;
+			intQ_B_OUTpipe[i] = 1'bx;
+			intQ_OVFLpipe[i] = 1'bx;
+		end
+		intQpipeend = `allUKs;
+		intQ_C_OUTpipeend = 0;
+		intQ_B_OUTpipeend = 0;
+		intQ_OVFLpipeend = 0;
+		intS = `allUKs;
+		intC_OUT = 0;
+		intB_OUT = 0;
+		intOVFL = 0;
+	end
+	
+	always@(A or intB or intADD or intBYPASS or intC_IN or intB_IN or intA_SIGNED or intB_SIGNED)
+	begin
+		tmpC = 0;
+		if(intC_IN !== 1'b0)
+		begin
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpC = intC_IN;
+			end
+		end
+		else if(intC_IN !== 1'b1 && C_ADD_MODE == `c_add_sub && intADD === 1'b0)
+		begin
+			tmpC[0] = ~intC_IN;
+		end
+		else if(intB_IN !== 1'b1 && C_ADD_MODE == `c_sub)
+		begin
+			tmpC[0] = ~intB_IN;
+		end
+		
+		if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED === 1))
+		begin
+			for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1)
+			begin
+				tmpA[j] = A[C_A_WIDTH-1];
+			end
+		end
+		else if(C_A_TYPE == `c_unsigned || (C_A_TYPE == `c_pin && intA_SIGNED === 0))
+		begin
+			for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1)
+			begin
+				tmpA[j] = 0;
+			end
+		end
+		
+		tmpA[C_A_WIDTH-1 : 0] = A;
+		
+		if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1))
+		begin
+			for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1)
+			begin
+				tmpB[j] = intB[C_B_WIDTH-1];
+			end
+		end
+		else if(C_B_TYPE == `c_unsigned || (C_B_TYPE == `c_pin && intB_SIGNED === 0))
+		begin
+			for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1)
+			begin
+				tmpB[j] = 0;
+			end
+		end
+		
+		tmpB[C_B_WIDTH-1 : 0] = intB;
+		
+		if(intBYPASS == 1)
+		begin
+			intS <= #1 tmpB[C_HIGH_BIT : C_LOW_BIT];
+			if (is_X(tmpB) && C_LATENCY >1)
+			begin
+				intC_OUT <= #1 1'bx;
+				intB_OUT <= #1 1'bx;
+				intOVFL <= #1 1'bx;
+			end
+			else
+			begin
+				intC_OUT <= #1 1'b0;
+				intB_OUT <= #1 1'b0;
+				intOVFL <= #1 1'b0;
+			end
+		end
+		else if(is_X(tmpA) || is_X(tmpB) || is_X(tmpC) || intBYPASS === 1'bx || intADD === 1'bx)
+		begin
+			intS <= #1 {C_HIGH_BIT-C_LOW_BIT+1{1'bx}};
+			intC_OUT <= #1 1'bx;
+			intB_OUT <= #1 1'bx;
+			intOVFL <= #1 1'bx;
+		end
+		else
+		begin
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpBC = add(tmpB, tmpC);
+			end
+			else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+			begin
+				tmpBC = add(tmpB, tmpC);
+			end
+			
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpABC = add(tmpA, tmpBC);
+			end
+			else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+			begin
+				tmpABC = sub(tmpA, tmpBC);
+			end
+			
+			intS <= #1 tmpABC[C_HIGH_BIT : C_LOW_BIT];
+			
+			if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1)
+			begin
+				if((C_ADD_MODE == `c_add_sub && intADD === 1'b1) || C_ADD_MODE == `c_add)
+					intC_OUT <= #1 tmpABC[tmpWidth-2];
+				else if(C_ADD_MODE == `c_add_sub && intADD === 1'b0)
+					intC_OUT <= #1 ~tmpABC[tmpWidth-2];
+			end
+			
+			if(C_HAS_B_OUT == 1 || C_HAS_Q_B_OUT == 1)
+			begin
+				intB_OUT <= #1 !tmpABC[tmpWidth-2];
+			end
+			
+			if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+			begin
+				tmpD[tmpWidth-3 : 0] = tmpA[tmpWidth-3 : 0];
+				if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED == 1)) 
+					tmpD[tmpWidth-2] = tmpA[tmpWidth-1];
+				else
+					tmpD[tmpWidth-2] = 1'b0;
+				tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0];
+				if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED == 1)) 
+					tmpE[tmpWidth-2] = tmpBC[tmpWidth-1];
+				else
+					tmpE[tmpWidth-2] = 1'b0;
+				if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+				begin
+					tmpF = sm_add(tmpD, tmpE);
+				end
+				else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+				begin
+					tmpF = sm_sub(tmpD, tmpE);
+				end
+				
+				intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpABC[tmpWidth-2];
+			end
+		end			
+	end
+	
+	always@(posedge CLK)
+		lastADD <= intADD;
+	
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+		begin
+			if (lastADD === intADD) // is pipeline data valid?
+			begin
+				for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+				begin
+					intQpipe[pipe] <= intQpipe[pipe+1];
+					intQ_C_OUTpipe[pipe] <= intQ_C_OUTpipe[pipe+1];
+					intQ_B_OUTpipe[pipe] <= intQ_B_OUTpipe[pipe+1];
+					intQ_OVFLpipe[pipe] <= intQ_OVFLpipe[pipe+1];
+				end
+			end
+			else
+			begin
+				for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+				begin
+					intQpipe[pipe] <= 'bx;
+					intQ_C_OUTpipe[pipe] <= 1'bx;
+					intQ_B_OUTpipe[pipe] <= 1'bx;
+					intQ_OVFLpipe[pipe] <= 1'bx;
+				end
+			end
+			intQpipe[C_LATENCY] <= intS;
+			intQ_C_OUTpipe[C_LATENCY] <= intC_OUT;
+			intQ_B_OUTpipe[C_LATENCY] <= intB_OUT;
+			intQ_OVFLpipe[C_LATENCY] <= intOVFL;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+			begin
+				if(intQ_C_OUTpipe[pipe] !== intQ_C_OUTpipe[pipe+1])
+					intQ_C_OUTpipe[pipe] <= 1'bx;
+				if(intQ_B_OUTpipe[pipe] !== intQ_B_OUTpipe[pipe+1])
+					intQ_B_OUTpipe[pipe] <= 1'bx;
+				if(intQ_OVFLpipe[pipe] !== intQ_OVFLpipe[pipe+1])
+					intQ_OVFLpipe[pipe] <= 1'bx;
+				tmp_pipe1 = intQpipe[pipe];
+				tmp_pipe2 = intQpipe[pipe+1];
+				for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				intQpipe[pipe] <= tmp_pipe1;
+			end
+			if(intQ_C_OUTpipe[C_LATENCY] !== intC_OUT)
+				intQ_C_OUTpipe[C_LATENCY] <= 1'bx;
+			if(intQ_B_OUTpipe[C_LATENCY] !== intB_OUT)
+				intQ_B_OUTpipe[C_LATENCY] <= 1'bx;
+			if(intQ_OVFLpipe[C_LATENCY] !== intOVFL)
+				intQ_OVFLpipe[C_LATENCY] <= 1'bx;
+			for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== intS[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			intQpipe[C_LATENCY] <= tmp_pipe1;
+		end
+	end
+	
+	always@(intS or intQpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQpipeend <= intS;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQpipeend <= intQpipe[2];
+		else
+			// pipeline data invalid
+			intQpipeend <= 'bx;
+	end
+	
+	always@(intC_OUT or intQ_C_OUTpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_C_OUTpipeend <= intC_OUT;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQ_C_OUTpipeend <= intQ_C_OUTpipe[2];
+		else
+			// Pipeline data invalid
+			intQ_C_OUTpipeend <= 1'bx;
+	end
+	
+	always@(intB_OUT or intQ_B_OUTpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_B_OUTpipeend <= intB_OUT;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQ_B_OUTpipeend <= intQ_B_OUTpipe[2];
+		else
+			intQ_B_OUTpipeend <= 1'bx;
+	end
+	
+	always@(intOVFL or intQ_OVFLpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_OVFLpipeend <= intOVFL;
+		else if (lastADD === intADD)
+			// Pipeline stages required 
+			intQ_OVFLpipeend <= intQ_OVFLpipe[2];
+		else
+			intQ_OVFLpipeend <= 1'bx;
+	end
+
+	always@(CLK)
+		lastCLK <= CLK;
+	
+/* helper functions */
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+		
+	function [C_B_WIDTH - 1 : 0] to_bitsB;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_B_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+				to_bitsB[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bitsB[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bitsB[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bitsB[i-1] = 0;
+				else
+				begin
+					$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+	function max;
+	input a;
+	input b;
+	begin
+		max = (a > b) ? a : b;
+	end
+	endfunction
+	
+	function is_X;
+	input [tmpWidth-1 : 0] i;
+	begin
+		is_X = 1'b0;
+		for(j = 0; j < tmpWidth; j = j + 1)
+		begin
+			if(i[j] === 1'bx) 
+				is_X = 1'b1;
+		end // loop
+	end
+	endfunction
+	
+	function [tmpWidth-1 : 0] add;
+	input [tmpWidth-1 : 0] i1;
+	input [tmpWidth-1 : 0] i2;
+	integer bit_index;
+	integer carryin, carryout;
+	begin
+		carryin = 0;
+		carryout = 0;
+		for(bit_index=0; bit_index < tmpWidth; bit_index = bit_index + 1)
+		begin
+			add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin;
+			carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index]));
+			carryin = carryout;
+		end
+	end
+	endfunction
+	
+	function [tmpWidth-1 : 0] sub;
+	input [tmpWidth-1 : 0] i1;
+	input [tmpWidth-1 : 0] i2;
+	begin
+		i2 = add(~i2, 1);
+		sub = add(i1, i2);
+	end
+	endfunction
+	
+	function [tmpWidth-2 : 0] sm_add;
+	input [tmpWidth-2 : 0] i1;
+	input [tmpWidth-2 : 0] i2;
+	integer bit_index;
+	integer carryin, carryout;
+	begin
+		carryin = 0;
+		carryout = 0;
+		for(bit_index=0; bit_index < tmpWidth-1; bit_index = bit_index + 1)
+		begin
+			sm_add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin;
+			carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index]));
+			carryin = carryout;
+		end
+	end
+	endfunction
+	
+	function [tmpWidth-2 : 0] sm_sub;
+	input [tmpWidth-2 : 0] i1;
+	input [tmpWidth-2 : 0] i2;
+	begin
+		i2 = sm_add(~i2, 1);
+		sm_sub = sm_add(i1, i2);
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_add
+`undef c_sub
+`undef c_add_sub
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef allUKs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V5_0.v

@@ -0,0 +1,684 @@
+/* $Id: C_ADDSUB_V5_0.v,v 1.17 2008/09/08 20:05:55 akennedy Exp $
+--
+-- Filename - C_ADDSUB_V5_0.v
+-- Author - Xilinx
+-- Creation - 22 Mar 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_ADDSUB_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_add 0
+`define c_sub 1
+`define c_add_sub 2
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}}
+
+module C_ADDSUB_V5_0 (A, B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT,
+					  SCLR, SSET, SINIT, A_SIGNED, B_SIGNED, OVFL, C_OUT, B_OUT,
+					  Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q);
+
+	parameter C_ADD_MODE 		= `c_add;
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_A_TYPE 			= `c_unsigned;
+	parameter C_A_WIDTH 		= 16;
+	parameter C_BYPASS_ENABLE 	= `c_override;
+	parameter C_BYPASS_LOW 		= 0;
+	parameter C_B_CONSTANT 		= 0;
+	parameter C_B_TYPE 			= `c_unsigned;
+	parameter C_B_VALUE 		= "0000000000000000";
+	parameter C_B_WIDTH 		= 16;
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_ADD 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_A_SIGNED 	= 0;
+	parameter C_HAS_BYPASS 		= 0;
+	parameter C_HAS_BYPASS_WITH_CIN = 0;
+    parameter C_HAS_B_IN 		= 1;
+	parameter C_HAS_B_OUT 		= 0;
+	parameter C_HAS_B_SIGNED 	= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_C_IN 		= 1;
+	parameter C_HAS_C_OUT 		= 0;
+	parameter C_HAS_OVFL 		= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_Q_B_OUT 	= 0;
+	parameter C_HAS_Q_C_OUT 	= 0;
+	parameter C_HAS_Q_OVFL 		= 0;
+	parameter C_HAS_S 			= 0; 
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HIGH_BIT 		= 15;
+	parameter C_LATENCY	       	= 1;
+	parameter C_LOW_BIT 		= 0;
+	parameter C_OUT_WIDTH 		= 16;
+	parameter C_PIPE_STAGES 	= 1;
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+	
+	
+	// internal parameters (not to be set from instanciation)
+	parameter tmpWidth = (C_A_WIDTH > C_B_WIDTH) ? C_A_WIDTH + 2 : C_B_WIDTH + 2;
+	parameter output_reg_width = C_HIGH_BIT-C_LOW_BIT+1;
+
+	input [C_A_WIDTH-1 : 0] A;
+	input [C_B_WIDTH-1 : 0] B;
+	input CLK;
+	input ADD;
+	input C_IN;
+	input B_IN;
+	input CE;
+	input BYPASS;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input A_SIGNED;
+	input B_SIGNED;
+	output OVFL;
+	output C_OUT;
+	output B_OUT;
+	output Q_OVFL;
+	output Q_C_OUT;
+	output Q_B_OUT;
+	output [C_HIGH_BIT : C_LOW_BIT] S;
+	output [C_HIGH_BIT : C_LOW_BIT] Q;
+    
+	
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_B_WIDTH-1 : 0] intBconst;
+	wire [C_B_WIDTH-1 : 0] intB;
+	wire intADD;
+	wire intBYPASS;
+	wire intC_IN;
+	wire intB_IN;
+	wire intCE;
+	wire intQCE;
+	wire intA_SIGNED;
+	wire intB_SIGNED;
+	reg intC_OUT;
+	reg intB_OUT;
+	reg intOVFL;
+	wire intQ_C_OUT;
+	wire intQ_B_OUT;
+	wire intQ_OVFL;
+	reg [C_HIGH_BIT : C_LOW_BIT ] intS;
+	wire [C_HIGH_BIT : C_LOW_BIT ] intQ;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	wire intACLR_INIT;
+	wire intSCLR_INIT;
+	wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode
+	reg lastCLK;
+	reg lastADD;
+	
+	reg [C_HIGH_BIT : C_LOW_BIT] intQpipe [C_LATENCY+2 : 0]; 
+	reg [C_LATENCY+2 : 0] intQ_C_OUTpipe; 
+	reg [C_LATENCY+2 : 0] intQ_B_OUTpipe; 
+	reg [C_LATENCY+2 : 0] intQ_OVFLpipe; 
+
+	reg [C_HIGH_BIT : C_LOW_BIT] intQpipeend;
+	reg intQ_C_OUTpipeend;
+	reg intQ_B_OUTpipeend;
+	reg intQ_OVFLpipeend;
+	reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe1;
+	reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe2;
+	
+	 
+	wire [C_HIGH_BIT : C_LOW_BIT] Q = (C_HAS_Q == 1 ? intQ : `allUKs);
+	wire Q_C_OUT = (C_HAS_Q_C_OUT == 1 ? intQ_C_OUT : 1'bx);
+	wire Q_B_OUT = (C_HAS_Q_B_OUT == 1 ? intQ_B_OUT : 1'bx);
+	wire Q_OVFL = (C_HAS_Q_OVFL == 1 ? intQ_OVFL : 1'bx);
+	wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs);
+	wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx);
+	wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx);
+	wire OVFL = (C_HAS_OVFL == 1 ? intOVFL : 1'bx);
+	
+	// Sort out default values for missing ports
+	
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intACLR_INIT = (intACLR || intAINIT);
+	assign intSCLR_INIT = (intSCLR || intSINIT);
+	
+	assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B;
+	assign intADD = (C_HAS_ADD === 1) ? ADD : ((C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3)); // 3 is an illegal value since this is an illegal option!	
+	assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0;
+	assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; // new parameter to allow the bypass mode to take account of the c_in
+	assign intC_IN = ((C_HAS_C_IN === 1) ? C_IN : ((C_HAS_ADD === 1) ? ~intADD : 0));
+	assign intB_IN = defval(B_IN, C_HAS_B_IN, 1);
+	assign intA_SIGNED = defval(A_SIGNED, C_HAS_A_SIGNED, 0);
+	//assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0);
+	assign intB_SIGNED = ((C_HAS_B_SIGNED === 0) ? 0 : (((C_HAS_B_SIGNED === 1) && ~((C_B_CONSTANT === 1) && (C_HAS_BYPASS === 0) && (C_B_VALUE[((C_B_WIDTH*8)-1):((C_B_WIDTH-1)*8)] === "0")) ? B_SIGNED : 0))) ;
+	assign intB = (intBYPASS === 0 ? intBconst : B);
+	assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1);
+	
+	integer j, k;
+	integer pipe, pipe1;
+	integer i;
+	
+	reg [tmpWidth-1 : 0] tmpA;
+	reg [tmpWidth-1 : 0] tmpB;
+	reg [tmpWidth-1 : 0] tmpC;
+	reg [tmpWidth-1 : 0] tmpBC;
+	reg [tmpWidth-1 : 0] tmpABC;
+	reg [tmpWidth-2 : 0] tmpD;
+	reg [tmpWidth-2 : 0] tmpE;
+	reg [tmpWidth-2 : 0] tmpF;
+	
+	// Registers on outputs by default
+	C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, output_reg_width)
+		regq (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	C_REG_FD_V5_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regcout (.D(intQ_C_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_C_OUT)); 
+
+	C_REG_FD_V5_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regbout (.D(intQ_B_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_B_OUT)); 
+
+	C_REG_FD_V5_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regovfl (.D(intQ_OVFLpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_OVFL)); 
+	
+	initial
+	begin
+	 	#1;
+		for(i = 0; i <= C_LATENCY+2; i = i + 1)
+		begin
+			intQpipe[i] = 'bx;
+			intQ_C_OUTpipe[i] = 1'bx;
+			intQ_B_OUTpipe[i] = 1'bx;
+			intQ_OVFLpipe[i] = 1'bx;
+		end
+		intQpipeend = `allUKs;
+		intQ_C_OUTpipeend = 0;
+		intQ_B_OUTpipeend = 0;
+		intQ_OVFLpipeend = 0;
+		intS = `allUKs;
+		intC_OUT = 0;
+		intB_OUT = 0;
+		intOVFL = 0;
+	end
+	
+	always@(A or intB or intADD or intBYPASS or intC_IN or intB_IN or intA_SIGNED or intB_SIGNED)
+	begin
+		tmpC = 0;
+		if(intC_IN !== 1'b0)
+		begin
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpC = intC_IN;
+			end
+		end
+		else if(intC_IN !== 1'b1 && C_ADD_MODE == `c_add_sub && intADD === 1'b0)
+		begin
+			tmpC[0] = ~intC_IN;
+		end
+		else if(intB_IN !== 1'b1 && C_ADD_MODE == `c_sub)
+		begin
+			tmpC[0] = ~intB_IN;
+		end
+		
+		if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED === 1))
+		begin
+			for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1)
+			begin
+				tmpA[j] = A[C_A_WIDTH-1];
+			end
+		end
+		else if(C_A_TYPE == `c_unsigned || (C_A_TYPE == `c_pin && intA_SIGNED === 0))
+		begin
+			for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1)
+			begin
+				tmpA[j] = 0;
+			end
+		end
+		
+		tmpA[C_A_WIDTH-1 : 0] = A;
+		
+		if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1))
+		begin
+			for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1)
+			begin
+				tmpB[j] = intB[C_B_WIDTH-1];
+			end
+		end
+		else if(C_B_TYPE == `c_unsigned || (C_B_TYPE == `c_pin && intB_SIGNED === 0))
+		begin
+			for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1)
+			begin
+				tmpB[j] = 0;
+			end
+		end
+		
+		tmpB[C_B_WIDTH-1 : 0] = intB;
+		
+		if(intBYPASS == 1 && intBYPASS_WITH_CIN == 0)
+		begin
+			intS <= #1 tmpB[C_HIGH_BIT : C_LOW_BIT];
+			if (is_X(tmpB) && C_LATENCY >1)
+			begin
+				intC_OUT <= #1 1'bx;
+				intB_OUT <= #1 1'bx;
+				intOVFL <= #1 1'bx;
+			end
+			else
+			begin
+				intC_OUT <= #1 1'b0;
+				intB_OUT <= #1 1'b0;
+				intOVFL <= #1 1'b0;
+			end
+		end
+		else if(is_X(tmpA) || is_X(tmpB) || is_X(tmpC) || intBYPASS === 1'bx || intADD === 1'bx)
+		begin
+			intS <= #1 {C_HIGH_BIT-C_LOW_BIT+1{1'bx}};
+			intC_OUT <= #1 1'bx;
+			intB_OUT <= #1 1'bx;
+			intOVFL <= #1 1'bx;
+		end
+		else if (intBYPASS == 1 && intBYPASS_WITH_CIN == 1) // new section to model the behaviour of the new
+		begin                                               // c_has_bypass_with_cin mode. This mode is only available 
+			tmpBC = add(tmpB, tmpC);                        // for Adder variations.
+			
+			intS <= #1 tmpBC[C_HIGH_BIT : C_LOW_BIT];
+			
+			if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1)
+			begin
+				intC_OUT <= #1 tmpBC[tmpWidth-2];
+			end
+						
+			if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+			begin
+								
+			if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+			begin
+				tmpD[tmpWidth-2 : 0] =  {tmpWidth - 1{1'b0}};
+				tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0];
+				tmpE[tmpWidth-2] = tmpBC[tmpWidth-1];
+                tmpF = sm_add(tmpD, tmpE);				
+				intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpBC[tmpWidth-2];
+			end
+			end
+		end
+        else
+		begin
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpBC = add(tmpB, tmpC);
+			end
+			else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+			begin
+				tmpBC = add(tmpB, tmpC);
+			end
+			
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpABC = add(tmpA, tmpBC);
+			end
+			else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+			begin
+				tmpABC = sub(tmpA, tmpBC);
+			end
+			
+			intS <= #1 tmpABC[C_HIGH_BIT : C_LOW_BIT];
+			
+			if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1)
+			begin
+				if((C_ADD_MODE == `c_add_sub && intADD === 1'b1) || C_ADD_MODE == `c_add)
+					intC_OUT <= #1 tmpABC[tmpWidth-2];
+				else if(C_ADD_MODE == `c_add_sub && intADD === 1'b0)
+					intC_OUT <= #1 ~tmpABC[tmpWidth-2];
+			end
+			
+			if(C_HAS_B_OUT == 1 || C_HAS_Q_B_OUT == 1)
+			begin
+				intB_OUT <= #1 !tmpABC[tmpWidth-2];
+			end
+			
+			if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+			begin
+				tmpD[tmpWidth-3 : 0] = tmpA[tmpWidth-3 : 0];
+				if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED == 1)) 
+					tmpD[tmpWidth-2] = tmpA[tmpWidth-1];
+				else
+					tmpD[tmpWidth-2] = 1'b0;
+				tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0];
+				if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED == 1)) 
+					tmpE[tmpWidth-2] = tmpBC[tmpWidth-1];
+				else
+					tmpE[tmpWidth-2] = 1'b0;
+				if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+				begin
+					tmpF = sm_add(tmpD, tmpE);
+				end
+				else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+				begin
+					tmpF = sm_sub(tmpD, tmpE);
+				end
+				
+				intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpABC[tmpWidth-2];
+			end
+		end						
+	end
+	
+	always@(posedge CLK)
+		lastADD <= intADD;
+	
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+		begin
+			if (lastADD === intADD) // is pipeline data valid?
+			begin
+				for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+				begin
+					intQpipe[pipe] <= intQpipe[pipe+1];
+					intQ_C_OUTpipe[pipe] <= intQ_C_OUTpipe[pipe+1];
+					intQ_B_OUTpipe[pipe] <= intQ_B_OUTpipe[pipe+1];
+					intQ_OVFLpipe[pipe] <= intQ_OVFLpipe[pipe+1];
+				end
+			end
+			else
+			begin
+				for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+				begin
+					intQpipe[pipe] <= 'bx;
+					intQ_C_OUTpipe[pipe] <= 1'bx;
+					intQ_B_OUTpipe[pipe] <= 1'bx;
+					intQ_OVFLpipe[pipe] <= 1'bx;
+				end
+			end
+			intQpipe[C_LATENCY] <= intS;
+			intQ_C_OUTpipe[C_LATENCY] <= intC_OUT;
+			intQ_B_OUTpipe[C_LATENCY] <= intB_OUT;
+			intQ_OVFLpipe[C_LATENCY] <= intOVFL;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+			begin
+				if(intQ_C_OUTpipe[pipe] !== intQ_C_OUTpipe[pipe+1])
+					intQ_C_OUTpipe[pipe] <= 1'bx;
+				if(intQ_B_OUTpipe[pipe] !== intQ_B_OUTpipe[pipe+1])
+					intQ_B_OUTpipe[pipe] <= 1'bx;
+				if(intQ_OVFLpipe[pipe] !== intQ_OVFLpipe[pipe+1])
+					intQ_OVFLpipe[pipe] <= 1'bx;
+				tmp_pipe1 = intQpipe[pipe];
+				tmp_pipe2 = intQpipe[pipe+1];
+				for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				intQpipe[pipe] <= tmp_pipe1;
+			end
+			if(intQ_C_OUTpipe[C_LATENCY] !== intC_OUT)
+				intQ_C_OUTpipe[C_LATENCY] <= 1'bx;
+			if(intQ_B_OUTpipe[C_LATENCY] !== intB_OUT)
+				intQ_B_OUTpipe[C_LATENCY] <= 1'bx;
+			if(intQ_OVFLpipe[C_LATENCY] !== intOVFL)
+				intQ_OVFLpipe[C_LATENCY] <= 1'bx;
+			for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== intS[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			intQpipe[C_LATENCY] <= tmp_pipe1;
+		end
+	end
+	
+	always@(intS or intQpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQpipeend <= intS;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQpipeend <= intQpipe[2];
+		else
+			// pipeline data invalid
+			intQpipeend <= 'bx;
+	end
+	
+	always@(intC_OUT or intQ_C_OUTpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_C_OUTpipeend <= intC_OUT;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQ_C_OUTpipeend <= intQ_C_OUTpipe[2];
+		else
+			// Pipeline data invalid
+			intQ_C_OUTpipeend <= 1'bx;
+	end
+	
+	always@(intB_OUT or intQ_B_OUTpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_B_OUTpipeend <= intB_OUT;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQ_B_OUTpipeend <= intQ_B_OUTpipe[2];
+		else
+			intQ_B_OUTpipeend <= 1'bx;
+	end
+	
+	always@(intOVFL or intQ_OVFLpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_OVFLpipeend <= intOVFL;
+		else if (lastADD === intADD)
+			// Pipeline stages required 
+			intQ_OVFLpipeend <= intQ_OVFLpipe[2];
+		else
+			intQ_OVFLpipeend <= 1'bx;
+	end
+
+	always@(CLK)
+		lastCLK <= CLK;
+	
+/* helper functions */
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+		
+	function [C_B_WIDTH - 1 : 0] to_bitsB;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_B_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+				to_bitsB[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bitsB[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bitsB[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bitsB[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+	function max;
+	input a;
+	input b;
+	begin
+		max = (a > b) ? a : b;
+	end
+	endfunction
+	
+	function is_X;
+	input [tmpWidth-1 : 0] i;
+	begin
+		is_X = 1'b0;
+		for(j = 0; j < tmpWidth; j = j + 1)
+		begin
+			if(i[j] === 1'bx) 
+				is_X = 1'b1;
+		end // loop
+	end
+	endfunction
+	
+	function [tmpWidth-1 : 0] add;
+	input [tmpWidth-1 : 0] i1;
+	input [tmpWidth-1 : 0] i2;
+	integer bit_index;
+	integer carryin, carryout;
+	begin
+		carryin = 0;
+		carryout = 0;
+		for(bit_index=0; bit_index < tmpWidth; bit_index = bit_index + 1)
+		begin
+			add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin;
+			carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index]));
+			carryin = carryout;
+		end
+	end
+	endfunction
+	
+	function [tmpWidth-1 : 0] sub;
+	input [tmpWidth-1 : 0] i1;
+	input [tmpWidth-1 : 0] i2;
+	begin
+		i2 = add(~i2, 1);
+		sub = add(i1, i2);
+	end
+	endfunction
+	
+	function [tmpWidth-2 : 0] sm_add;
+	input [tmpWidth-2 : 0] i1;
+	input [tmpWidth-2 : 0] i2;
+	integer bit_index;
+	integer carryin, carryout;
+	begin
+		carryin = 0;
+		carryout = 0;
+		for(bit_index=0; bit_index < tmpWidth-1; bit_index = bit_index + 1)
+		begin
+			sm_add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin;
+			carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index]));
+			carryin = carryout;
+		end
+	end
+	endfunction
+	
+	function [tmpWidth-2 : 0] sm_sub;
+	input [tmpWidth-2 : 0] i1;
+	input [tmpWidth-2 : 0] i2;
+	begin
+		i2 = sm_add(~i2, 1);
+		sm_sub = sm_add(i1, i2);
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_add
+`undef c_sub
+`undef c_add_sub
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef allUKs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V6_0.v

@@ -0,0 +1,742 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_ADDSUB_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_ADDSUB_V6_0.v
+-- Author - Xilinx
+-- Creation - 22 Mar 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_ADDSUB_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_add 0
+`define c_sub 1
+`define c_add_sub 2
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}}
+
+module C_ADDSUB_V6_0 (A, B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT,
+					  SCLR, SSET, SINIT, A_SIGNED, B_SIGNED, OVFL, C_OUT, B_OUT,
+					  Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q);
+
+	parameter C_ADD_MODE 		= `c_add;
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_A_TYPE 			= `c_unsigned;
+	parameter C_A_WIDTH 		= 16;
+	parameter C_BYPASS_ENABLE 	= `c_override;
+	parameter C_BYPASS_LOW 		= 0;
+	parameter C_B_CONSTANT 		= 0;
+	parameter C_B_TYPE 			= `c_unsigned;
+	parameter C_B_VALUE 		= "0000000000000000";
+	parameter C_B_WIDTH 		= 16;
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_ADD 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_A_SIGNED 	= 0;
+	parameter C_HAS_BYPASS 		= 0;
+	parameter C_HAS_BYPASS_WITH_CIN = 0;
+    parameter C_HAS_B_IN 		= 1;
+	parameter C_HAS_B_OUT 		= 0;
+	parameter C_HAS_B_SIGNED 	= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_C_IN 		= 1;
+	parameter C_HAS_C_OUT 		= 0;
+	parameter C_HAS_OVFL 		= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_Q_B_OUT 	= 0;
+	parameter C_HAS_Q_C_OUT 	= 0;
+	parameter C_HAS_Q_OVFL 		= 0;
+	parameter C_HAS_S 			= 0; 
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HIGH_BIT 		= 15;
+	parameter C_LATENCY	       	= 1;
+	parameter C_LOW_BIT 		= 0;
+	parameter C_OUT_WIDTH 		= 16;
+	parameter C_PIPE_STAGES 	= 1;
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+	
+	
+	// internal parameters (not to be set from instanciation)
+	parameter tmpWidth = (C_A_WIDTH > C_B_WIDTH) ? C_A_WIDTH + 2 : C_B_WIDTH + 2;
+	parameter output_reg_width = C_HIGH_BIT-C_LOW_BIT+1;
+
+	input [C_A_WIDTH-1 : 0] A;
+	input [C_B_WIDTH-1 : 0] B;
+	input CLK;
+	input ADD;
+	input C_IN;
+	input B_IN;
+	input CE;
+	input BYPASS;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input A_SIGNED;
+	input B_SIGNED;
+	output OVFL;
+	output C_OUT;
+	output B_OUT;
+	output Q_OVFL;
+	output Q_C_OUT;
+	output Q_B_OUT;
+	output [C_HIGH_BIT : C_LOW_BIT] S;
+	output [C_HIGH_BIT : C_LOW_BIT] Q;
+    
+	
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_B_WIDTH-1 : 0] intBconst;
+	wire [C_B_WIDTH-1 : 0] intB;
+	wire intADD;
+	wire intBYPASS;
+	wire intC_IN;
+	wire intB_IN;
+	wire intCE;
+	wire intQCE;
+	wire intA_SIGNED;
+	wire intB_SIGNED;
+	reg intC_OUT;
+	reg intB_OUT;
+	reg intOVFL;
+	wire intQ_C_OUT;
+	wire intQ_B_OUT;
+	wire intQ_OVFL;
+	reg [C_HIGH_BIT : C_LOW_BIT ] intS;
+	wire [C_HIGH_BIT : C_LOW_BIT ] intQ;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	wire intACLR_INIT;
+	wire intSCLR_INIT;
+	wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode
+	reg lastCLK;
+	reg lastADD;
+    wire [8 : 1] b_max;	
+	reg [C_HIGH_BIT : C_LOW_BIT] intQpipe [C_LATENCY+2 : 0]; 
+	reg [C_LATENCY+2 : 0] intQ_C_OUTpipe; 
+	reg [C_LATENCY+2 : 0] intQ_B_OUTpipe; 
+	reg [C_LATENCY+2 : 0] intQ_OVFLpipe; 
+	reg [C_LATENCY-1 : 0] intADDpipe;
+
+	reg [C_HIGH_BIT : C_LOW_BIT] intQpipeend;
+	reg intQ_C_OUTpipeend;
+	reg intQ_B_OUTpipeend;
+	reg intQ_OVFLpipeend;
+	reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe1;
+	reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe2;
+	
+	 
+	wire [C_HIGH_BIT : C_LOW_BIT] Q = (C_HAS_Q == 1 ? intQ : `allUKs);
+	wire Q_C_OUT = (C_HAS_Q_C_OUT == 1 ? intQ_C_OUT : 1'bx);
+	wire Q_B_OUT = (C_HAS_Q_B_OUT == 1 ? intQ_B_OUT : 1'bx);
+	wire Q_OVFL = (C_HAS_Q_OVFL == 1 ? intQ_OVFL : 1'bx);
+	wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs);
+	wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx);
+	wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx);
+	wire OVFL = (C_HAS_OVFL == 1 ? intOVFL : 1'bx);
+	
+	// Sort out default values for missing ports
+	
+	assign b_max = max_bval(C_B_VALUE);
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intACLR_INIT = (intACLR || intAINIT);
+	assign intSCLR_INIT = (intSCLR || intSINIT);
+	
+	assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B;
+//	assign intADD = (C_HAS_ADD === 1) ? ((C_LATENCY < 2) ? ADD : intADDpipe[C_LATENCY-1]) : ((C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3)); // 3 is an illegal value since this is an illegal option!	
+	assign intADD =  (C_HAS_ADD === 1) ? ADD :  (C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3); // 3 is an illegal value since this is an illegal option!	
+	assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0;
+	assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; // new parameter to allow the bypass mode to take account of the c_in
+	assign intC_IN = ((C_HAS_C_IN === 1) ? C_IN : ((C_HAS_ADD === 1) ? ~intADD : 0));
+	assign intB_IN = defval(B_IN, C_HAS_B_IN, 1);
+	assign intA_SIGNED = defval(A_SIGNED, C_HAS_A_SIGNED, 0);
+	//assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0);
+	assign intB_SIGNED = ((C_HAS_B_SIGNED === 0) ? 0 : (((C_HAS_B_SIGNED === 1) && ~((C_B_CONSTANT === 1) && (C_HAS_BYPASS === 0) && (b_max === 0)) ? B_SIGNED : 0))) ;
+	assign intB = (intBYPASS === 0 ? intBconst : B);
+	assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1);
+	
+	integer j, k;
+	integer pipe, pipe1;
+	integer i;
+	
+	reg [tmpWidth-1 : 0] tmpA;
+	reg [tmpWidth-1 : 0] tmpB;
+	reg [tmpWidth-1 : 0] tmpC;
+	reg [tmpWidth-1 : 0] tmpBC;
+	reg [tmpWidth-1 : 0] tmpABC;
+	reg [tmpWidth-2 : 0] tmpD;
+	reg [tmpWidth-2 : 0] tmpE;
+	reg [tmpWidth-2 : 0] tmpF;
+	
+	// Registers on outputs by default
+	C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, output_reg_width)
+		regq (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regcout (.D(intQ_C_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_C_OUT)); 
+
+	C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regbout (.D(intQ_B_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_B_OUT)); 
+
+	C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regovfl (.D(intQ_OVFLpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_OVFL)); 
+	
+	initial
+	begin
+	 	#1;
+		for(i = 0; i <= C_LATENCY+2; i = i + 1)
+		begin
+			intQpipe[i] = 'bx;
+			intQ_C_OUTpipe[i] = 1'bx;
+			intQ_B_OUTpipe[i] = 1'bx;
+			intQ_OVFLpipe[i] = 1'bx;
+		end
+		intQpipeend = `allUKs;
+		intQ_C_OUTpipeend = 1'bx;
+		intQ_B_OUTpipeend = 1'bx;
+		intQ_OVFLpipeend = 1'bx;
+		intS = `allUKs;
+		intC_OUT = 1'bx;
+		intB_OUT = 1'bx;
+		intOVFL = 1'bx;
+	end
+	
+	always@(A or intB or intADD or intBYPASS or intC_IN or intB_IN or intA_SIGNED or intB_SIGNED)
+	begin
+		tmpC = 0;
+		if(intC_IN !== 1'b0)
+		begin
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpC = intC_IN;
+			end
+		end
+		else if(intC_IN !== 1'b1 && C_ADD_MODE == `c_add_sub && intADD === 1'b0)
+		begin
+			tmpC[0] = ~intC_IN;
+		end
+		else if(intB_IN !== 1'b1 && C_ADD_MODE == `c_sub)
+		begin
+			tmpC[0] = ~intB_IN;
+		end
+		
+		if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED === 1))
+		begin
+			for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1)
+			begin
+				tmpA[j] = A[C_A_WIDTH-1];
+			end
+		end
+		else if(C_A_TYPE == `c_unsigned || (C_A_TYPE == `c_pin && intA_SIGNED === 0))
+		begin
+			for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1)
+			begin
+				tmpA[j] = 0;
+			end
+		end
+		
+		tmpA[C_A_WIDTH-1 : 0] = A;
+		
+		if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1))
+		begin
+			for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1)
+			begin
+				tmpB[j] = intB[C_B_WIDTH-1];
+			end
+		end
+		else if(C_B_TYPE == `c_unsigned || (C_B_TYPE == `c_pin && intB_SIGNED === 0))
+		begin
+			for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1)
+			begin
+				tmpB[j] = 0;
+			end
+		end
+		
+		tmpB[C_B_WIDTH-1 : 0] = intB;
+		
+		if(intBYPASS == 1 && intBYPASS_WITH_CIN == 0)
+		begin
+			intS <= #1 tmpB[C_HIGH_BIT : C_LOW_BIT];
+			if (is_X(tmpB))
+			begin
+				intC_OUT <= #1 1'bx;
+				intB_OUT <= #1 1'bx;
+				intOVFL <= #1 1'bx;
+			end
+			else
+			begin
+				intC_OUT <= #1 1'b0;
+				intB_OUT <= #1 1'b0;
+				intOVFL <= #1 1'b0;
+			end
+		end
+		else if(is_X(tmpA) || is_X(tmpB) || is_X(tmpC) || intBYPASS === 1'bx || intADD === 1'bx)
+		begin
+			intS <= #1 {C_HIGH_BIT-C_LOW_BIT+1{1'bx}};
+			intC_OUT <= #1 1'bx;
+			intB_OUT <= #1 1'bx;
+			intOVFL <= #1 1'bx;
+		end
+		else if (intBYPASS == 1 && intBYPASS_WITH_CIN == 1) // new section to model the behaviour of the new
+		begin                                               // c_has_bypass_with_cin mode. This mode is only available 
+			tmpBC = add(tmpB, tmpC);                        // for Adder variations.
+			
+			intS <= #1 tmpBC[C_HIGH_BIT : C_LOW_BIT];
+			
+			if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1)
+			begin
+				intC_OUT <= #1 tmpBC[tmpWidth-2];
+			end
+						
+			if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+			begin
+								
+			if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+			begin
+				tmpD[tmpWidth-2 : 0] =  {tmpWidth - 1{1'b0}};
+				tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0];
+				tmpE[tmpWidth-2] = tmpBC[tmpWidth-1];
+                tmpF = sm_add(tmpD, tmpE);				
+				intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpBC[tmpWidth-2];
+			end
+			end
+		end
+        else
+		begin
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpBC = add(tmpB, tmpC);
+			end
+			else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+			begin
+				tmpBC = add(tmpB, tmpC);
+			end
+			
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpABC = add(tmpA, tmpBC);
+			end
+			else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+			begin
+				tmpABC = sub(tmpA, tmpBC);
+			end
+			
+			intS <= #1 tmpABC[C_HIGH_BIT : C_LOW_BIT];
+			
+			if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1)
+			begin
+				if((C_ADD_MODE == `c_add_sub && intADD === 1'b1) || C_ADD_MODE == `c_add)
+					intC_OUT <= #1 tmpABC[tmpWidth-2];
+				else if(C_ADD_MODE == `c_add_sub && intADD === 1'b0)
+					intC_OUT <= #1 ~tmpABC[tmpWidth-2];
+			end
+			
+			if(C_HAS_B_OUT == 1 || C_HAS_Q_B_OUT == 1)
+			begin
+				intB_OUT <= #1 !tmpABC[tmpWidth-2];
+			end
+			
+			if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+			begin
+				tmpD[tmpWidth-3 : 0] = tmpA[tmpWidth-3 : 0];
+				if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED == 1)) 
+					tmpD[tmpWidth-2] = tmpA[tmpWidth-1];
+				else
+					tmpD[tmpWidth-2] = 1'b0;
+				tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0];
+				if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED == 1)) 
+					tmpE[tmpWidth-2] = tmpBC[tmpWidth-1];
+				else
+					tmpE[tmpWidth-2] = 1'b0;
+				if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+				begin
+					tmpF = sm_add(tmpD, tmpE);
+				end
+				else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+				begin
+					tmpF = sm_sub(tmpD, tmpE);
+				end
+				
+				intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpABC[tmpWidth-2];
+			end
+		end						
+	end
+	
+	always@(posedge CLK)
+		lastADD <= intADD;
+	
+	always@(posedge CLK )
+	begin
+        if ((intACLR === 1'b1 || intSCLR === 1'b1) && C_ADD_MODE === `c_add)
+        begin 
+           for (pipe = 2; pipe <= C_LATENCY+2; pipe = pipe + 1)
+           begin
+              intQpipe[pipe] <= 1'b0;
+	   	  	  intQ_C_OUTpipe[pipe] <= 1'b0;
+		      intQ_B_OUTpipe[pipe] <= 1'b0;
+		   	  intQ_OVFLpipe[pipe] <= 1'b0;
+           end 
+        end
+		else if(CLK === 1'b1 && lastCLK === 1'b0 && intQCE === 1'b1) // OK! Update pipelines!
+		begin
+ 		   for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+		   begin
+		      intQpipe[pipe] <= intQpipe[pipe+1];
+		   	  intQ_C_OUTpipe[pipe] <= intQ_C_OUTpipe[pipe+1];
+		   	  intQ_B_OUTpipe[pipe] <= intQ_B_OUTpipe[pipe+1];
+		   	  intQ_OVFLpipe[pipe] <= intQ_OVFLpipe[pipe+1];
+		   end
+		   
+		   intQpipe[C_LATENCY] <= intS;
+		   intQ_C_OUTpipe[C_LATENCY] <= intC_OUT;
+		   intQ_B_OUTpipe[C_LATENCY] <= intB_OUT;
+		   intQ_OVFLpipe[C_LATENCY] <= intOVFL;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intQCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+			begin
+				if(intQ_C_OUTpipe[pipe] !== intQ_C_OUTpipe[pipe+1])
+					intQ_C_OUTpipe[pipe] <= 1'bx;
+				if(intQ_B_OUTpipe[pipe] !== intQ_B_OUTpipe[pipe+1])
+					intQ_B_OUTpipe[pipe] <= 1'bx;
+				if(intQ_OVFLpipe[pipe] !== intQ_OVFLpipe[pipe+1])
+					intQ_OVFLpipe[pipe] <= 1'bx;
+				tmp_pipe1 = intQpipe[pipe];
+				tmp_pipe2 = intQpipe[pipe+1];
+				for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				intQpipe[pipe] <= tmp_pipe1;
+			end
+			if(intQ_C_OUTpipe[C_LATENCY] !== intC_OUT)
+				intQ_C_OUTpipe[C_LATENCY] <= 1'bx;
+			if(intQ_B_OUTpipe[C_LATENCY] !== intB_OUT)
+				intQ_B_OUTpipe[C_LATENCY] <= 1'bx;
+			if(intQ_OVFLpipe[C_LATENCY] !== intOVFL)
+				intQ_OVFLpipe[C_LATENCY] <= 1'bx;
+			for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== intS[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			intQpipe[C_LATENCY] <= tmp_pipe1;
+		end
+	end
+	
+	always@(intS or intQpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQpipeend <= intS;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQpipeend <= intQpipe[2];
+	end
+	
+	always@(intC_OUT or intQ_C_OUTpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_C_OUTpipeend <= intC_OUT;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQ_C_OUTpipeend <= intQ_C_OUTpipe[2];
+	end
+	
+	always@(intB_OUT or intQ_B_OUTpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_B_OUTpipeend <= intB_OUT;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQ_B_OUTpipeend <= intQ_B_OUTpipe[2];
+	end
+	
+	always@(intOVFL or intQ_OVFLpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_OVFLpipeend <= intOVFL;
+		else if (lastADD === intADD)
+			// Pipeline stages required 
+			intQ_OVFLpipeend <= intQ_OVFLpipe[2];
+	end   
+
+
+	always@(CLK)
+		lastCLK <= CLK;
+	
+
+
+/* helper functions */
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+		
+	function [C_B_WIDTH - 1 : 0] to_bitsB;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_B_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+				to_bitsB[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bitsB[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bitsB[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bitsB[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+    function max_bval;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer last_val;
+	integer non_null_string;
+	begin
+		non_null_string = 1;
+		for(i = 0; i < C_B_WIDTH; i = i + 1)
+		begin // Is the string empty?
+		
+		//	if(instring[(i*8)] == 0 && 
+		//		instring[(i*8)-1] == 0 && 
+		//		instring[(i*8)-2] == 0 && 
+		//		instring[(i*8)-3] == 0 && 
+	   //			instring[(i*8)-4] == 0 && 
+		//		instring[(i*8)-5] == 0 && 
+		 //		instring[(i*8)-6] == 0 && 
+		//		instring[(i*8)-7] == 0 &&
+		//		non_null_string == 1)
+		//		non_null_string = 0;
+
+             // is string a '0'				 
+	   //		else if(instring[(i*8)] == 0 && 
+	            if(instring[(i*8)] == 0 &&
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0 &&
+					non_null_string == 1)
+//				 	non_null_string = 1;
+					last_val = 0;
+				  // Or is it a '1'? 
+  		        else if(instring[(i*8)] == 0 && 
+		 			instring[(i*8)-1] == 0 && 
+		 			instring[(i*8)-2] == 1 && 
+		 			instring[(i*8)-3] == 1 && 
+		 			instring[(i*8)-4] == 0 && 
+		 			instring[(i*8)-5] == 0 && 
+		 			instring[(i*8)-6] == 0 && 
+		 			instring[(i*8)-7] == 1 &&
+		 			non_null_string == 1)		
+		  
+  		  		   //	non_null_string = 1;
+ 		            last_val = 1;
+				else
+				    non_null_string = 0;
+		end
+
+				max_bval = last_val;
+    end
+	endfunction
+
+	function max;
+	input a;
+	input b;
+	begin
+		max = (a > b) ? a : b;
+	end
+	endfunction
+	
+	function is_X;
+	input [tmpWidth-1 : 0] i;
+	begin
+		is_X = 1'b0;
+		for(j = 0; j < tmpWidth; j = j + 1)
+		begin
+			if(i[j] === 1'bx) 
+				is_X = 1'b1;
+		end // loop
+	end
+	endfunction
+	
+	function [tmpWidth-1 : 0] add;
+	input [tmpWidth-1 : 0] i1;
+	input [tmpWidth-1 : 0] i2;
+	integer bit_index;
+	integer carryin, carryout;
+	begin
+		carryin = 0;
+		carryout = 0;
+		for(bit_index=0; bit_index < tmpWidth; bit_index = bit_index + 1)
+		begin
+			add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin;
+			carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index]));
+			carryin = carryout;
+		end
+	end
+	endfunction
+	
+	function [tmpWidth-1 : 0] sub;
+	input [tmpWidth-1 : 0] i1;
+	input [tmpWidth-1 : 0] i2;
+	begin
+		i2 = add(~i2, 1);
+		sub = add(i1, i2);
+	end
+	endfunction
+	
+	function [tmpWidth-2 : 0] sm_add;
+	input [tmpWidth-2 : 0] i1;
+	input [tmpWidth-2 : 0] i2;
+	integer bit_index;
+	integer carryin, carryout;
+	begin
+		carryin = 0;
+		carryout = 0;
+		for(bit_index=0; bit_index < tmpWidth-1; bit_index = bit_index + 1)
+		begin
+			sm_add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin;
+			carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index]));
+			carryin = carryout;
+		end
+	end
+	endfunction
+	
+	function [tmpWidth-2 : 0] sm_sub;
+	input [tmpWidth-2 : 0] i1;
+	input [tmpWidth-2 : 0] i2;
+	begin
+		i2 = sm_add(~i2, 1);
+		sm_sub = sm_add(i1, i2);
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_add
+`undef c_sub
+`undef c_add_sub
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef allUKs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V7_0.v

@@ -0,0 +1,772 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+
+/* $Id: C_ADDSUB_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_ADDSUB_V7_0.v
+-- Author - Xilinx
+-- Creation - 22 Mar 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_ADDSUB_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_add 0
+`define c_sub 1
+`define c_add_sub 2
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}}
+
+module C_ADDSUB_V7_0 (A, B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT,
+					  SCLR, SSET, SINIT, A_SIGNED, B_SIGNED, OVFL, C_OUT, B_OUT,
+					  Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q);
+
+	parameter C_ADD_MODE 		= `c_add;
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_A_TYPE 			= `c_unsigned;
+	parameter C_A_WIDTH 		= 16;
+	parameter C_BYPASS_ENABLE 	= `c_override;
+	parameter C_BYPASS_LOW 		= 0;
+	parameter C_B_CONSTANT 		= 0;
+	parameter C_B_TYPE 			= `c_unsigned;
+	parameter C_B_VALUE 		= "0000000000000000";
+	parameter C_B_WIDTH 		= 16;
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_ADD 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_A_SIGNED 	= 0;
+	parameter C_HAS_BYPASS 		= 0;
+	parameter C_HAS_BYPASS_WITH_CIN = 0;
+    parameter C_HAS_B_IN 		= 1;
+	parameter C_HAS_B_OUT 		= 0;
+	parameter C_HAS_B_SIGNED 	= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_C_IN 		= 1;
+	parameter C_HAS_C_OUT 		= 0;
+	parameter C_HAS_OVFL 		= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_Q_B_OUT 	= 0;
+	parameter C_HAS_Q_C_OUT 	= 0;
+	parameter C_HAS_Q_OVFL 		= 0;
+	parameter C_HAS_S 			= 0; 
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HIGH_BIT 		= 15;
+	parameter C_LATENCY	       	= 1;
+	parameter C_LOW_BIT 		= 0;
+	parameter C_OUT_WIDTH 		= 16;
+	parameter C_PIPE_STAGES 	= 1;
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+	
+	
+	// internal parameters (not to be set from instanciation)
+	parameter tmpWidth = (C_A_WIDTH > C_B_WIDTH) ? C_A_WIDTH + 2 : C_B_WIDTH + 2;
+	parameter output_reg_width = C_HIGH_BIT-C_LOW_BIT+1;
+
+	input [C_A_WIDTH-1 : 0] A;
+	input [C_B_WIDTH-1 : 0] B;
+	input CLK;
+	input ADD;
+	input C_IN;
+	input B_IN;
+	input CE;
+	input BYPASS;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input A_SIGNED;
+	input B_SIGNED;
+	output OVFL;
+	output C_OUT;
+	output B_OUT;
+	output Q_OVFL;
+	output Q_C_OUT;
+	output Q_B_OUT;
+	output [C_HIGH_BIT : C_LOW_BIT] S;
+	output [C_HIGH_BIT : C_LOW_BIT] Q;
+    
+	
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_B_WIDTH-1 : 0] intBconst;
+	wire [C_B_WIDTH-1 : 0] intB;
+	wire intADD;
+	wire intBYPASS;
+	wire intC_IN;
+	wire intB_IN;
+	wire intCE;
+	wire intQCE;
+	wire intA_SIGNED;
+	wire intB_SIGNED;
+	reg intC_OUT;
+	reg intB_OUT;
+	reg intOVFL;
+	wire intQ_C_OUT;
+	wire intQ_B_OUT;
+	wire intQ_OVFL;
+	reg [C_HIGH_BIT : C_LOW_BIT ] intS;
+	wire [C_HIGH_BIT : C_LOW_BIT ] intQ;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	wire intACLR_INIT;
+	wire intSCLR_INIT;
+	wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode
+	reg lastCLK;
+	reg lastADD;
+    wire [8 : 1] b_max;	
+	reg [C_HIGH_BIT : C_LOW_BIT] intQpipe [C_LATENCY+2 : 0]; 
+	reg [C_LATENCY+2 : 0] intQ_C_OUTpipe; 
+	reg [C_LATENCY+2 : 0] intQ_B_OUTpipe; 
+	reg [C_LATENCY+2 : 0] intQ_OVFLpipe; 
+	reg [C_LATENCY-1 : 0] intADDpipe;
+
+	reg [C_HIGH_BIT : C_LOW_BIT] intQpipeend;
+	reg intQ_C_OUTpipeend;
+	reg intQ_B_OUTpipeend;
+	reg intQ_OVFLpipeend;
+	reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe1;
+	reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe2;
+	
+	 
+	wire [C_HIGH_BIT : C_LOW_BIT] Q = (C_HAS_Q == 1 ? intQ : `allUKs);
+	wire Q_C_OUT = (C_HAS_Q_C_OUT == 1 ? intQ_C_OUT : 1'bx);
+	wire Q_B_OUT = (C_HAS_Q_B_OUT == 1 ? intQ_B_OUT : 1'bx);
+	wire Q_OVFL = (C_HAS_Q_OVFL == 1 ? intQ_OVFL : 1'bx);
+	wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs);
+	wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx);
+	wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx);
+	wire OVFL = (C_HAS_OVFL == 1 ? intOVFL : 1'bx);
+	
+	// Sort out default values for missing ports
+	
+	assign b_max = max_bval(C_B_VALUE);
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intACLR_INIT = (intACLR || intAINIT);
+	assign intSCLR_INIT = (intSCLR || intSINIT);
+	
+	assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B;
+//	assign intADD = (C_HAS_ADD === 1) ? ((C_LATENCY < 2) ? ADD : intADDpipe[C_LATENCY-1]) : ((C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3)); // 3 is an illegal value since this is an illegal option!	
+	assign intADD =  (C_HAS_ADD === 1) ? ADD :  (C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3); // 3 is an illegal value since this is an illegal option!	
+	assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0;
+	assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; // new parameter to allow the bypass mode to take account of the c_in
+	assign intC_IN = ((C_HAS_C_IN === 1) ? C_IN : ((C_HAS_ADD === 1) ? ~intADD : 0));
+	assign intB_IN = defval(B_IN, C_HAS_B_IN, 1);
+	assign intA_SIGNED = defval(A_SIGNED, C_HAS_A_SIGNED, 0);
+	//assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0);
+	assign intB_SIGNED = ((C_HAS_B_SIGNED === 0) ? 0 : (((C_HAS_B_SIGNED === 1) && ~((C_B_CONSTANT === 1) && (C_HAS_BYPASS === 0) && (b_max === 0)) ? B_SIGNED : 0))) ;
+	assign intB = (intBYPASS === 0 ? intBconst : B);
+	assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1);
+	
+	integer j, k;
+	integer pipe, pipe1;
+	integer i;
+	
+	reg [tmpWidth-1 : 0] tmpA;
+	reg [tmpWidth-1 : 0] tmpB;
+	reg [tmpWidth-1 : 0] tmpC;
+	reg [tmpWidth-1 : 0] tmpBC;
+	reg [tmpWidth-1 : 0] tmpABC;
+	reg [tmpWidth-2 : 0] tmpD;
+	reg [tmpWidth-2 : 0] tmpE;
+	reg [tmpWidth-2 : 0] tmpF;
+	
+	// Registers on outputs by default
+	C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, output_reg_width)
+		regq (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regcout (.D(intQ_C_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_C_OUT)); 
+
+	C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regbout (.D(intQ_B_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_B_OUT)); 
+
+	C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		regovfl (.D(intQ_OVFLpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT),
+			  .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET),
+			  .Q(intQ_OVFL)); 
+	
+	initial
+	begin
+	 	#1;
+		for(i = 0; i <= C_LATENCY+2; i = i + 1)
+		begin
+			intQpipe[i] = 'bx;
+			intQ_C_OUTpipe[i] = 1'bx;
+			intQ_B_OUTpipe[i] = 1'bx;
+			intQ_OVFLpipe[i] = 1'bx;
+		end
+		intQpipeend = `allUKs;
+		intQ_C_OUTpipeend = 1'bx;
+		intQ_B_OUTpipeend = 1'bx;
+		intQ_OVFLpipeend = 1'bx;
+		intS = `allUKs;
+		intC_OUT = 1'bx;
+		intB_OUT = 1'bx;
+		intOVFL = 1'bx;
+	end
+	
+	always@(A or intB or intADD or intBYPASS or intC_IN or intB_IN or intA_SIGNED or intB_SIGNED)
+	begin
+		tmpC = 0;
+		if(intC_IN !== 1'b0)
+		begin
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpC = intC_IN;
+			end
+		end
+		else if(intC_IN !== 1'b1 && C_ADD_MODE == `c_add_sub && intADD === 1'b0)
+		begin
+			tmpC[0] = ~intC_IN;
+		end
+		else if(intB_IN !== 1'b1 && C_ADD_MODE == `c_sub)
+		begin
+			tmpC[0] = ~intB_IN;
+		end
+		
+		if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED === 1))
+		begin
+			for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1)
+			begin
+				tmpA[j] = A[C_A_WIDTH-1];
+			end
+		end
+		else if(C_A_TYPE == `c_unsigned || (C_A_TYPE == `c_pin && intA_SIGNED === 0))
+		begin
+			for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1)
+			begin
+				tmpA[j] = 0;
+			end
+		end
+		
+		tmpA[C_A_WIDTH-1 : 0] = A;
+		
+		if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1))
+		begin
+			for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1)
+			begin
+				tmpB[j] = intB[C_B_WIDTH-1];
+			end
+		end
+		else if(C_B_TYPE == `c_unsigned || (C_B_TYPE == `c_pin && intB_SIGNED === 0))
+		begin
+			for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1)
+			begin
+				tmpB[j] = 0;
+			end
+		end
+		
+		tmpB[C_B_WIDTH-1 : 0] = intB;
+		
+		if(intBYPASS == 1 && intBYPASS_WITH_CIN == 0)
+		begin
+			intS <= #1 tmpB[C_HIGH_BIT : C_LOW_BIT];
+			if (is_X(tmpB))
+			begin
+				intC_OUT <= #1 1'bx;
+				intB_OUT <= #1 1'bx;
+				intOVFL <= #1 1'bx;
+			end
+			else
+			begin
+				intC_OUT <= #1 1'b0;
+				intB_OUT <= #1 1'b0;
+				intOVFL <= #1 1'b0;
+			end
+		end
+		else if(is_X(tmpA) || is_X(tmpB) || is_X(tmpC) || intBYPASS === 1'bx || intADD === 1'bx)
+		begin
+			intS <= #1 {C_HIGH_BIT-C_LOW_BIT+1{1'bx}};
+			intC_OUT <= #1 1'bx;
+			intB_OUT <= #1 1'bx;
+			intOVFL <= #1 1'bx;
+		end
+		else if (intBYPASS == 1 && intBYPASS_WITH_CIN == 1) // new section to model the behaviour of the new
+		begin                                               // c_has_bypass_with_cin mode. This mode is only available 
+			tmpBC = add(tmpB, tmpC);                        // for Adder variations.
+			
+			intS <= #1 tmpBC[C_HIGH_BIT : C_LOW_BIT];
+			
+			if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1)
+			begin
+				intC_OUT <= #1 tmpBC[tmpWidth-2];
+			end
+						
+			if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+			begin
+								
+			if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+			begin
+				tmpD[tmpWidth-2 : 0] =  {tmpWidth - 1{1'b0}};
+				tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0];
+				tmpE[tmpWidth-2] = tmpBC[tmpWidth-1];
+                tmpF = sm_add(tmpD, tmpE);				
+				intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpBC[tmpWidth-2];
+			end
+			end
+		end
+        else
+		begin
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpBC = add(tmpB, tmpC);
+			end
+			else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+			begin
+				tmpBC = add(tmpB, tmpC);
+			end
+			
+			if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+			begin
+				tmpABC = add(tmpA, tmpBC);
+			end
+			else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+			begin
+				tmpABC = sub(tmpA, tmpBC);
+			end
+			
+			intS <= #1 tmpABC[C_HIGH_BIT : C_LOW_BIT];
+			
+			if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1)
+			begin
+				if((C_ADD_MODE == `c_add_sub && intADD === 1'b1) || C_ADD_MODE == `c_add)
+					intC_OUT <= #1 tmpABC[tmpWidth-2];
+				else if(C_ADD_MODE == `c_add_sub && intADD === 1'b0)
+					intC_OUT <= #1 ~tmpABC[tmpWidth-2];
+			end
+			
+			if(C_HAS_B_OUT == 1 || C_HAS_Q_B_OUT == 1)
+			begin
+				intB_OUT <= #1 !tmpABC[tmpWidth-2];
+			end
+			
+			if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1)
+			begin
+				tmpD[tmpWidth-3 : 0] = tmpA[tmpWidth-3 : 0];
+				if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED == 1)) 
+					tmpD[tmpWidth-2] = tmpA[tmpWidth-1];
+				else
+					tmpD[tmpWidth-2] = 1'b0;
+				tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0];
+				if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED == 1)) 
+					tmpE[tmpWidth-2] = tmpBC[tmpWidth-1];
+				else
+					tmpE[tmpWidth-2] = 1'b0;
+				if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add)
+				begin
+					tmpF = sm_add(tmpD, tmpE);
+				end
+				else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub)
+				begin
+					tmpF = sm_sub(tmpD, tmpE);
+				end
+				
+				intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpABC[tmpWidth-2];
+			end
+		end						
+	end
+	
+	always@(posedge CLK)
+		lastADD <= intADD;
+	
+	always@(posedge CLK )
+	begin
+        if ((intACLR === 1'b1 || intSCLR === 1'b1) && C_ADD_MODE === `c_add)
+        begin 
+           for (pipe = 2; pipe <= C_LATENCY+2; pipe = pipe + 1)
+           begin
+              intQpipe[pipe] <= 1'b0;
+	   	  	  intQ_C_OUTpipe[pipe] <= 1'b0;
+		      intQ_B_OUTpipe[pipe] <= 1'b0;
+		   	  intQ_OVFLpipe[pipe] <= 1'b0;
+           end 
+        end
+		else if(CLK === 1'b1 && lastCLK === 1'b0 && intQCE === 1'b1) // OK! Update pipelines!
+		begin
+ 		   for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+		   begin
+		      intQpipe[pipe] <= intQpipe[pipe+1];
+		   	  intQ_C_OUTpipe[pipe] <= intQ_C_OUTpipe[pipe+1];
+		   	  intQ_B_OUTpipe[pipe] <= intQ_B_OUTpipe[pipe+1];
+		   	  intQ_OVFLpipe[pipe] <= intQ_OVFLpipe[pipe+1];
+		   end
+		   
+		   intQpipe[C_LATENCY] <= intS;
+		   intQ_C_OUTpipe[C_LATENCY] <= intC_OUT;
+		   intQ_B_OUTpipe[C_LATENCY] <= intB_OUT;
+		   intQ_OVFLpipe[C_LATENCY] <= intOVFL;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intQCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1)
+			begin
+				if(intQ_C_OUTpipe[pipe] !== intQ_C_OUTpipe[pipe+1])
+					intQ_C_OUTpipe[pipe] <= 1'bx;
+				if(intQ_B_OUTpipe[pipe] !== intQ_B_OUTpipe[pipe+1])
+					intQ_B_OUTpipe[pipe] <= 1'bx;
+				if(intQ_OVFLpipe[pipe] !== intQ_OVFLpipe[pipe+1])
+					intQ_OVFLpipe[pipe] <= 1'bx;
+				tmp_pipe1 = intQpipe[pipe];
+				tmp_pipe2 = intQpipe[pipe+1];
+				for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				intQpipe[pipe] <= tmp_pipe1;
+			end
+			if(intQ_C_OUTpipe[C_LATENCY] !== intC_OUT)
+				intQ_C_OUTpipe[C_LATENCY] <= 1'bx;
+			if(intQ_B_OUTpipe[C_LATENCY] !== intB_OUT)
+				intQ_B_OUTpipe[C_LATENCY] <= 1'bx;
+			if(intQ_OVFLpipe[C_LATENCY] !== intOVFL)
+				intQ_OVFLpipe[C_LATENCY] <= 1'bx;
+			for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== intS[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			intQpipe[C_LATENCY] <= tmp_pipe1;
+		end
+	end
+	
+	always@(intS or intQpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQpipeend <= intS;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQpipeend <= intQpipe[2];
+	end
+	
+	always@(intC_OUT or intQ_C_OUTpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_C_OUTpipeend <= intC_OUT;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQ_C_OUTpipeend <= intQ_C_OUTpipe[2];
+	end
+	
+	always@(intB_OUT or intQ_B_OUTpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_B_OUTpipeend <= intB_OUT;
+		else if (lastADD === intADD)
+			// Pipeline stages required
+			intQ_B_OUTpipeend <= intQ_B_OUTpipe[2];
+	end
+	
+	always@(intOVFL or intQ_OVFLpipe[2] or intADD or lastADD)
+	begin
+		if(C_LATENCY < 2) // No pipeline
+			intQ_OVFLpipeend <= intOVFL;
+		else if (lastADD === intADD)
+			// Pipeline stages required 
+			intQ_OVFLpipeend <= intQ_OVFLpipe[2];
+	end   
+
+
+	always@(CLK)
+		lastCLK <= CLK;
+	
+
+
+/* helper functions */
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+		
+	function [C_B_WIDTH - 1 : 0] to_bitsB;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_B_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+				to_bitsB[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_B_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bitsB[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bitsB[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bitsB[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+    function max_bval;
+	input [C_B_WIDTH*8 : 1] instring;
+	integer i;
+	integer last_val;
+	integer non_null_string;
+	begin
+		non_null_string = 1;
+		for(i = 0; i < C_B_WIDTH; i = i + 1)
+		begin // Is the string empty?
+		
+		//	if(instring[(i*8)] == 0 && 
+		//		instring[(i*8)-1] == 0 && 
+		//		instring[(i*8)-2] == 0 && 
+		//		instring[(i*8)-3] == 0 && 
+	   //			instring[(i*8)-4] == 0 && 
+		//		instring[(i*8)-5] == 0 && 
+		 //		instring[(i*8)-6] == 0 && 
+		//		instring[(i*8)-7] == 0 &&
+		//		non_null_string == 1)
+		//		non_null_string = 0;
+
+             // is string a '0'				 
+	   //		else if(instring[(i*8)] == 0 && 
+	            if(instring[(i*8)] == 0 &&
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0 &&
+					non_null_string == 1)
+//				 	non_null_string = 1;
+					last_val = 0;
+				  // Or is it a '1'? 
+  		        else if(instring[(i*8)] == 0 && 
+		 			instring[(i*8)-1] == 0 && 
+		 			instring[(i*8)-2] == 1 && 
+		 			instring[(i*8)-3] == 1 && 
+		 			instring[(i*8)-4] == 0 && 
+		 			instring[(i*8)-5] == 0 && 
+		 			instring[(i*8)-6] == 0 && 
+		 			instring[(i*8)-7] == 1 &&
+		 			non_null_string == 1)		
+		  
+  		  		   //	non_null_string = 1;
+ 		            last_val = 1;
+				else
+				    non_null_string = 0;
+		end
+
+				max_bval = last_val;
+    end
+	endfunction
+
+	function max;
+	input a;
+	input b;
+	begin
+		max = (a > b) ? a : b;
+	end
+	endfunction
+	
+	function is_X;
+	input [tmpWidth-1 : 0] i;
+	begin
+		is_X = 1'b0;
+		for(j = 0; j < tmpWidth; j = j + 1)
+		begin
+			if(i[j] === 1'bx) 
+				is_X = 1'b1;
+		end // loop
+	end
+	endfunction
+	
+	function [tmpWidth-1 : 0] add;
+	input [tmpWidth-1 : 0] i1;
+	input [tmpWidth-1 : 0] i2;
+	integer bit_index;
+	integer carryin, carryout;
+	begin
+		carryin = 0;
+		carryout = 0;
+		for(bit_index=0; bit_index < tmpWidth; bit_index = bit_index + 1)
+		begin
+			add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin;
+			carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index]));
+			carryin = carryout;
+		end
+	end
+	endfunction
+	
+	function [tmpWidth-1 : 0] sub;
+	input [tmpWidth-1 : 0] i1;
+	input [tmpWidth-1 : 0] i2;
+	begin
+		i2 = add(~i2, 1);
+		sub = add(i1, i2);
+	end
+	endfunction
+	
+	function [tmpWidth-2 : 0] sm_add;
+	input [tmpWidth-2 : 0] i1;
+	input [tmpWidth-2 : 0] i2;
+	integer bit_index;
+	integer carryin, carryout;
+	begin
+		carryin = 0;
+		carryout = 0;
+		for(bit_index=0; bit_index < tmpWidth-1; bit_index = bit_index + 1)
+		begin
+			sm_add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin;
+			carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index]));
+			carryin = carryout;
+		end
+	end
+	endfunction
+	
+	function [tmpWidth-2 : 0] sm_sub;
+	input [tmpWidth-2 : 0] i1;
+	input [tmpWidth-2 : 0] i2;
+	begin
+		i2 = sm_add(~i2, 1);
+		sm_sub = sm_add(i1, i2);
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_add
+`undef c_sub
+`undef c_add_sub
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef allUKs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_BIT_CORRELATOR_V3_0.v

@@ -0,0 +1,438 @@
+//-- $ID:$
+// ************************************************************************
+// $Id: C_BIT_CORRELATOR_V3_0.V
+// ************************************************************************
+// Copyright 2000 - Xilinx Inc.
+// All rights reserved.
+// ************************************************************************
+// Filename: C_BIT_CORRELATOR_V3_0.V 
+// Creation : Nov. 1th, 2000
+// Description: Verilog Behavioral Model for bit_correlator Model
+// 
+// Algorithm : Compares the bits of a sequence, with a pattern
+//             which may/maynot have some bits masked. The sequence
+//             can be from upto 8 possible channels, sequencing every
+//             clock cycle. (currently supported for serial input)
+// ************************************************************************
+// ************************************************************************
+// Last Change :
+//
+// ************************************************************************
+
+`timescale 1ns/10ps 
+
+// some definitions
+
+`define true  1'b1
+`define false 1'b0
+
+`define c_enable_rlocs   0
+
+`define c_serial 0
+`define c_parallel_2_serial 1
+`define c_parallel 2
+
+`define c_no_reload 0
+`define c_reload 1
+
+module C_BIT_CORRELATOR_V3_0
+  (CLK,                     // clock
+   DIN,                     // Data INput
+   LD_DIN, LD_WE, COEF_LD,  // unsupported reload ports for version 3.0
+   ND,                      // qualifying signal for DIN, new data
+   DOUT,                    // Data OUTput
+   RDY, RFD,                //DOUT qualifier ReaDY, ND qualifier Ready_For_Data
+   SEL_I, SEL_O);           // Input and Output channel indicator
+
+  parameter C_CHANNELS          = 1;
+  parameter C_DATA_WIDTH        = 1;
+  // unsupported placement option for version 3.0
+  parameter C_ENABLE_RLOCS      = `false;
+  parameter C_HAS_MASK          = `false;
+  parameter C_HAS_SEL_INDICATOR      = `false;
+  parameter C_INPUT_TYPE        = `c_serial;
+  parameter C_LATENCY           = 2; //latency in correlating,
+                                     //doesn't include latency 
+                                     //due to reading data 
+  parameter C_MEM_INIT_FILE     = "bit_corr_16.mif";
+  
+  // unsupported reload options for version 3.0
+  parameter C_RELOAD            = `c_no_reload; 
+  parameter C_RELOAD_DELAY      = 0;
+  parameter C_RELOAD_MEM_TYPE   = 0;
+
+  // unsupported placement option for version 3.0
+  parameter C_SHAPE             = 0;
+
+  // number of taps of the bit correlator
+  parameter C_TAPS              = 16;
+  
+  /******* number of bits needed to represent #channels ********/
+  parameter channel_width = ((C_CHANNELS <=2) ? 1:
+                            ((C_CHANNELS <=4) ? 2:
+                            ((C_CHANNELS <=8) ? 3:4)));
+  
+  /*************************************************************
+   using word 'score' to mean the #bits matching and score_width
+   is the bit_width required to represent this number.
+  *************************************************************/
+  parameter score_width   = ((C_TAPS <    2) ? 1:
+                            ((C_TAPS <    4) ? 2:
+                            ((C_TAPS <    8) ? 3:
+                            ((C_TAPS <   16) ? 4:
+                            ((C_TAPS <   32) ? 5:
+                            ((C_TAPS <   64) ? 6:
+                            ((C_TAPS <  128) ? 7:
+                            ((C_TAPS <  256) ? 8:
+                            ((C_TAPS <  512) ? 9:
+                            ((C_TAPS < 1024) ? 10:
+                            ((C_TAPS < 2048) ? 11:
+                            ((C_TAPS < 4096) ? 12:13))))))))))));
+  parameter rfd_delay     = ((C_INPUT_TYPE == `c_parallel_2_serial) ? 
+                                                             C_DATA_WIDTH : 1);
+  parameter rdy_counter_max = rfd_delay;
+  
+  parameter rdy_latency   = C_LATENCY;
+  
+  parameter actual_input_width = ((C_INPUT_TYPE == `c_serial) ? 1:
+                                 ((C_INPUT_TYPE == `c_parallel) ? C_TAPS :
+                                          C_DATA_WIDTH));
+  input CLK;
+  input [actual_input_width - 1 : 0] DIN;
+  input LD_DIN;   // not supported in version 3.0
+  input LD_WE;    // not supported in version 3.0
+  input COEF_LD;  // not supported in version 3.0
+  input ND;
+  
+  output [score_width - 1 : 0] DOUT;
+  output RDY;
+  output RFD;
+  output [channel_width - 1 : 0] SEL_I;
+  output [channel_width - 1 : 0] SEL_O;
+
+  reg [score_width - 1 : 0] DOUT;
+  reg RDY;
+  reg RFD;
+  reg [channel_width - 1 : 0] SEL_I;
+  reg [channel_width - 1 : 0] SEL_O;
+  
+  reg local_rdy;
+
+  // registers for input storage
+  reg [C_TAPS - 1        : 0] reg_din[C_CHANNELS - 1:0];
+  reg [C_TAPS - 1        : 0] tmp_din;
+  reg [C_TAPS - 1        : 0] tmp_reg_din;
+  // registers for pattern and mask
+  reg [C_TAPS - 1        : 0] pattern;
+  reg [C_TAPS - 1        : 0] mask;
+
+  reg [channel_width - 1 : 0] in_channel;
+  reg [score_width - 1   : 0] count;
+  //reg [C_DATA_WIDTH - 1  : 0] psc_din;
+  reg [actual_input_width - 1  : 0] psc_din;  //hp, 30jul, trying to correct
+                          //the VSS/VCS error messages for psc_bin(C_DATA_WIDTH-1:1) usage.
+  reg [score_width       : 0] dout_array[ C_LATENCY - 1 :0];
+  reg [score_width       : 0] sel_o_array[ C_LATENCY - 1:0];
+  reg rdy_array[ rdy_latency : 0];
+  
+  reg input_buffer_empty;
+
+  integer count_rfd, delay, count_rdy;
+  integer i, bits;
+  integer start_correlator; //integer value to start off the process
+
+  integer load_counter;
+  
+  /************** shift new data into corresponding channel ***********/
+  task shift_data;
+  
+  begin
+    if (C_INPUT_TYPE == `c_parallel) 
+    begin
+      if ((ND == 1'b1) && (RFD == 1'b1))
+        reg_din[0] = DIN;
+    end
+    else if(C_INPUT_TYPE == `c_serial)
+    begin
+      if((ND == 1'b1) && (RFD == 1'b1))
+      begin
+        tmp_din = reg_din[in_channel];
+        if(C_TAPS > 1)
+          tmp_din = {tmp_din[(C_TAPS - 2) : 0], DIN};
+        else
+          tmp_din = DIN;
+        reg_din[in_channel] = tmp_din;
+      end
+    end
+    else if(C_INPUT_TYPE == `c_parallel_2_serial)
+    begin
+      if((ND == 1'b1) && (RFD == 1'b1))
+      begin
+        psc_din = DIN;
+        load_counter = 0;
+      end
+
+      else if ((load_counter < (actual_input_width-1)) && (actual_input_width> 1))
+      begin
+        for (i = 0; i <= actual_input_width - 1;i=i + 1)
+        begin
+          if(i== (actual_input_width - 1) )
+            psc_din[actual_input_width - 1] = 1'b0;
+          else 
+            psc_din[i] = psc_din[i+1];
+        end
+         //psc_din = {1'b0, psc_din[(actual_input_width - 1): 1]};
+        load_counter = load_counter + 1;
+      end
+
+      if((ND == 1'b0) && (RFD == 1'b1))
+        input_buffer_empty = 1'b1;
+      else
+        input_buffer_empty = 1'b0;
+        
+  
+      tmp_din = reg_din[in_channel];
+      if (input_buffer_empty == 1'b0)
+      begin
+      if(C_TAPS > 1) 
+        tmp_din = {tmp_din[(C_TAPS -2) : 0], psc_din[0]};
+      else
+        tmp_din = psc_din[0];
+      end
+      reg_din[in_channel] = tmp_din;
+    end
+  end
+  endtask
+  
+  /************** read the file for pattern and mask bits ***********/
+  task read_pattern_mask;
+  
+  reg[3:0] data_from_file[(C_TAPS -1) : 0];
+  reg [3:0] tmp;
+  
+  begin
+    // Reading the MIF file and assigning the bits to
+    // pattern and mask variable
+  
+    $readmemh(C_MEM_INIT_FILE, data_from_file);
+  
+    for(i=0;i<C_TAPS;i=i+1)
+    begin
+      tmp = data_from_file[i]; 
+      pattern[i] = tmp[0];       
+      if(C_HAS_MASK)
+        mask[i] = tmp[1];
+      else
+        mask[i] = 1'b1;
+    end
+  
+  end 
+  endtask //end task
+  
+  /***********************************************************************
+   * Initializing various registers
+  ***********************************************************************/
+  initial
+
+  begin
+  
+    //for (bits=0;bits <= C_TAPS - 1;bits=bits+1)
+    //  tmp_din[bits] = 0;
+
+    tmp_din = {C_TAPS{1'b0}};
+    tmp_reg_din = {C_TAPS{1'b0}};
+    //psc_din = {C_DATA_WIDTH{1'b0}};
+    //hp, 30jul, trying to correct
+    //the VSS/VCS error messages for psc_bin(C_DATA_WIDTH-1:1) usage.
+    psc_din = {actual_input_width{1'b0}};
+
+    for (i = 0;i < C_CHANNELS;i=i + 1)
+      reg_din[i] = tmp_din;
+  
+
+  // Initializing the input_channel_select_indicator
+       in_channel = 0;
+      if((C_HAS_SEL_INDICATOR) && (C_INPUT_TYPE == `c_serial))
+      begin
+        SEL_I = in_channel;
+      end
+      else
+      begin
+        SEL_I = {channel_width{1'bx}};
+      end
+
+  // Initializing the output_channel_select_indicator
+      if((C_HAS_SEL_INDICATOR) && (C_INPUT_TYPE == `c_serial))
+      begin
+        SEL_O = {channel_width{1'b0}};
+      end
+      else
+        SEL_O = {channel_width{1'bx}};
+
+
+    // Set the value for count_rfd, RFD, RDY
+      count_rfd = rfd_delay - 2;
+      
+      RFD = 1;
+      RDY = 0;
+      local_rdy = 0;
+      DOUT = 0;
+
+      count_rdy = 0;
+      count_rfd = 0;
+
+      for (i = 0; i<= C_LATENCY - 1; i = i+1)
+      begin
+        sel_o_array[i] = 0;
+        dout_array[i] = 0;
+      end
+      for (i = 0; i<= C_LATENCY - 1; i = i+1)
+        rdy_array[i] = 0;
+      
+    // initialize the pattern
+      read_pattern_mask;
+
+      start_correlator = 0;
+
+  end //initial
+
+/*******************************************************************
+ * Select the data dependent on the input type
+ ******************************************************************/
+  always @ (posedge CLK )
+  begin
+    if ((ND == 1'b1 ) && (RFD == 1'b1))
+    begin
+
+      /*******************  Incrementing channel counter *************/
+      if (C_INPUT_TYPE == `c_serial) 
+        in_channel = (in_channel >= C_CHANNELS -1 ) ? 0: in_channel + 1;
+
+      start_correlator = 1; //basically waiting for 1st ND
+
+    end // ND high
+
+    shift_data;
+
+/*******************  Counting the matched bits ************/
+    if (start_correlator == 0)
+      count = 0;
+    else
+    begin
+      count = 0;
+      tmp_reg_din = reg_din[in_channel];
+      for(bits=0; bits <= (C_TAPS - 1) ; bits = bits + 1)
+      begin
+        if(mask[bits] == 1'b1)
+        begin
+          if(tmp_reg_din[bits] == pattern[bits])
+          begin
+            count = count + 1;
+          end
+        end
+      end
+    end
+  
+    // generate RFD
+    //if((C_INPUT_TYPE == `c_parallel_2_serial) && (C_DATA_WIDTH > 1))
+
+    //hp,30jul, trying to correct
+    //the VSS/VCS error messages for psc_bin(C_DATA_WIDTH-1:1) usage.
+    if((C_INPUT_TYPE == `c_parallel_2_serial) && (actual_input_width > 1))
+    begin
+      if((ND == 1) && (RFD == 1)) // also checking RFD to allow for ND
+                                  // ND to remain high all time when
+                                  // user has the input ready always
+      begin
+        count_rfd = rfd_delay - 2;
+        RFD <= 1'b0;
+      end
+      else if(start_correlator == 1)
+      begin
+        if (count_rfd == 0)  // RFD is pulled high 1 clk cycle earlier
+        begin                  // so that we donot waste one clock.
+          RFD <=  1'b1;
+        end
+        else if (count_rfd > 0)
+        begin
+          RFD <=  1'b0;
+          count_rfd =  (count_rfd - 1);
+        end
+        else
+          $display( "%m,%dns Error: count_rfd < 0", $time);
+      end
+    end
+    else
+      RFD <= 1'b1;
+
+    // local_rdy generation dependent on ND and C_DATA_WIDTH
+
+    if (ND == 1)
+    begin
+      local_rdy = 1;
+      count_rdy = rdy_counter_max - 1;
+    end
+    else
+    begin
+      if(count_rdy == 0)
+      begin
+        local_rdy = 0;
+      end
+      else
+      begin
+        count_rdy = count_rdy - 1;
+        local_rdy = 1;
+      end
+    end
+      
+    // RDY generation
+    if(rdy_latency == 1)
+      RDY <= local_rdy;
+    else
+    begin
+      RDY <= rdy_array[rdy_latency - 2];
+      for (delay = rdy_latency -3 ;delay >= 0;delay = delay -1)
+        rdy_array[delay +1] <= rdy_array[delay];
+      rdy_array[0] <= local_rdy;
+    end
+
+    if (C_LATENCY == 1)
+      DOUT <= count;
+    else if (C_LATENCY >= 2)
+    begin
+      DOUT <= dout_array[C_LATENCY - 2];
+      for ( delay = C_LATENCY - 3; delay >= 0; delay = delay - 1)
+        dout_array[delay + 1] <= dout_array[delay];
+      dout_array[0] <= count;
+    end
+
+    //generate SEL_O 
+    if((C_HAS_SEL_INDICATOR) && (C_INPUT_TYPE == `c_serial))
+    begin
+        if (C_LATENCY >= 1) 
+        begin
+          SEL_O <= sel_o_array[C_LATENCY - 1];
+          for (delay = C_LATENCY - 2;delay >= 0; delay = delay - 1) 
+            sel_o_array[delay + 1] <= sel_o_array[delay];
+          sel_o_array[0] <= in_channel;
+        end
+
+      //generating SEL_O
+      SEL_I = in_channel; 
+    end
+
+  end //always
+
+endmodule
+
+`undef true
+`undef false
+
+`undef c_enable_rlocs
+
+`undef c_serial
+`undef c_parallel_2_serial
+`undef c_parallel
+
+`undef c_no_reload
+`undef c_reload

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V4_0.v

@@ -0,0 +1,409 @@
+/* $Id: C_COUNTER_BINARY_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_COUNTER_BINARY_V4_0.v
+-- Author - Xilinx
+-- Creation -14 July 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_COUNTER_BINARY_V4_0 module
+*/
+
+
+
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define c_up 0
+`define c_down 1
+`define c_updown 2
+`define allXs {C_WIDTH{1'bx}}
+
+module C_COUNTER_BINARY_V4_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q);
+
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_COUNT_BY		= "";
+	parameter C_COUNT_MODE		= `c_up;
+	parameter C_COUNT_TO		= "1111111111111111";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 		= 0;
+	parameter C_HAS_IV 		= 0;
+	parameter C_HAS_L 		= 0;
+	parameter C_HAS_LOAD		= 0;
+	parameter C_HAS_Q_THRESH0	= 0;
+	parameter C_HAS_Q_THRESH1	= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HAS_THRESH0		= 0;
+	parameter C_HAS_THRESH1		= 0;
+	parameter C_HAS_UP 		= 0;
+	parameter C_LOAD_ENABLE 	= `c_no_override;
+	parameter C_LOAD_LOW		= 0;
+	parameter C_PIPE_STAGES 	= 0;    
+	parameter C_RESTRICT_COUNT      = 0;
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_THRESH0_VALUE       = "1111111111111111";
+	parameter C_THRESH1_VALUE       = "1111111111111111";
+	parameter C_THRESH_EARLY        = 1;
+	parameter C_WIDTH		= 16;
+
+	parameter C_OUT_TYPE            = `c_signed;
+	parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0);
+	
+	parameter iaxero = {62{"0"}};
+	parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE};
+	parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE};
+	parameter iazero = {64{"0"}};
+	parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == "0" ? (iextendC_THRESH0_VALUE[1] == "0" ? 
+					(iextendC_THRESH0_VALUE[2] == "0" ? (iextendC_THRESH0_VALUE[3] == "0" ? 
+					(iextendC_THRESH0_VALUE[4] == "0" ? (iextendC_THRESH0_VALUE[5] == "0" ? 
+					(iextendC_THRESH0_VALUE[6] == "0" ? (iextendC_THRESH0_VALUE[7] == "0" ? 
+					(iextendC_THRESH0_VALUE[8] == "0" ? (iextendC_THRESH0_VALUE[9] == "0" ? 
+					(iextendC_THRESH0_VALUE[10] == "0" ? (iextendC_THRESH0_VALUE[11] == "0" ? 
+					(iextendC_THRESH0_VALUE[12] == "0" ? (iextendC_THRESH0_VALUE[13] == "0" ? 
+					(iextendC_THRESH0_VALUE[14] == "0" ? (iextendC_THRESH0_VALUE[15] == "0" ? 
+					(iextendC_THRESH0_VALUE[16] == "0" ? (iextendC_THRESH0_VALUE[17] == "0" ? 
+					(iextendC_THRESH0_VALUE[18] == "0" ? (iextendC_THRESH0_VALUE[19] == "0" ? 
+					(iextendC_THRESH0_VALUE[20] == "0" ? (iextendC_THRESH0_VALUE[21] == "0" ? 
+					(iextendC_THRESH0_VALUE[22] == "0" ? (iextendC_THRESH0_VALUE[23] == "0" ? 
+					(iextendC_THRESH0_VALUE[24] == "0" ? (iextendC_THRESH0_VALUE[25] == "0" ? 
+					(iextendC_THRESH0_VALUE[26] == "0" ? (iextendC_THRESH0_VALUE[27] == "0" ? 
+					(iextendC_THRESH0_VALUE[28] == "0" ? (iextendC_THRESH0_VALUE[29] == "0" ? 
+					(iextendC_THRESH0_VALUE[30] == "0" ? (iextendC_THRESH0_VALUE[31] == "0" ? 
+					(iextendC_THRESH0_VALUE[32] == "0" ? (iextendC_THRESH0_VALUE[33] == "0" ? 
+					(iextendC_THRESH0_VALUE[34] == "0" ? (iextendC_THRESH0_VALUE[35] == "0" ? 
+					(iextendC_THRESH0_VALUE[36] == "0" ? (iextendC_THRESH0_VALUE[37] == "0" ? 
+					(iextendC_THRESH0_VALUE[38] == "0" ? (iextendC_THRESH0_VALUE[39] == "0" ? 
+					(iextendC_THRESH0_VALUE[40] == "0" ? (iextendC_THRESH0_VALUE[41] == "0" ? 
+					(iextendC_THRESH0_VALUE[42] == "0" ? (iextendC_THRESH0_VALUE[43] == "0" ? 
+					(iextendC_THRESH0_VALUE[44] == "0" ? (iextendC_THRESH0_VALUE[45] == "0" ? 
+					(iextendC_THRESH0_VALUE[46] == "0" ? (iextendC_THRESH0_VALUE[47] == "0" ? 
+					(iextendC_THRESH0_VALUE[48] == "0" ? (iextendC_THRESH0_VALUE[49] == "0" ? 
+					(iextendC_THRESH0_VALUE[50] == "0" ? (iextendC_THRESH0_VALUE[51] == "0" ? 
+					(iextendC_THRESH0_VALUE[52] == "0" ? (iextendC_THRESH0_VALUE[53] == "0" ? 
+					(iextendC_THRESH0_VALUE[54] == "0" ? (iextendC_THRESH0_VALUE[55] == "0" ? 
+					(iextendC_THRESH0_VALUE[56] == "0" ? (iextendC_THRESH0_VALUE[57] == "0" ? 
+					(iextendC_THRESH0_VALUE[58] == "0" ? (iextendC_THRESH0_VALUE[59] == "0" ? 
+					(iextendC_THRESH0_VALUE[60] == "0" ? (iextendC_THRESH0_VALUE[61] == "0" ? 
+					(iextendC_THRESH0_VALUE[62] == "0" ? (iextendC_THRESH0_VALUE[63] == "0" ? 0
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0));
+	parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == "0" ? (iextendC_THRESH1_VALUE[1] == "0" ? 
+					(iextendC_THRESH1_VALUE[2] == "0" ? (iextendC_THRESH1_VALUE[3] == "0" ? 
+					(iextendC_THRESH1_VALUE[4] == "0" ? (iextendC_THRESH1_VALUE[5] == "0" ? 
+					(iextendC_THRESH1_VALUE[6] == "0" ? (iextendC_THRESH1_VALUE[7] == "0" ? 
+					(iextendC_THRESH1_VALUE[8] == "0" ? (iextendC_THRESH1_VALUE[9] == "0" ? 
+					(iextendC_THRESH1_VALUE[10] == "0" ? (iextendC_THRESH1_VALUE[11] == "0" ? 
+					(iextendC_THRESH1_VALUE[12] == "0" ? (iextendC_THRESH1_VALUE[13] == "0" ? 
+					(iextendC_THRESH1_VALUE[14] == "0" ? (iextendC_THRESH1_VALUE[15] == "0" ? 
+					(iextendC_THRESH1_VALUE[16] == "0" ? (iextendC_THRESH1_VALUE[17] == "0" ? 
+					(iextendC_THRESH1_VALUE[18] == "0" ? (iextendC_THRESH1_VALUE[19] == "0" ? 
+					(iextendC_THRESH1_VALUE[20] == "0" ? (iextendC_THRESH1_VALUE[21] == "0" ? 
+					(iextendC_THRESH1_VALUE[22] == "0" ? (iextendC_THRESH1_VALUE[23] == "0" ? 
+					(iextendC_THRESH1_VALUE[24] == "0" ? (iextendC_THRESH1_VALUE[25] == "0" ? 
+					(iextendC_THRESH1_VALUE[26] == "0" ? (iextendC_THRESH1_VALUE[27] == "0" ? 
+					(iextendC_THRESH1_VALUE[28] == "0" ? (iextendC_THRESH1_VALUE[29] == "0" ? 
+					(iextendC_THRESH1_VALUE[30] == "0" ? (iextendC_THRESH1_VALUE[31] == "0" ? 
+					(iextendC_THRESH1_VALUE[32] == "0" ? (iextendC_THRESH1_VALUE[33] == "0" ? 
+					(iextendC_THRESH1_VALUE[34] == "0" ? (iextendC_THRESH1_VALUE[35] == "0" ? 
+					(iextendC_THRESH1_VALUE[36] == "0" ? (iextendC_THRESH1_VALUE[37] == "0" ? 
+					(iextendC_THRESH1_VALUE[38] == "0" ? (iextendC_THRESH1_VALUE[39] == "0" ? 
+					(iextendC_THRESH1_VALUE[40] == "0" ? (iextendC_THRESH1_VALUE[41] == "0" ? 
+					(iextendC_THRESH1_VALUE[42] == "0" ? (iextendC_THRESH1_VALUE[43] == "0" ? 
+					(iextendC_THRESH1_VALUE[44] == "0" ? (iextendC_THRESH1_VALUE[45] == "0" ? 
+					(iextendC_THRESH1_VALUE[46] == "0" ? (iextendC_THRESH1_VALUE[47] == "0" ? 
+					(iextendC_THRESH1_VALUE[48] == "0" ? (iextendC_THRESH1_VALUE[49] == "0" ? 
+					(iextendC_THRESH1_VALUE[50] == "0" ? (iextendC_THRESH1_VALUE[51] == "0" ? 
+					(iextendC_THRESH1_VALUE[52] == "0" ? (iextendC_THRESH1_VALUE[53] == "0" ? 
+					(iextendC_THRESH1_VALUE[54] == "0" ? (iextendC_THRESH1_VALUE[55] == "0" ? 
+					(iextendC_THRESH1_VALUE[56] == "0" ? (iextendC_THRESH1_VALUE[57] == "0" ? 
+					(iextendC_THRESH1_VALUE[58] == "0" ? (iextendC_THRESH1_VALUE[59] == "0" ? 
+					(iextendC_THRESH1_VALUE[60] == "0" ? (iextendC_THRESH1_VALUE[61] == "0" ? 
+					(iextendC_THRESH1_VALUE[62] == "0" ? (iextendC_THRESH1_VALUE[63] == "0" ? 0
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0));
+	
+	
+	
+			
+
+	input CLK;
+	input UP;
+	input CE;
+	input LOAD;
+	input [C_WIDTH-1 : 0] L;
+	input [C_WIDTH-1 : 0] IV;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output THRESH0;
+	output Q_THRESH0;
+	output THRESH1;
+	output Q_THRESH1;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire intUP;
+	wire intUPbar = ~intUP;
+	wire intCE;
+	wire intLOAD;
+	wire [C_WIDTH-1 : 0] intL;
+	wire [C_WIDTH-1 : 0] intB;
+	wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}};
+	wire intSCLR;
+	wire intCount_to_reached;
+	reg intTHRESH0;
+	reg intTHRESH1;
+	wire intQ_THRESH0;
+	wire intQ_THRESH1;
+	wire [C_WIDTH-1 : 0] intFBq;
+	wire [C_WIDTH-1 : 0] intFBs;
+	wire [C_WIDTH-1 : 0] intQ = intFBq;
+	wire [C_WIDTH-1 : 0] intFBq_or_zero;
+	wire [C_WIDTH-1 : 0] intFBs_or_q;
+	wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY);
+	wire [C_WIDTH-1 : 0] intB_or_load;
+	wire [C_WIDTH-1 : 0] tmpintB_or_load;
+	
+	wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx);
+	wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx);
+	wire [C_WIDTH-1 : 0] Q = intQ;
+	
+	wire [C_WIDTH-1 : 0] intXLOADMUX;
+	wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL);
+	wire [C_WIDTH-1 : 0] intXL;
+	wire intXLOAD;
+	wire intXXLOAD;
+	wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD;
+	
+	// Sort out default values for missing ports
+	
+	assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0));
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}});
+	assign intB = (C_HAS_IV == 1 ? IV : intCount_by);
+	assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL);
+	assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD );
+	assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0));
+	assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0));
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB));
+	assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq);
+	
+	
+	// The addsub on which this is based...
+	
+	C_ADDSUB_V4_0 #(C_COUNT_MODE, 
+					C_AINIT_VAL, 
+					C_OUT_TYPE, 
+					C_WIDTH, 
+					(((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))),
+					C_LOAD_LOW,	// DLUNN CHANGED FROM 0, 
+					0, 
+					C_OUT_TYPE, 
+					"", 
+					C_WIDTH, 
+					C_ENABLE_RLOCS, 
+					C_HAS_ACLR, 
+					C_HAS_UP, 
+					C_HAS_AINIT, 
+					C_HAS_ASET,
+					0, 
+					C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1),	// DLUNN CHANGED FROM 1, 
+					0, 
+					0, 
+					0, 
+					C_HAS_CE, 
+					1, 
+					0, 
+					0, 
+					1, 
+					0, 
+					0, 
+					0, 
+					1, 
+					adder_HAS_SCLR,
+					C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1), 
+					C_HAS_SSET, 
+					C_WIDTH-1,
+			                1,
+					0, 
+					C_WIDTH,
+					C_PIPE_STAGES, 
+					C_SINIT_VAL, 
+					C_SYNC_ENABLE, 
+					C_SYNC_PRIORITY)
+		the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP),
+					.CE(CE), .C_IN(intUPbar), .ACLR(ACLR), .ASET(ASET),
+					.AINIT(AINIT), .SCLR(intSCLR_RESET), .SSET(SSET),
+					.SINIT(SINIT), .BYPASS(intXLOAD), .S(intFBs), .Q(intFBq)); 
+					
+	// The Restrict Count/Sinit LOAD mux
+	
+	C_MUX_BUS_V4_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mxRCSL(.MA(intSINITVAL), .MB(intL), .S(intLOAD), .O(intXLOADMUX));
+			  
+	// The feedback mux
+	
+	C_MUX_BUS_V4_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mxfb(.MA(intFBq), .MB(all_zeros), .S(intXXLOAD), .O(intFBq_or_zero));
+			
+	// The LOAD mux
+	
+	C_MUX_BUS_V4_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mx1(.MA(intB), .MB(intXL), .S(intXXLOAD), .O(tmpintB_or_load));
+			  
+	// The Threshhold comparators
+	
+	C_COMPARE_V4_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, 
+					 C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0,
+					 0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 0, 0, C_WIDTH)
+			th0(.A(intFBs_or_q), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(intSCLR_RESET), .A_EQ_B(THRESH0), .QA_EQ_B(Q_THRESH0));
+				
+	C_COMPARE_V4_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, 
+					 C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1,
+					 0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 0, 0, C_WIDTH)
+			th1(.A(intFBs_or_q), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(intSCLR_RESET), .A_EQ_B(THRESH1), .QA_EQ_B(Q_THRESH1));
+				
+	C_COMPARE_V4_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, 
+					 0, 0, 0, 0, 0, 0, C_HAS_CE, 1,
+					 0, 0, 0, 0, 0, C_HAS_SCLR, 0, 0, 0, 0, C_WIDTH)
+			th_to(.A(intFBs), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(SCLR), .QA_EQ_B(intCount_to_reached));
+				
+	initial 
+	begin
+	
+		#1;
+	
+	
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+
+
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef c_up
+`undef c_down
+`undef c_updown
+`undef allXs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V5_0.v

@@ -0,0 +1,440 @@
+/* $Id: C_COUNTER_BINARY_V5_0.v,v 1.17 2008/09/08 20:05:55 akennedy Exp $
+--
+-- Filename - C_COUNTER_BINARY_V5_0.v
+-- Author - Xilinx
+-- Creation -14 July 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_COUNTER_BINARY_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define c_up 0
+`define c_down 1
+`define c_updown 2
+`define allXs {C_WIDTH{1'bx}}
+
+module C_COUNTER_BINARY_V5_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q);
+
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_COUNT_BY		= "";
+	parameter C_COUNT_MODE		= `c_up;
+	parameter C_COUNT_TO		= "1111111111111111";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 		= 0;
+	parameter C_HAS_IV 		= 0;
+	parameter C_HAS_L 		= 0;
+	parameter C_HAS_LOAD		= 0;
+	parameter C_HAS_Q_THRESH0	= 0;
+	parameter C_HAS_Q_THRESH1	= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HAS_THRESH0		= 0;
+	parameter C_HAS_THRESH1		= 0;
+	parameter C_HAS_UP 		= 0;
+	parameter C_LOAD_ENABLE 	= `c_no_override;
+	parameter C_LOAD_LOW		= 0;
+	parameter C_PIPE_STAGES 	= 0;    
+	parameter C_RESTRICT_COUNT      = 0;
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_THRESH0_VALUE       = "1111111111111111";
+	parameter C_THRESH1_VALUE       = "1111111111111111";
+	parameter C_THRESH_EARLY        = 1;
+	parameter C_WIDTH		= 16;
+
+	parameter C_OUT_TYPE            = `c_signed;
+	parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0);
+	
+	parameter iaxero = {62{"0"}};
+	parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE};
+	parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE};
+	parameter iazero = {64{"0"}};
+	parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == "0" ? (iextendC_THRESH0_VALUE[1] == "0" ? 
+					(iextendC_THRESH0_VALUE[2] == "0" ? (iextendC_THRESH0_VALUE[3] == "0" ? 
+					(iextendC_THRESH0_VALUE[4] == "0" ? (iextendC_THRESH0_VALUE[5] == "0" ? 
+					(iextendC_THRESH0_VALUE[6] == "0" ? (iextendC_THRESH0_VALUE[7] == "0" ? 
+					(iextendC_THRESH0_VALUE[8] == "0" ? (iextendC_THRESH0_VALUE[9] == "0" ? 
+					(iextendC_THRESH0_VALUE[10] == "0" ? (iextendC_THRESH0_VALUE[11] == "0" ? 
+					(iextendC_THRESH0_VALUE[12] == "0" ? (iextendC_THRESH0_VALUE[13] == "0" ? 
+					(iextendC_THRESH0_VALUE[14] == "0" ? (iextendC_THRESH0_VALUE[15] == "0" ? 
+					(iextendC_THRESH0_VALUE[16] == "0" ? (iextendC_THRESH0_VALUE[17] == "0" ? 
+					(iextendC_THRESH0_VALUE[18] == "0" ? (iextendC_THRESH0_VALUE[19] == "0" ? 
+					(iextendC_THRESH0_VALUE[20] == "0" ? (iextendC_THRESH0_VALUE[21] == "0" ? 
+					(iextendC_THRESH0_VALUE[22] == "0" ? (iextendC_THRESH0_VALUE[23] == "0" ? 
+					(iextendC_THRESH0_VALUE[24] == "0" ? (iextendC_THRESH0_VALUE[25] == "0" ? 
+					(iextendC_THRESH0_VALUE[26] == "0" ? (iextendC_THRESH0_VALUE[27] == "0" ? 
+					(iextendC_THRESH0_VALUE[28] == "0" ? (iextendC_THRESH0_VALUE[29] == "0" ? 
+					(iextendC_THRESH0_VALUE[30] == "0" ? (iextendC_THRESH0_VALUE[31] == "0" ? 
+					(iextendC_THRESH0_VALUE[32] == "0" ? (iextendC_THRESH0_VALUE[33] == "0" ? 
+					(iextendC_THRESH0_VALUE[34] == "0" ? (iextendC_THRESH0_VALUE[35] == "0" ? 
+					(iextendC_THRESH0_VALUE[36] == "0" ? (iextendC_THRESH0_VALUE[37] == "0" ? 
+					(iextendC_THRESH0_VALUE[38] == "0" ? (iextendC_THRESH0_VALUE[39] == "0" ? 
+					(iextendC_THRESH0_VALUE[40] == "0" ? (iextendC_THRESH0_VALUE[41] == "0" ? 
+					(iextendC_THRESH0_VALUE[42] == "0" ? (iextendC_THRESH0_VALUE[43] == "0" ? 
+					(iextendC_THRESH0_VALUE[44] == "0" ? (iextendC_THRESH0_VALUE[45] == "0" ? 
+					(iextendC_THRESH0_VALUE[46] == "0" ? (iextendC_THRESH0_VALUE[47] == "0" ? 
+					(iextendC_THRESH0_VALUE[48] == "0" ? (iextendC_THRESH0_VALUE[49] == "0" ? 
+					(iextendC_THRESH0_VALUE[50] == "0" ? (iextendC_THRESH0_VALUE[51] == "0" ? 
+					(iextendC_THRESH0_VALUE[52] == "0" ? (iextendC_THRESH0_VALUE[53] == "0" ? 
+					(iextendC_THRESH0_VALUE[54] == "0" ? (iextendC_THRESH0_VALUE[55] == "0" ? 
+					(iextendC_THRESH0_VALUE[56] == "0" ? (iextendC_THRESH0_VALUE[57] == "0" ? 
+					(iextendC_THRESH0_VALUE[58] == "0" ? (iextendC_THRESH0_VALUE[59] == "0" ? 
+					(iextendC_THRESH0_VALUE[60] == "0" ? (iextendC_THRESH0_VALUE[61] == "0" ? 
+					(iextendC_THRESH0_VALUE[62] == "0" ? (iextendC_THRESH0_VALUE[63] == "0" ? 0
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0));
+	parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == "0" ? (iextendC_THRESH1_VALUE[1] == "0" ? 
+					(iextendC_THRESH1_VALUE[2] == "0" ? (iextendC_THRESH1_VALUE[3] == "0" ? 
+					(iextendC_THRESH1_VALUE[4] == "0" ? (iextendC_THRESH1_VALUE[5] == "0" ? 
+					(iextendC_THRESH1_VALUE[6] == "0" ? (iextendC_THRESH1_VALUE[7] == "0" ? 
+					(iextendC_THRESH1_VALUE[8] == "0" ? (iextendC_THRESH1_VALUE[9] == "0" ? 
+					(iextendC_THRESH1_VALUE[10] == "0" ? (iextendC_THRESH1_VALUE[11] == "0" ? 
+					(iextendC_THRESH1_VALUE[12] == "0" ? (iextendC_THRESH1_VALUE[13] == "0" ? 
+					(iextendC_THRESH1_VALUE[14] == "0" ? (iextendC_THRESH1_VALUE[15] == "0" ? 
+					(iextendC_THRESH1_VALUE[16] == "0" ? (iextendC_THRESH1_VALUE[17] == "0" ? 
+					(iextendC_THRESH1_VALUE[18] == "0" ? (iextendC_THRESH1_VALUE[19] == "0" ? 
+					(iextendC_THRESH1_VALUE[20] == "0" ? (iextendC_THRESH1_VALUE[21] == "0" ? 
+					(iextendC_THRESH1_VALUE[22] == "0" ? (iextendC_THRESH1_VALUE[23] == "0" ? 
+					(iextendC_THRESH1_VALUE[24] == "0" ? (iextendC_THRESH1_VALUE[25] == "0" ? 
+					(iextendC_THRESH1_VALUE[26] == "0" ? (iextendC_THRESH1_VALUE[27] == "0" ? 
+					(iextendC_THRESH1_VALUE[28] == "0" ? (iextendC_THRESH1_VALUE[29] == "0" ? 
+					(iextendC_THRESH1_VALUE[30] == "0" ? (iextendC_THRESH1_VALUE[31] == "0" ? 
+					(iextendC_THRESH1_VALUE[32] == "0" ? (iextendC_THRESH1_VALUE[33] == "0" ? 
+					(iextendC_THRESH1_VALUE[34] == "0" ? (iextendC_THRESH1_VALUE[35] == "0" ? 
+					(iextendC_THRESH1_VALUE[36] == "0" ? (iextendC_THRESH1_VALUE[37] == "0" ? 
+					(iextendC_THRESH1_VALUE[38] == "0" ? (iextendC_THRESH1_VALUE[39] == "0" ? 
+					(iextendC_THRESH1_VALUE[40] == "0" ? (iextendC_THRESH1_VALUE[41] == "0" ? 
+					(iextendC_THRESH1_VALUE[42] == "0" ? (iextendC_THRESH1_VALUE[43] == "0" ? 
+					(iextendC_THRESH1_VALUE[44] == "0" ? (iextendC_THRESH1_VALUE[45] == "0" ? 
+					(iextendC_THRESH1_VALUE[46] == "0" ? (iextendC_THRESH1_VALUE[47] == "0" ? 
+					(iextendC_THRESH1_VALUE[48] == "0" ? (iextendC_THRESH1_VALUE[49] == "0" ? 
+					(iextendC_THRESH1_VALUE[50] == "0" ? (iextendC_THRESH1_VALUE[51] == "0" ? 
+					(iextendC_THRESH1_VALUE[52] == "0" ? (iextendC_THRESH1_VALUE[53] == "0" ? 
+					(iextendC_THRESH1_VALUE[54] == "0" ? (iextendC_THRESH1_VALUE[55] == "0" ? 
+					(iextendC_THRESH1_VALUE[56] == "0" ? (iextendC_THRESH1_VALUE[57] == "0" ? 
+					(iextendC_THRESH1_VALUE[58] == "0" ? (iextendC_THRESH1_VALUE[59] == "0" ? 
+					(iextendC_THRESH1_VALUE[60] == "0" ? (iextendC_THRESH1_VALUE[61] == "0" ? 
+					(iextendC_THRESH1_VALUE[62] == "0" ? (iextendC_THRESH1_VALUE[63] == "0" ? 0
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0));
+	
+	
+	
+			
+
+	input CLK;
+	input UP;
+	input CE;
+	input LOAD;
+	input [C_WIDTH-1 : 0] L;
+	input [C_WIDTH-1 : 0] IV;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output THRESH0;
+	output Q_THRESH0;
+	output THRESH1;
+	output Q_THRESH1;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire intUP;
+	wire intUPbar = ~intUP;
+	wire intCE;
+	wire intLOAD;
+	wire [C_WIDTH-1 : 0] intL;
+	wire [C_WIDTH-1 : 0] intB;
+	wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}};
+	wire intSCLR;
+	wire intCount_to_reached;
+	reg intTHRESH0;
+	reg intTHRESH1;
+	wire intQ_THRESH0;
+	wire intQ_THRESH1;
+	wire [C_WIDTH-1 : 0] intFBq;
+	wire [C_WIDTH-1 : 0] intFBs;
+	wire [C_WIDTH-1 : 0] intQ = intFBq;
+	wire [C_WIDTH-1 : 0] intFBq_or_zero;
+	wire [C_WIDTH-1 : 0] intFBs_or_q;
+	wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY);
+	wire [C_WIDTH-1 : 0] intB_or_load;
+	wire [C_WIDTH-1 : 0] tmpintB_or_load;
+	
+	wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx);
+	wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx);
+	wire [C_WIDTH-1 : 0] Q = intQ;
+	
+	wire [C_WIDTH-1 : 0] intXLOADMUX;
+	wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL);
+	wire [C_WIDTH-1 : 0] intXL;
+	wire intXLOAD;
+	wire intXXLOAD;
+	wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD;
+	
+	// Sort out default values for missing ports
+	
+	assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0));
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}});
+	assign intB = (C_HAS_IV == 1 ? IV : intCount_by);
+	assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL);
+	assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD );
+	assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0));
+	assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0));
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB));
+	assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq);
+	
+	
+	// The addsub on which this is based...
+	
+	C_ADDSUB_V5_0 #(C_COUNT_MODE, 
+					C_AINIT_VAL, 
+					C_OUT_TYPE, 
+					C_WIDTH, 
+					(((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))),
+					C_LOAD_LOW,	// DLUNN CHANGED FROM 0, 
+					0, 
+					C_OUT_TYPE, 
+					"0000000000000000", 
+					C_WIDTH, 
+					C_ENABLE_RLOCS, 
+					C_HAS_ACLR, 
+					C_HAS_UP, 
+					C_HAS_AINIT, 
+					C_HAS_ASET,
+					0, 
+					C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1),	// DLUNN CHANGED FROM 1, 
+					0,
+                    0, 
+					0, 
+					0, 
+					C_HAS_CE, 
+					1, 
+					0, 
+					0, 
+					1, 
+					0, 
+					0, 
+					0, 
+					1, 
+					adder_HAS_SCLR,
+					C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1), 
+					C_HAS_SSET, 
+					C_WIDTH-1,
+			                1,
+					0, 
+					C_WIDTH,
+					C_PIPE_STAGES, 
+					C_SINIT_VAL, 
+					C_SYNC_ENABLE, 
+					C_SYNC_PRIORITY)
+		the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP),
+					.C_IN(intUPbar), .B_IN(), .CE(CE), .BYPASS(intXLOAD),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_RESET), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(), .B_SIGNED(), .OVFL(), .C_OUT(), .B_OUT(),
+					.Q_OVFL(), .Q_C_OUT(), .Q_B_OUT(),
+					.S(intFBs), .Q(intFBq)); 
+					
+	// The Restrict Count/Sinit LOAD mux
+	
+	C_MUX_BUS_V5_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mxRCSL(.MA(intSINITVAL), .MB(intL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(),
+				   .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(),
+				   .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(),
+				   .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(),
+			       .S(intLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(),
+				   .SCLR(), .SSET(), .SINIT(),
+			       .O(intXLOADMUX), .Q());
+			  
+	// The feedback mux
+	
+	C_MUX_BUS_V5_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mxfb(.MA(intFBq), .MB(all_zeros), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(),
+				 .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(),
+				 .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(),
+				 .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(),
+			     .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(),
+				 .SCLR(), .SSET(), .SINIT(),
+			     .O(intFBq_or_zero), .Q());
+			
+	// The LOAD mux
+	
+	C_MUX_BUS_V5_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mx1(.MA(intB), .MB(intXL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(),
+				.MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(),
+				.MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(),
+				.MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(),
+			    .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(),
+				 .SCLR(), .SSET(), .SINIT(),
+			    .O(tmpintB_or_load), .Q());
+			  
+	// The Threshhold comparators
+	
+	C_COMPARE_V5_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, 
+					 C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0,
+					 0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 0, 0, C_WIDTH)
+			th0(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), 
+			    .ACLR(ACLR), .ASET(),
+			    .SCLR(intSCLR_RESET), .SSET(),
+  			    .A_EQ_B(THRESH0), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(),
+  			    .QA_EQ_B(Q_THRESH0), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B());
+				
+	C_COMPARE_V5_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, 
+					 C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1,
+					 0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 0, 0, C_WIDTH)
+			th1(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), 
+			    .ACLR(ACLR), .ASET(),
+			    .SCLR(intSCLR_RESET), .SSET(),
+			    .A_EQ_B(THRESH1), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(),
+			    .QA_EQ_B(Q_THRESH1), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B());
+				
+	C_COMPARE_V5_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, 
+					 0, 0, 0, 0, 0, 0, C_HAS_CE, 1,
+					 0, 0, 0, 0, 0, C_HAS_SCLR, 0, 0, 0, 0, C_WIDTH)
+			th_to(.A(intFBs), .B(), .CLK(CLK), .CE(CE), 
+			.ACLR(ACLR), .ASET(),
+			.SCLR(SCLR), .SSET(),
+			.A_EQ_B(), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(),
+			.QA_EQ_B(intCount_to_reached), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B());
+				
+	initial 
+	begin
+	
+		#1;
+	
+	
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns : non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+
+
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef c_up
+`undef c_down
+`undef c_updown
+`undef allXs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V6_0.v

@@ -0,0 +1,470 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_COUNTER_BINARY_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_COUNTER_BINARY_V6_0.v
+-- Author - Xilinx
+-- Creation -14 July 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_COUNTER_BINARY_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define c_up 0
+`define c_down 1
+`define c_updown 2
+`define allXs {C_WIDTH{1'bx}}
+
+module C_COUNTER_BINARY_V6_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q);
+
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_COUNT_BY		= "";
+	parameter C_COUNT_MODE		= `c_up;
+	parameter C_COUNT_TO		= "1111111111111111";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 		= 0;
+	parameter C_HAS_IV 		= 0;
+	parameter C_HAS_L 		= 0;
+	parameter C_HAS_LOAD		= 0;
+	parameter C_HAS_Q_THRESH0	= 0;
+	parameter C_HAS_Q_THRESH1	= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HAS_THRESH0		= 0;
+	parameter C_HAS_THRESH1		= 0;
+	parameter C_HAS_UP 		= 0;
+	parameter C_LOAD_ENABLE 	= `c_no_override;
+	parameter C_LOAD_LOW		= 0;
+	parameter C_PIPE_STAGES 	= 0;    
+	parameter C_RESTRICT_COUNT      = 0;
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_THRESH0_VALUE       = "1111111111111111";
+	parameter C_THRESH1_VALUE       = "1111111111111111";
+	parameter C_THRESH_EARLY        = 1;
+	parameter C_WIDTH		= 16;
+
+	parameter C_OUT_TYPE            = `c_signed;
+	parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0);
+	
+	parameter iaxero = {62{"0"}};
+	parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE};
+	parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE};
+	parameter iazero = {64{"0"}};
+	parameter TH_TO_HAS_SCLR = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1) ? 1 : 0);
+	parameter TH_TO_HAS_ASET = ((C_HAS_AINIT && (C_AINIT_VAL == C_COUNT_TO)) ? 1 : 0);
+	parameter TH_TO_HAS_ACLR = ((C_HAS_ACLR || (C_HAS_AINIT && (C_AINIT_VAL != C_COUNT_TO))) ? 1 : 0);
+	parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == "0" ? (iextendC_THRESH0_VALUE[1] == "0" ? 
+					(iextendC_THRESH0_VALUE[2] == "0" ? (iextendC_THRESH0_VALUE[3] == "0" ? 
+					(iextendC_THRESH0_VALUE[4] == "0" ? (iextendC_THRESH0_VALUE[5] == "0" ? 
+					(iextendC_THRESH0_VALUE[6] == "0" ? (iextendC_THRESH0_VALUE[7] == "0" ? 
+					(iextendC_THRESH0_VALUE[8] == "0" ? (iextendC_THRESH0_VALUE[9] == "0" ? 
+					(iextendC_THRESH0_VALUE[10] == "0" ? (iextendC_THRESH0_VALUE[11] == "0" ? 
+					(iextendC_THRESH0_VALUE[12] == "0" ? (iextendC_THRESH0_VALUE[13] == "0" ? 
+					(iextendC_THRESH0_VALUE[14] == "0" ? (iextendC_THRESH0_VALUE[15] == "0" ? 
+					(iextendC_THRESH0_VALUE[16] == "0" ? (iextendC_THRESH0_VALUE[17] == "0" ? 
+					(iextendC_THRESH0_VALUE[18] == "0" ? (iextendC_THRESH0_VALUE[19] == "0" ? 
+					(iextendC_THRESH0_VALUE[20] == "0" ? (iextendC_THRESH0_VALUE[21] == "0" ? 
+					(iextendC_THRESH0_VALUE[22] == "0" ? (iextendC_THRESH0_VALUE[23] == "0" ? 
+					(iextendC_THRESH0_VALUE[24] == "0" ? (iextendC_THRESH0_VALUE[25] == "0" ? 
+					(iextendC_THRESH0_VALUE[26] == "0" ? (iextendC_THRESH0_VALUE[27] == "0" ? 
+					(iextendC_THRESH0_VALUE[28] == "0" ? (iextendC_THRESH0_VALUE[29] == "0" ? 
+					(iextendC_THRESH0_VALUE[30] == "0" ? (iextendC_THRESH0_VALUE[31] == "0" ? 
+					(iextendC_THRESH0_VALUE[32] == "0" ? (iextendC_THRESH0_VALUE[33] == "0" ? 
+					(iextendC_THRESH0_VALUE[34] == "0" ? (iextendC_THRESH0_VALUE[35] == "0" ? 
+					(iextendC_THRESH0_VALUE[36] == "0" ? (iextendC_THRESH0_VALUE[37] == "0" ? 
+					(iextendC_THRESH0_VALUE[38] == "0" ? (iextendC_THRESH0_VALUE[39] == "0" ? 
+					(iextendC_THRESH0_VALUE[40] == "0" ? (iextendC_THRESH0_VALUE[41] == "0" ? 
+					(iextendC_THRESH0_VALUE[42] == "0" ? (iextendC_THRESH0_VALUE[43] == "0" ? 
+					(iextendC_THRESH0_VALUE[44] == "0" ? (iextendC_THRESH0_VALUE[45] == "0" ? 
+					(iextendC_THRESH0_VALUE[46] == "0" ? (iextendC_THRESH0_VALUE[47] == "0" ? 
+					(iextendC_THRESH0_VALUE[48] == "0" ? (iextendC_THRESH0_VALUE[49] == "0" ? 
+					(iextendC_THRESH0_VALUE[50] == "0" ? (iextendC_THRESH0_VALUE[51] == "0" ? 
+					(iextendC_THRESH0_VALUE[52] == "0" ? (iextendC_THRESH0_VALUE[53] == "0" ? 
+					(iextendC_THRESH0_VALUE[54] == "0" ? (iextendC_THRESH0_VALUE[55] == "0" ? 
+					(iextendC_THRESH0_VALUE[56] == "0" ? (iextendC_THRESH0_VALUE[57] == "0" ? 
+					(iextendC_THRESH0_VALUE[58] == "0" ? (iextendC_THRESH0_VALUE[59] == "0" ? 
+					(iextendC_THRESH0_VALUE[60] == "0" ? (iextendC_THRESH0_VALUE[61] == "0" ? 
+					(iextendC_THRESH0_VALUE[62] == "0" ? (iextendC_THRESH0_VALUE[63] == "0" ? 0
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0));
+	parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == "0" ? (iextendC_THRESH1_VALUE[1] == "0" ? 
+					(iextendC_THRESH1_VALUE[2] == "0" ? (iextendC_THRESH1_VALUE[3] == "0" ? 
+					(iextendC_THRESH1_VALUE[4] == "0" ? (iextendC_THRESH1_VALUE[5] == "0" ? 
+					(iextendC_THRESH1_VALUE[6] == "0" ? (iextendC_THRESH1_VALUE[7] == "0" ? 
+					(iextendC_THRESH1_VALUE[8] == "0" ? (iextendC_THRESH1_VALUE[9] == "0" ? 
+					(iextendC_THRESH1_VALUE[10] == "0" ? (iextendC_THRESH1_VALUE[11] == "0" ? 
+					(iextendC_THRESH1_VALUE[12] == "0" ? (iextendC_THRESH1_VALUE[13] == "0" ? 
+					(iextendC_THRESH1_VALUE[14] == "0" ? (iextendC_THRESH1_VALUE[15] == "0" ? 
+					(iextendC_THRESH1_VALUE[16] == "0" ? (iextendC_THRESH1_VALUE[17] == "0" ? 
+					(iextendC_THRESH1_VALUE[18] == "0" ? (iextendC_THRESH1_VALUE[19] == "0" ? 
+					(iextendC_THRESH1_VALUE[20] == "0" ? (iextendC_THRESH1_VALUE[21] == "0" ? 
+					(iextendC_THRESH1_VALUE[22] == "0" ? (iextendC_THRESH1_VALUE[23] == "0" ? 
+					(iextendC_THRESH1_VALUE[24] == "0" ? (iextendC_THRESH1_VALUE[25] == "0" ? 
+					(iextendC_THRESH1_VALUE[26] == "0" ? (iextendC_THRESH1_VALUE[27] == "0" ? 
+					(iextendC_THRESH1_VALUE[28] == "0" ? (iextendC_THRESH1_VALUE[29] == "0" ? 
+					(iextendC_THRESH1_VALUE[30] == "0" ? (iextendC_THRESH1_VALUE[31] == "0" ? 
+					(iextendC_THRESH1_VALUE[32] == "0" ? (iextendC_THRESH1_VALUE[33] == "0" ? 
+					(iextendC_THRESH1_VALUE[34] == "0" ? (iextendC_THRESH1_VALUE[35] == "0" ? 
+					(iextendC_THRESH1_VALUE[36] == "0" ? (iextendC_THRESH1_VALUE[37] == "0" ? 
+					(iextendC_THRESH1_VALUE[38] == "0" ? (iextendC_THRESH1_VALUE[39] == "0" ? 
+					(iextendC_THRESH1_VALUE[40] == "0" ? (iextendC_THRESH1_VALUE[41] == "0" ? 
+					(iextendC_THRESH1_VALUE[42] == "0" ? (iextendC_THRESH1_VALUE[43] == "0" ? 
+					(iextendC_THRESH1_VALUE[44] == "0" ? (iextendC_THRESH1_VALUE[45] == "0" ? 
+					(iextendC_THRESH1_VALUE[46] == "0" ? (iextendC_THRESH1_VALUE[47] == "0" ? 
+					(iextendC_THRESH1_VALUE[48] == "0" ? (iextendC_THRESH1_VALUE[49] == "0" ? 
+					(iextendC_THRESH1_VALUE[50] == "0" ? (iextendC_THRESH1_VALUE[51] == "0" ? 
+					(iextendC_THRESH1_VALUE[52] == "0" ? (iextendC_THRESH1_VALUE[53] == "0" ? 
+					(iextendC_THRESH1_VALUE[54] == "0" ? (iextendC_THRESH1_VALUE[55] == "0" ? 
+					(iextendC_THRESH1_VALUE[56] == "0" ? (iextendC_THRESH1_VALUE[57] == "0" ? 
+					(iextendC_THRESH1_VALUE[58] == "0" ? (iextendC_THRESH1_VALUE[59] == "0" ? 
+					(iextendC_THRESH1_VALUE[60] == "0" ? (iextendC_THRESH1_VALUE[61] == "0" ? 
+					(iextendC_THRESH1_VALUE[62] == "0" ? (iextendC_THRESH1_VALUE[63] == "0" ? 0
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0));
+	
+	
+	
+			
+
+	input CLK;
+	input UP;
+	input CE;
+	input LOAD;
+	input [C_WIDTH-1 : 0] L;
+	input [C_WIDTH-1 : 0] IV;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output THRESH0;
+	output Q_THRESH0;
+	output THRESH1;
+	output Q_THRESH1;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire intUP;
+	wire intUPbar = ~intUP;
+	wire intCE;
+	wire intLOAD;
+	wire [C_WIDTH-1 : 0] intL;
+	wire [C_WIDTH-1 : 0] intB;
+	wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}};
+	wire intSCLR;
+	wire intCount_to_reached;
+	reg intTHRESH0;
+	reg intTHRESH1;
+	wire intQ_THRESH0;
+	wire intQ_THRESH1;
+	wire [C_WIDTH-1 : 0] intFBq;
+	wire [C_WIDTH-1 : 0] intFBs;
+	wire [C_WIDTH-1 : 0] intQ = intFBq;
+	wire [C_WIDTH-1 : 0] intFBq_or_zero;
+	wire [C_WIDTH-1 : 0] intFBs_or_q;
+	wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY);
+	wire [C_WIDTH-1 : 0] intB_or_load;
+	wire [C_WIDTH-1 : 0] tmpintB_or_load;
+	
+	wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx);
+	wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx);
+	wire [C_WIDTH-1 : 0] Q = intQ;
+	
+	wire [C_WIDTH-1 : 0] intXLOADMUX;
+	wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL);
+	wire [C_WIDTH-1 : 0] intXL;
+	wire intXLOAD;
+	wire intXXLOAD;
+	wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD;
+	wire #5 intSCLR_RESET_for_thresh = intSCLR; //((intSCLR && intCE) || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD;
+
+    wire intSCLR_for_th_to;
+	wire ACLR_for_th_to;
+	wire ASET_for_th_to;
+	
+	// Sort out default values for missing ports
+	
+	assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0));
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}});
+	assign intB = (C_HAS_IV == 1 ? IV : intCount_by);
+	assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL);
+	assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD );
+	assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0));
+	assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0));
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB));
+	assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq);
+
+    assign intSCLR_for_th_to = ((C_HAS_SCLR == 1 && C_HAS_SSET == 1) ? (SCLR | SSET) :
+	                            (C_HAS_SCLR == 1 && C_HAS_SSET == 0) ? SCLR :
+								(C_HAS_SCLR == 0 && C_HAS_SSET == 1) ? SSET :
+								0);
+    assign ACLR_for_th_to = ((C_HAS_ACLR == 1 && (C_HAS_AINIT == 1 && C_COUNT_TO != C_AINIT_VAL)) 
+                          ? (ACLR | AINIT) 
+	                      : ((C_HAS_AINIT == 1 && C_COUNT_TO != C_AINIT_VAL) 
+						  ? AINIT 
+						  : (C_HAS_ACLR == 1 ? ACLR : 0)));
+	assign ASET_for_th_to = ((C_HAS_AINIT == 1 && C_COUNT_TO == C_AINIT_VAL) 
+                          ? AINIT 
+	                      : 0);
+	
+	
+	// The addsub on which this is based...
+	
+	C_ADDSUB_V6_0 #(C_COUNT_MODE, 
+					C_AINIT_VAL, 
+					C_OUT_TYPE, 
+					C_WIDTH, 
+					(((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))),
+					C_LOAD_LOW,	// DLUNN CHANGED FROM 0, 
+					0, 
+					C_OUT_TYPE, 
+					"0000000000000000", 
+					C_WIDTH, 
+					C_ENABLE_RLOCS, 
+					C_HAS_ACLR, 
+					C_HAS_UP, 
+					C_HAS_AINIT, 
+					C_HAS_ASET,
+					0, 
+					C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1),	// DLUNN CHANGED FROM 1, 
+					0,
+                    0, 
+					0, 
+					0, 
+					C_HAS_CE, 
+					1, 
+					0, 
+					0, 
+					1, 
+					0, 
+					0, 
+					0, 
+					1, 
+					adder_HAS_SCLR,
+					C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1), 
+					C_HAS_SSET, 
+					C_WIDTH-1,
+			                1,
+					0, 
+					C_WIDTH,
+					C_PIPE_STAGES, 
+					C_SINIT_VAL, 
+					C_SYNC_ENABLE, 
+					C_SYNC_PRIORITY)
+		the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP),
+					.C_IN(intUPbar), .B_IN(), .CE(CE), .BYPASS(intXLOAD),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_RESET), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(), .B_SIGNED(), .OVFL(), .C_OUT(), .B_OUT(),
+					.Q_OVFL(), .Q_C_OUT(), .Q_B_OUT(),
+					.S(intFBs), .Q(intFBq)); 
+					
+	// The Restrict Count/Sinit LOAD mux
+	
+	C_MUX_BUS_V6_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mxRCSL(.MA(intSINITVAL), .MB(intL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(),
+				   .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(),
+				   .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(),
+				   .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(),
+			       .S(intLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(),
+				   .SCLR(), .SSET(), .SINIT(),
+			       .O(intXLOADMUX), .Q());
+			  
+	// The feedback mux
+	
+	C_MUX_BUS_V6_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mxfb(.MA(intFBq), .MB(all_zeros), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(),
+				 .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(),
+				 .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(),
+				 .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(),
+			     .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(),
+				 .SCLR(), .SSET(), .SINIT(),
+			     .O(intFBq_or_zero), .Q());
+			
+	// The LOAD mux
+	
+	C_MUX_BUS_V6_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mx1(.MA(intB), .MB(intXL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(),
+				.MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(),
+				.MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(),
+				.MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(),
+			    .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(),
+				 .SCLR(), .SSET(), .SINIT(),
+			    .O(tmpintB_or_load), .Q());
+			  
+	// The Threshhold comparators
+	
+	C_COMPARE_V6_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, 
+					 C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0,
+					 0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 1, 0, C_WIDTH)
+			th0(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), 
+			    .ACLR(ACLR), .ASET(),
+			    .SCLR(intSCLR_RESET_for_thresh), .SSET(),
+  			    .A_EQ_B(THRESH0), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(),
+  			    .QA_EQ_B(Q_THRESH0), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B());
+				
+	C_COMPARE_V6_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, 
+					 C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1,
+					 0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 1, 0, C_WIDTH)
+			th1(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), 
+			    .ACLR(ACLR), .ASET(),
+			    .SCLR(intSCLR_RESET_for_thresh), .SSET(),
+			    .A_EQ_B(THRESH1), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(),
+			    .QA_EQ_B(Q_THRESH1), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B());
+				
+	C_COMPARE_V6_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, TH_TO_HAS_ACLR, TH_TO_HAS_ASET, 
+					 0, 0, 0, 0, 0, 0, C_HAS_CE, 1,
+					 0, 0, 0, 0, 0, TH_TO_HAS_SCLR, 0, 0, C_SYNC_ENABLE, 0, C_WIDTH)
+			th_to(.A(intFBs), .B(), .CLK(CLK), .CE(CE), 
+			.ACLR(ACLR_for_th_to), .ASET(ASET_for_th_to),
+			.SCLR(intSCLR_for_th_to), .SSET(),
+			.A_EQ_B(), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(),
+			.QA_EQ_B(intCount_to_reached), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B());
+				
+	initial 
+	begin
+	
+		#1;
+	
+	
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns : non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+
+
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef c_up
+`undef c_down
+`undef c_updown
+`undef allXs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V7_0.v

@@ -0,0 +1,501 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Id: C_COUNTER_BINARY_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_COUNTER_BINARY_V7_0.v
+-- Author - Xilinx
+-- Creation -14 July 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_COUNTER_BINARY_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_signed 0
+`define c_unsigned 1
+`define c_pin 2
+`define c_up 0
+`define c_down 1
+`define c_updown 2
+`define allXs {C_WIDTH{1'bx}}
+
+module C_COUNTER_BINARY_V7_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q);
+
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_COUNT_BY		= "";
+	parameter C_COUNT_MODE		= `c_up;
+	parameter C_COUNT_TO		= "1111111111111111";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 		= 0;
+	parameter C_HAS_IV 		= 0;
+	parameter C_HAS_L 		= 0;
+	parameter C_HAS_LOAD		= 0;
+	parameter C_HAS_Q_THRESH0	= 0;
+	parameter C_HAS_Q_THRESH1	= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HAS_THRESH0		= 0;
+	parameter C_HAS_THRESH1		= 0;
+	parameter C_HAS_UP 		= 0;
+	parameter C_LOAD_ENABLE 	= `c_no_override;
+	parameter C_LOAD_LOW		= 0;
+	parameter C_PIPE_STAGES 	= 0;    
+	parameter C_RESTRICT_COUNT      = 0;
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_THRESH0_VALUE       = "1111111111111111";
+	parameter C_THRESH1_VALUE       = "1111111111111111";
+	parameter C_THRESH_EARLY        = 1;
+	parameter C_WIDTH		= 16;
+
+
+
+	parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0);
+	
+	parameter iaxero = {62{"0"}};
+	parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE};
+	parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE};
+	parameter iazero = {64{"0"}};
+	parameter TH_TO_HAS_SCLR = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1) ? 1 : 0);
+	parameter TH_TO_HAS_ASET = ((C_HAS_AINIT && (C_AINIT_VAL == C_COUNT_TO)) ? 1 : 0);
+	parameter TH_TO_HAS_ACLR = ((C_HAS_ACLR || (C_HAS_AINIT && (C_AINIT_VAL != C_COUNT_TO))) ? 1 : 0);
+	parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == 0 ? (iextendC_THRESH0_VALUE[1] == 0 ? 
+					(iextendC_THRESH0_VALUE[2] == 0 ? (iextendC_THRESH0_VALUE[3] == 0 ? 
+					(iextendC_THRESH0_VALUE[4] == 0 ? (iextendC_THRESH0_VALUE[5] == 0 ? 
+					(iextendC_THRESH0_VALUE[6] == 0 ? (iextendC_THRESH0_VALUE[7] == 0 ? 
+					(iextendC_THRESH0_VALUE[8] == 0 ? (iextendC_THRESH0_VALUE[9] == 0 ? 
+					(iextendC_THRESH0_VALUE[10] == 0 ? (iextendC_THRESH0_VALUE[11] == 0 ? 
+					(iextendC_THRESH0_VALUE[12] == 0 ? (iextendC_THRESH0_VALUE[13] == 0 ? 
+					(iextendC_THRESH0_VALUE[14] == 0 ? (iextendC_THRESH0_VALUE[15] == 0 ? 
+					(iextendC_THRESH0_VALUE[16] == 0 ? (iextendC_THRESH0_VALUE[17] == 0 ? 
+					(iextendC_THRESH0_VALUE[18] == 0 ? (iextendC_THRESH0_VALUE[19] == 0 ? 
+					(iextendC_THRESH0_VALUE[20] == 0 ? (iextendC_THRESH0_VALUE[21] == 0 ? 
+					(iextendC_THRESH0_VALUE[22] == 0 ? (iextendC_THRESH0_VALUE[23] == 0 ? 
+					(iextendC_THRESH0_VALUE[24] == 0 ? (iextendC_THRESH0_VALUE[25] == 0 ? 
+					(iextendC_THRESH0_VALUE[26] == 0 ? (iextendC_THRESH0_VALUE[27] == 0 ? 
+					(iextendC_THRESH0_VALUE[28] == 0 ? (iextendC_THRESH0_VALUE[29] == 0 ? 
+					(iextendC_THRESH0_VALUE[30] == 0 ? (iextendC_THRESH0_VALUE[31] == 0 ? 
+					(iextendC_THRESH0_VALUE[32] == 0 ? (iextendC_THRESH0_VALUE[33] == 0 ? 
+					(iextendC_THRESH0_VALUE[34] == 0 ? (iextendC_THRESH0_VALUE[35] == 0 ? 
+					(iextendC_THRESH0_VALUE[36] == 0 ? (iextendC_THRESH0_VALUE[37] == 0 ? 
+					(iextendC_THRESH0_VALUE[38] == 0 ? (iextendC_THRESH0_VALUE[39] == 0 ? 
+					(iextendC_THRESH0_VALUE[40] == 0 ? (iextendC_THRESH0_VALUE[41] == 0 ? 
+					(iextendC_THRESH0_VALUE[42] == 0 ? (iextendC_THRESH0_VALUE[43] == 0 ? 
+					(iextendC_THRESH0_VALUE[44] == 0 ? (iextendC_THRESH0_VALUE[45] == 0 ? 
+					(iextendC_THRESH0_VALUE[46] == 0 ? (iextendC_THRESH0_VALUE[47] == 0 ? 
+					(iextendC_THRESH0_VALUE[48] == 0 ? (iextendC_THRESH0_VALUE[49] == 0 ? 
+					(iextendC_THRESH0_VALUE[50] == 0 ? (iextendC_THRESH0_VALUE[51] == 0 ? 
+					(iextendC_THRESH0_VALUE[52] == 0 ? (iextendC_THRESH0_VALUE[53] == 0 ? 
+					(iextendC_THRESH0_VALUE[54] == 0 ? (iextendC_THRESH0_VALUE[55] == 0 ? 
+					(iextendC_THRESH0_VALUE[56] == 0 ? (iextendC_THRESH0_VALUE[57] == 0 ? 
+					(iextendC_THRESH0_VALUE[58] == 0 ? (iextendC_THRESH0_VALUE[59] == 0 ? 
+					(iextendC_THRESH0_VALUE[60] == 0 ? (iextendC_THRESH0_VALUE[61] == 0 ? 
+					(iextendC_THRESH0_VALUE[62] == 0 ? (iextendC_THRESH0_VALUE[63] == 0 ? 0
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0));
+	parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == 0 ? (iextendC_THRESH1_VALUE[1] == 0 ? 
+					(iextendC_THRESH1_VALUE[2] == 0 ? (iextendC_THRESH1_VALUE[3] == 0 ? 
+					(iextendC_THRESH1_VALUE[4] == 0 ? (iextendC_THRESH1_VALUE[5] == 0 ? 
+					(iextendC_THRESH1_VALUE[6] == 0 ? (iextendC_THRESH1_VALUE[7] == 0 ? 
+					(iextendC_THRESH1_VALUE[8] == 0 ? (iextendC_THRESH1_VALUE[9] == 0 ? 
+					(iextendC_THRESH1_VALUE[10] == 0 ? (iextendC_THRESH1_VALUE[11] == 0 ? 
+					(iextendC_THRESH1_VALUE[12] == 0 ? (iextendC_THRESH1_VALUE[13] == 0 ? 
+					(iextendC_THRESH1_VALUE[14] == 0 ? (iextendC_THRESH1_VALUE[15] == 0 ? 
+					(iextendC_THRESH1_VALUE[16] == 0 ? (iextendC_THRESH1_VALUE[17] == 0 ? 
+					(iextendC_THRESH1_VALUE[18] == 0 ? (iextendC_THRESH1_VALUE[19] == 0 ? 
+					(iextendC_THRESH1_VALUE[20] == 0 ? (iextendC_THRESH1_VALUE[21] == 0 ? 
+					(iextendC_THRESH1_VALUE[22] == 0 ? (iextendC_THRESH1_VALUE[23] == 0 ? 
+					(iextendC_THRESH1_VALUE[24] == 0 ? (iextendC_THRESH1_VALUE[25] == 0 ? 
+					(iextendC_THRESH1_VALUE[26] == 0 ? (iextendC_THRESH1_VALUE[27] == 0 ? 
+					(iextendC_THRESH1_VALUE[28] == 0 ? (iextendC_THRESH1_VALUE[29] == 0 ? 
+					(iextendC_THRESH1_VALUE[30] == 0 ? (iextendC_THRESH1_VALUE[31] == 0 ? 
+					(iextendC_THRESH1_VALUE[32] == 0 ? (iextendC_THRESH1_VALUE[33] == 0 ? 
+					(iextendC_THRESH1_VALUE[34] == 0 ? (iextendC_THRESH1_VALUE[35] == 0 ? 
+					(iextendC_THRESH1_VALUE[36] == 0 ? (iextendC_THRESH1_VALUE[37] == 0 ? 
+					(iextendC_THRESH1_VALUE[38] == 0 ? (iextendC_THRESH1_VALUE[39] == 0 ? 
+					(iextendC_THRESH1_VALUE[40] == 0 ? (iextendC_THRESH1_VALUE[41] == 0 ? 
+					(iextendC_THRESH1_VALUE[42] == 0 ? (iextendC_THRESH1_VALUE[43] == 0 ? 
+					(iextendC_THRESH1_VALUE[44] == 0 ? (iextendC_THRESH1_VALUE[45] == 0 ? 
+					(iextendC_THRESH1_VALUE[46] == 0 ? (iextendC_THRESH1_VALUE[47] == 0 ? 
+					(iextendC_THRESH1_VALUE[48] == 0 ? (iextendC_THRESH1_VALUE[49] == 0 ? 
+					(iextendC_THRESH1_VALUE[50] == 0 ? (iextendC_THRESH1_VALUE[51] == 0 ? 
+					(iextendC_THRESH1_VALUE[52] == 0 ? (iextendC_THRESH1_VALUE[53] == 0 ? 
+					(iextendC_THRESH1_VALUE[54] == 0 ? (iextendC_THRESH1_VALUE[55] == 0 ? 
+					(iextendC_THRESH1_VALUE[56] == 0 ? (iextendC_THRESH1_VALUE[57] == 0 ? 
+					(iextendC_THRESH1_VALUE[58] == 0 ? (iextendC_THRESH1_VALUE[59] == 0 ? 
+					(iextendC_THRESH1_VALUE[60] == 0 ? (iextendC_THRESH1_VALUE[61] == 0 ? 
+					(iextendC_THRESH1_VALUE[62] == 0 ? (iextendC_THRESH1_VALUE[63] == 0 ? 0
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
+					: (C_HAS_SCLR == 1 ? 1 : 0));
+	parameter C_OUT_TYPE            = `c_signed;
+	
+	
+	
+			
+
+	input CLK;
+	input UP;
+	input CE;
+	input LOAD;
+	input [C_WIDTH-1 : 0] L;
+	input [C_WIDTH-1 : 0] IV;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output THRESH0;
+	output Q_THRESH0;
+	output THRESH1;
+	output Q_THRESH1;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire intUP;
+	wire intUPbar = ~intUP;
+	wire intCE;
+	wire intLOAD;
+	wire [C_WIDTH-1 : 0] intL;
+	wire [C_WIDTH-1 : 0] intB;
+	wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}};
+	wire intSCLR;
+	wire intCount_to_reached;
+	reg intTHRESH0;
+	reg intTHRESH1;
+	wire intQ_THRESH0;
+	wire intQ_THRESH1;
+	wire [C_WIDTH-1 : 0] intFBq;
+	wire [C_WIDTH-1 : 0] intFBs;
+	wire [C_WIDTH-1 : 0] intQ = intFBq;
+	wire [C_WIDTH-1 : 0] intFBq_or_zero;
+	wire [C_WIDTH-1 : 0] intFBs_or_q;
+	wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY);
+	wire [C_WIDTH-1 : 0] intB_or_load;
+	wire [C_WIDTH-1 : 0] tmpintB_or_load;
+	
+	wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx);
+	wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx);
+	wire [C_WIDTH-1 : 0] Q = intQ;
+	
+	wire [C_WIDTH-1 : 0] intXLOADMUX;
+	wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL);
+	wire [C_WIDTH-1 : 0] intXL;
+	wire intXLOAD;
+	wire intXXLOAD;
+	wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD;
+	wire #5 intSCLR_RESET_for_thresh = intSCLR; //((intSCLR && intCE) || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD;
+
+    wire intSCLR_for_th_to;
+	wire ACLR_for_th_to;
+	wire ASET_for_th_to;
+	
+	// Sort out default values for missing ports
+	
+	assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0));
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}});
+	assign intB = (C_HAS_IV == 1 ? IV : intCount_by);
+	assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL);
+	assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD );
+	assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0));
+	assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0));
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB));
+	assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq);
+
+    assign intSCLR_for_th_to = ((C_HAS_SCLR == 1 && C_HAS_SSET == 1) ? (SCLR | SSET) :
+	                            (C_HAS_SCLR == 1 && C_HAS_SSET == 0) ? SCLR :
+								(C_HAS_SCLR == 0 && C_HAS_SSET == 1) ? SSET :
+								0);
+    assign ACLR_for_th_to = ((C_HAS_ACLR == 1 && (C_HAS_AINIT == 1 && C_COUNT_TO != C_AINIT_VAL)) 
+                          ? (ACLR | AINIT) 
+	                      : ((C_HAS_AINIT == 1 && C_COUNT_TO != C_AINIT_VAL) 
+						  ? AINIT 
+						  : (C_HAS_ACLR == 1 ? ACLR : 0)));
+	assign ASET_for_th_to = ((C_HAS_AINIT == 1 && C_COUNT_TO == C_AINIT_VAL) 
+                          ? AINIT 
+	                      : 0);
+	
+	
+	// The addsub on which this is based...
+	
+	C_ADDSUB_V7_0 #(C_COUNT_MODE, 
+					C_AINIT_VAL, 
+					C_OUT_TYPE, 
+					C_WIDTH, 
+					(((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))),
+					C_LOAD_LOW,	// DLUNN CHANGED FROM 0, 
+					0, 
+					C_OUT_TYPE, 
+					"0000000000000000", 
+					C_WIDTH, 
+					C_ENABLE_RLOCS, 
+					C_HAS_ACLR, 
+					C_HAS_UP, 
+					C_HAS_AINIT, 
+					C_HAS_ASET,
+					0, 
+					C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1),	// DLUNN CHANGED FROM 1, 
+					0,
+                    0, 
+					0, 
+					0, 
+					C_HAS_CE, 
+					1, 
+					0, 
+					0, 
+					1, 
+					0, 
+					0, 
+					0, 
+					1, 
+					adder_HAS_SCLR,
+					C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1), 
+					C_HAS_SSET, 
+					C_WIDTH-1,
+			                1,
+					0, 
+					C_WIDTH,
+					C_PIPE_STAGES, 
+					C_SINIT_VAL, 
+					C_SYNC_ENABLE, 
+					C_SYNC_PRIORITY)
+		the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP),
+					.C_IN(intUPbar), .B_IN(), .CE(CE), .BYPASS(intXLOAD),
+					.ACLR(ACLR), .ASET(ASET), .AINIT(AINIT),
+					.SCLR(intSCLR_RESET), .SSET(SSET), .SINIT(SINIT),
+					.A_SIGNED(), .B_SIGNED(), .OVFL(), .C_OUT(), .B_OUT(),
+					.Q_OVFL(), .Q_C_OUT(), .Q_B_OUT(),
+					.S(intFBs), .Q(intFBq)); 
+					
+	// The Restrict Count/Sinit LOAD mux
+	
+	C_MUX_BUS_V7_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mxRCSL(.MA(intSINITVAL), .MB(intL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(),
+				   .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(),
+				   .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(),
+				   .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(),
+			       .S(intLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(),
+				   .SCLR(), .SSET(), .SINIT(),
+			       .O(intXLOADMUX), .Q());
+			  
+	// The feedback mux
+	
+	C_MUX_BUS_V7_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mxfb(.MA(intFBq), .MB(all_zeros), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(),
+				 .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(),
+				 .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(),
+				 .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(),
+			     .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(),
+				 .SCLR(), .SSET(), .SINIT(),
+			     .O(intFBq_or_zero), .Q());
+			
+	// The LOAD mux
+	
+	C_MUX_BUS_V7_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, 
+					 0, 0, 1, "", 0, 0, C_WIDTH)
+			mx1(.MA(intB), .MB(intXL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(),
+				.MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(),
+				.MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(),
+				.MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(),
+			    .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(),
+				 .SCLR(), .SSET(), .SINIT(),
+			    .O(tmpintB_or_load), .Q());
+			  
+	// The Threshhold comparators
+	
+	C_COMPARE_V7_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, 
+					 C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0,
+					 0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 1, 0, C_WIDTH)
+			th0(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), 
+			    .ACLR(ACLR), .ASET(),
+			    .SCLR(intSCLR_RESET_for_thresh), .SSET(),
+  			    .A_EQ_B(THRESH0), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(),
+  			    .QA_EQ_B(Q_THRESH0), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B());
+				
+	C_COMPARE_V7_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, 
+					 C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1,
+					 0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 1, 0, C_WIDTH)
+			th1(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), 
+			    .ACLR(ACLR), .ASET(),
+			    .SCLR(intSCLR_RESET_for_thresh), .SSET(),
+			    .A_EQ_B(THRESH1), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(),
+			    .QA_EQ_B(Q_THRESH1), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B());
+				
+	C_COMPARE_V7_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, TH_TO_HAS_ACLR, TH_TO_HAS_ASET, 
+					 0, 0, 0, 0, 0, 0, C_HAS_CE, 1,
+					 0, 0, 0, 0, 0, TH_TO_HAS_SCLR, 0, 0, C_SYNC_ENABLE, 0, C_WIDTH)
+			th_to(.A(intFBs), .B(), .CLK(CLK), .CE(CE), 
+			.ACLR(ACLR_for_th_to), .ASET(ASET_for_th_to),
+			.SCLR(intSCLR_for_th_to), .SSET(),
+			.A_EQ_B(), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(),
+			.QA_EQ_B(intCount_to_reached), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B());
+				
+	initial 
+	begin
+	
+		#1;
+	
+	
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns : non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+
+
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_signed
+`undef c_unsigned
+`undef c_pin
+`undef c_up
+`undef c_down
+`undef c_updown
+`undef allXs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DECODE_BINARY_V4_0.v

@@ -0,0 +1,240 @@
+/* $Id: C_DECODE_BINARY_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_DECODE_BINARY_V4_0.v
+-- Author - Xilinx
+-- Creation - 21 May 1999
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_DECODE_BINARY_V4_0 module
+*/
+
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define alldb1s {C_OUT_WIDTH{1'b1}}
+`define all0s 'b0
+`define alldbXs {C_OUT_WIDTH{1'bx}}
+
+module C_DECODE_BINARY_V4_0 (CLK, EN, CE, S, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_EN			= 0;
+	parameter C_HAS_O			= 0;
+	parameter C_HAS_Q			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_OUT_HIGH		= 1;
+	parameter C_OUT_WIDTH 		= 8;
+	parameter C_PIPE_STAGES		= 1;
+	parameter C_SEL_WIDTH		= 3;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input EN;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_OUT_WIDTH-1 : 0] O;
+	output [C_OUT_WIDTH-1 : 0] Q;
+	 
+	reg [C_OUT_WIDTH-1 : 0] data;
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	wire intEN;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	reg [C_OUT_WIDTH-1 : 0] intO;
+	reg [C_OUT_WIDTH-1 : 0] tmpO;
+	wire [C_OUT_WIDTH-1 : 0] intQ;
+	 
+	reg [C_OUT_WIDTH-1 : 0] intQpipe [C_PIPE_STAGES+2 : 0];
+	reg [C_OUT_WIDTH-1 : 0] intQpipeend;
+	reg [C_OUT_WIDTH : 0] tmp_pipe1;
+	reg [C_OUT_WIDTH : 0] tmp_pipe2;
+
+	wire [C_OUT_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `alldbXs);
+	wire [C_OUT_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `alldbXs);
+	reg lastCLK;
+
+	// Sort out default values for missing ports
+	
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intEN = defval(EN, C_HAS_EN, 1);
+
+	integer i, j, k;
+	integer m, unknown;
+	integer pipe, pipe1;
+	
+	// Register on output by default
+	C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_OUT_WIDTH)
+		reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+		for(j = 0; j <= C_PIPE_STAGES - 1; j = j + 1)
+			intQpipe[j] = 'b0;
+		i = 0;
+		k = 1;
+		unknown = 0;
+
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1'b1)
+				i = i + k;
+			else if(S[j] === 1'bx || S[j] === 1'bz)
+				unknown = 1;
+			k = k * 2;	
+		end
+		
+		if(unknown == 1 && intEN === 1'b1)
+			tmpO = `alldbXs;
+		else if(C_OUT_HIGH === 1'b1)
+		begin
+			tmpO = `all0s;	
+			tmpO[i] = intEN;
+		end
+		else if(C_OUT_HIGH === 1'b0)
+		begin
+			tmpO = `alldb1s;
+			tmpO[i] = ~(intEN);
+		end
+		else // C_OUT_HIGH unknown
+			tmpO = `alldbXs;
+
+		intO <= #1 tmpO;
+		
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend = intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend = intQpipe[2];
+		end
+	end
+
+	always @(CLK)
+  		lastCLK <= CLK;
+
+	always@(S or intEN)
+	begin
+		i = 0;
+		k = 1;
+		unknown = 0;
+
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1'b1)
+				i = i + k;
+			else if(S[j] === 1'bx || S[j] === 1'bz)
+				unknown = 1;
+			k = k * 2;	
+		end
+		
+		if(unknown == 1 && intEN === 1'b1)
+			tmpO = `alldbXs;
+		else if(C_OUT_HIGH === 1'b1)
+		begin
+			tmpO = `all0s;	
+			tmpO[i] = intEN;
+		end
+		else if(C_OUT_HIGH === 1'b0)
+		begin
+			tmpO = `alldb1s;
+			tmpO[i] = ~(intEN);
+		end
+		else // C_OUT_HIGH unknown
+			tmpO = `alldbXs;
+
+		intO <= #1 tmpO;
+	end		
+
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				intQpipe[pipe] <= intQpipe[pipe+1];
+			end
+			intQpipe[C_PIPE_STAGES] <= intO;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				tmp_pipe1 = intQpipe[pipe];
+				tmp_pipe2 = intQpipe[pipe+1];
+				for(pipe1 = 0; pipe1 < C_OUT_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				intQpipe[pipe] <= tmp_pipe1;
+			end
+			tmp_pipe1 = intQpipe[C_PIPE_STAGES];
+			for(pipe1 = 0; pipe1 < C_OUT_WIDTH; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== intO[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			intQpipe[C_PIPE_STAGES] <= tmp_pipe1;
+		end
+	end
+	
+	always@(intO or intQpipe[2])
+	begin
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend <= intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend <= intQpipe[2];
+		end
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+
+endmodule	
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef alldb1s
+`undef all0s
+`undef alldbXs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DECODE_BINARY_V5_0.v

@@ -0,0 +1,240 @@
+/* $Id: C_DECODE_BINARY_V5_0.v,v 1.17 2008/09/08 20:05:55 akennedy Exp $
+--
+-- Filename - C_DECODE_BINARY_V5_0.v
+-- Author - Xilinx
+-- Creation - 21 May 1999
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_DECODE_BINARY_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define alldb1s {C_OUT_WIDTH{1'b1}}
+`define all0s 'b0
+`define alldbXs {C_OUT_WIDTH{1'bx}}
+
+module C_DECODE_BINARY_V5_0 (CLK, EN, CE, S, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_EN			= 0;
+	parameter C_HAS_O			= 0;
+	parameter C_HAS_Q			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_OUT_HIGH		= 1;
+	parameter C_OUT_WIDTH 		= 8;
+	parameter C_PIPE_STAGES		= 1;
+	parameter C_SEL_WIDTH		= 3;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input EN;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_OUT_WIDTH-1 : 0] O;
+	output [C_OUT_WIDTH-1 : 0] Q;
+	 
+	reg [C_OUT_WIDTH-1 : 0] data;
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	wire intEN;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	reg [C_OUT_WIDTH-1 : 0] intO;
+	reg [C_OUT_WIDTH-1 : 0] tmpO;
+	wire [C_OUT_WIDTH-1 : 0] intQ;
+	 
+	reg [C_OUT_WIDTH-1 : 0] intQpipe [C_PIPE_STAGES+2 : 0];
+	reg [C_OUT_WIDTH-1 : 0] intQpipeend;
+	reg [C_OUT_WIDTH : 0] tmp_pipe1;
+	reg [C_OUT_WIDTH : 0] tmp_pipe2;
+
+	wire [C_OUT_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `alldbXs);
+	wire [C_OUT_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `alldbXs);
+	reg lastCLK;
+
+	// Sort out default values for missing ports
+	
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intEN = defval(EN, C_HAS_EN, 1);
+
+	integer i, j, k;
+	integer m, unknown;
+	integer pipe, pipe1;
+	
+	// Register on output by default
+	C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_OUT_WIDTH)
+		reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+		for(j = 0; j <= C_PIPE_STAGES - 1; j = j + 1)
+			intQpipe[j] = 'b0;
+		i = 0;
+		k = 1;
+		unknown = 0;
+
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1'b1)
+				i = i + k;
+			else if(S[j] === 1'bx || S[j] === 1'bz)
+				unknown = 1;
+			k = k * 2;	
+		end
+		
+		if(unknown == 1 && intEN === 1'b1)
+			tmpO = `alldbXs;
+		else if(C_OUT_HIGH === 1'b1)
+		begin
+			tmpO = `all0s;	
+			tmpO[i] = intEN;
+		end
+		else if(C_OUT_HIGH === 1'b0)
+		begin
+			tmpO = `alldb1s;
+			tmpO[i] = ~(intEN);
+		end
+		else // C_OUT_HIGH unknown
+			tmpO = `alldbXs;
+
+		intO <= #1 tmpO;
+		
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend = intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend = intQpipe[2];
+		end
+	end
+
+	always @(CLK)
+  		lastCLK <= CLK;
+
+	always@(S or intEN)
+	begin
+		i = 0;
+		k = 1;
+		unknown = 0;
+
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1'b1)
+				i = i + k;
+			else if(S[j] === 1'bx || S[j] === 1'bz)
+				unknown = 1;
+			k = k * 2;	
+		end
+		
+		if(unknown == 1 && intEN === 1'b1)
+			tmpO = `alldbXs;
+		else if(C_OUT_HIGH === 1'b1)
+		begin
+			tmpO = `all0s;	
+			tmpO[i] = intEN;
+		end
+		else if(C_OUT_HIGH === 1'b0)
+		begin
+			tmpO = `alldb1s;
+			tmpO[i] = ~(intEN);
+		end
+		else // C_OUT_HIGH unknown
+			tmpO = `alldbXs;
+
+		intO <= #1 tmpO;
+	end		
+
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				intQpipe[pipe] <= intQpipe[pipe+1];
+			end
+			intQpipe[C_PIPE_STAGES] <= intO;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				tmp_pipe1 = intQpipe[pipe];
+				tmp_pipe2 = intQpipe[pipe+1];
+				for(pipe1 = 0; pipe1 < C_OUT_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				intQpipe[pipe] <= tmp_pipe1;
+			end
+			tmp_pipe1 = intQpipe[C_PIPE_STAGES];
+			for(pipe1 = 0; pipe1 < C_OUT_WIDTH; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== intO[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			intQpipe[C_PIPE_STAGES] <= tmp_pipe1;
+		end
+	end
+	
+	always@(intO or intQpipe[2])
+	begin
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend <= intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend <= intQpipe[2];
+		end
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+
+endmodule	
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef alldb1s
+`undef all0s
+`undef alldbXs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DECODE_BINARY_V6_0.v

@@ -0,0 +1,250 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_DECODE_BINARY_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_DECODE_BINARY_V6_0.v
+-- Author - Xilinx
+-- Creation - 21 May 1999
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_DECODE_BINARY_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define alldb1s {C_OUT_WIDTH{1'b1}}
+`define all0s 'b0
+`define alldbXs {C_OUT_WIDTH{1'bx}}
+
+module C_DECODE_BINARY_V6_0 (CLK, EN, CE, S, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_EN			= 0;
+	parameter C_HAS_O			= 0;
+	parameter C_HAS_Q			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HEIGHT          = 0;
+	parameter C_OUT_HIGH		= 1;
+	parameter C_OUT_WIDTH 		= 8;
+	parameter C_PIPE_STAGES		= 1;
+	parameter C_SEL_WIDTH		= 3;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input EN;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_OUT_WIDTH-1 : 0] O;
+	output [C_OUT_WIDTH-1 : 0] Q;
+	 
+	reg [C_OUT_WIDTH-1 : 0] data;
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	wire intEN;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	reg [C_OUT_WIDTH-1 : 0] intO;
+	reg [C_OUT_WIDTH-1 : 0] tmpO;
+	wire [C_OUT_WIDTH-1 : 0] intQ;
+	 
+	reg [C_OUT_WIDTH-1 : 0] intQpipe [C_PIPE_STAGES+2 : 0];
+	reg [C_OUT_WIDTH-1 : 0] intQpipeend;
+	reg [C_OUT_WIDTH : 0] tmp_pipe1;
+	reg [C_OUT_WIDTH : 0] tmp_pipe2;
+
+	wire [C_OUT_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `alldbXs);
+	wire [C_OUT_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `alldbXs);
+	reg lastCLK;
+
+	// Sort out default values for missing ports
+	
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intEN = defval(EN, C_HAS_EN, 1);
+
+	integer i, j, k;
+	integer m, unknown;
+	integer pipe, pipe1;
+	
+	// Register on output by default
+	C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_OUT_WIDTH)
+		reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+		for(j = 0; j <= C_PIPE_STAGES - 1; j = j + 1)
+			intQpipe[j] = 'b0;
+		i = 0;
+		k = 1;
+		unknown = 0;
+
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1'b1)
+				i = i + k;
+			else if(S[j] === 1'bx || S[j] === 1'bz)
+				unknown = 1;
+			k = k * 2;	
+		end
+		
+		if(unknown == 1 && intEN === 1'b1)
+			tmpO = `alldbXs;
+		else if(C_OUT_HIGH === 1'b1)
+		begin
+			tmpO = `all0s;	
+			tmpO[i] = intEN;
+		end
+		else if(C_OUT_HIGH === 1'b0)
+		begin
+			tmpO = `alldb1s;
+			tmpO[i] = ~(intEN);
+		end
+		else // C_OUT_HIGH unknown
+			tmpO = `alldbXs;
+
+		intO <= #1 tmpO;
+		
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend = intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend = intQpipe[2];
+		end
+	end
+
+	always @(CLK)
+  		lastCLK <= CLK;
+
+	always@(S or intEN)
+	begin
+		i = 0;
+		k = 1;
+		unknown = 0;
+
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1'b1)
+				i = i + k;
+			else if(S[j] === 1'bx || S[j] === 1'bz)
+				unknown = 1;
+			k = k * 2;	
+		end
+		
+		if(unknown == 1 && intEN === 1'b1)
+			tmpO = `alldbXs;
+		else if(C_OUT_HIGH === 1'b1)
+		begin
+			tmpO = `all0s;	
+			tmpO[i] = intEN;
+		end
+		else if(C_OUT_HIGH === 1'b0)
+		begin
+			tmpO = `alldb1s;
+			tmpO[i] = ~(intEN);
+		end
+		else // C_OUT_HIGH unknown
+			tmpO = `alldbXs;
+
+		intO <= #1 tmpO;
+	end		
+
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				intQpipe[pipe] <= intQpipe[pipe+1];
+			end
+			intQpipe[C_PIPE_STAGES] <= intO;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				tmp_pipe1 = intQpipe[pipe];
+				tmp_pipe2 = intQpipe[pipe+1];
+				for(pipe1 = 0; pipe1 < C_OUT_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				intQpipe[pipe] <= tmp_pipe1;
+			end
+			tmp_pipe1 = intQpipe[C_PIPE_STAGES];
+			for(pipe1 = 0; pipe1 < C_OUT_WIDTH; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== intO[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			intQpipe[C_PIPE_STAGES] <= tmp_pipe1;
+		end
+	end
+	
+	always@(intO or intQpipe[2])
+	begin
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend <= intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend <= intQpipe[2];
+		end
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+
+endmodule	
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef alldb1s
+`undef all0s
+`undef alldbXs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DECODE_BINARY_V7_0.v

@@ -0,0 +1,279 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Id: C_DECODE_BINARY_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_DECODE_BINARY_V7_0.v
+-- Author - Xilinx
+-- Creation - 21 May 1999
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_DECODE_BINARY_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define alldb1s {C_OUT_WIDTH{1'b1}}
+`define all0s 'b0
+`define alldbXs {C_OUT_WIDTH{1'bx}}
+
+module C_DECODE_BINARY_V7_0 (CLK, EN, CE, S, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_EN			= 0;
+	parameter C_HAS_O			= 0;
+	parameter C_HAS_Q			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_HEIGHT          = 0;
+	parameter C_OUT_HIGH		= 1;
+	parameter C_OUT_WIDTH 		= 8;
+	parameter C_PIPE_STAGES		= 1;
+	parameter C_SEL_WIDTH		= 3;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input EN;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_OUT_WIDTH-1 : 0] O;
+	output [C_OUT_WIDTH-1 : 0] Q;
+	 
+	reg [C_OUT_WIDTH-1 : 0] data;
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	wire intEN;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	reg [C_OUT_WIDTH-1 : 0] intO;
+	reg [C_OUT_WIDTH-1 : 0] tmpO;
+	wire [C_OUT_WIDTH-1 : 0] intQ;
+	 
+	reg [C_OUT_WIDTH-1 : 0] intQpipe [C_PIPE_STAGES+2 : 0];
+	reg [C_OUT_WIDTH-1 : 0] intQpipeend;
+	reg [C_OUT_WIDTH : 0] tmp_pipe1;
+	reg [C_OUT_WIDTH : 0] tmp_pipe2;
+
+	wire [C_OUT_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `alldbXs);
+	wire [C_OUT_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `alldbXs);
+	reg lastCLK;
+
+	// Sort out default values for missing ports
+	
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	assign intEN = defval(EN, C_HAS_EN, 1);
+
+	integer i, j, k;
+	integer m, unknown;
+	integer pipe, pipe1;
+	
+	// Register on output by default
+	C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_OUT_WIDTH)
+		reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+		for(j = 0; j <= C_PIPE_STAGES - 1; j = j + 1)
+			intQpipe[j] = 'b0;
+		i = 0;
+		k = 1;
+		unknown = 0;
+
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1'b1)
+				i = i + k;
+			else if(S[j] === 1'bx || S[j] === 1'bz)
+				unknown = 1;
+			k = k * 2;	
+		end
+		
+		if(unknown == 1 && intEN === 1'b1)
+			tmpO = `alldbXs;
+		else if(C_OUT_HIGH === 1'b1)
+		begin
+			tmpO = `all0s;	
+			tmpO[i] = intEN;
+		end
+		else if(C_OUT_HIGH === 1'b0)
+		begin
+			tmpO = `alldb1s;
+			tmpO[i] = ~(intEN);
+		end
+		else // C_OUT_HIGH unknown
+			tmpO = `alldbXs;
+
+		intO <= #1 tmpO;
+		
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend = intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend = intQpipe[2];
+		end
+	end
+
+	always @(CLK)
+  		lastCLK <= CLK;
+
+	always@(S or intEN)
+	begin
+		i = 0;
+		k = 1;
+		unknown = 0;
+
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1'b1)
+				i = i + k;
+			else if(S[j] === 1'bx || S[j] === 1'bz)
+				unknown = 1;
+			k = k * 2;	
+		end
+		
+		if(unknown == 1 && intEN === 1'b1)
+			tmpO = `alldbXs;
+		else if(C_OUT_HIGH === 1'b1)
+		begin
+			tmpO = `all0s;	
+			tmpO[i] = intEN;
+		end
+		else if(C_OUT_HIGH === 1'b0)
+		begin
+			tmpO = `alldb1s;
+			tmpO[i] = ~(intEN);
+		end
+		else // C_OUT_HIGH unknown
+			tmpO = `alldbXs;
+
+		intO <= #1 tmpO;
+	end		
+
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				intQpipe[pipe] <= intQpipe[pipe+1];
+			end
+			intQpipe[C_PIPE_STAGES] <= intO;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				tmp_pipe1 = intQpipe[pipe];
+				tmp_pipe2 = intQpipe[pipe+1];
+				for(pipe1 = 0; pipe1 < C_OUT_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				intQpipe[pipe] <= tmp_pipe1;
+			end
+			tmp_pipe1 = intQpipe[C_PIPE_STAGES];
+			for(pipe1 = 0; pipe1 < C_OUT_WIDTH; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== intO[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			intQpipe[C_PIPE_STAGES] <= tmp_pipe1;
+		end
+	end
+	
+	always@(intO or intQpipe[2])
+	begin
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend <= intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend <= intQpipe[2];
+		end
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+
+endmodule	
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef alldb1s
+`undef all0s
+`undef alldbXs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V5_0.v

@@ -0,0 +1,890 @@
+/* $Id: C_DIST_MEM_V5_0.v,v 1.17 2008/09/08 20:06:48 akennedy Exp $
+--
+-- Filename - C_DIST_MEM_V5_0.v
+-- Author - Xilinx
+-- Creation - 24 Mar 1999
+--
+-- Description
+--  Distributed RAM Simulation Model
+*/
+
+
+`timescale 1ns/10ps
+`define all0s 'b0
+`define all1s {C_WIDTH{1'b1}}
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+`define addrallXs {C_ADDR_WIDTH{1'bx}}
+
+`define c_rom 0
+`define c_sp_ram 1
+`define c_dp_ram 2
+`define c_srl16 3
+
+`define c_lut_based 0
+`define c_buft_based 1
+
+module C_DIST_MEM_V5_0 (A, D, DPRA, SPRA, CLK, WE, I_CE, RD_EN, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO);
+
+  parameter C_ADDR_WIDTH     = 6;
+  parameter C_DEFAULT_DATA   = "0";
+  parameter C_DEFAULT_DATA_RADIX = 1;
+  parameter C_DEPTH          = 64;
+  parameter C_ENABLE_RLOCS   = 1;
+  parameter C_GENERATE_MIF   = 0;
+  parameter C_HAS_CLK        = 1;
+  parameter C_HAS_D          = 1;
+  parameter C_HAS_DPO        = 0;
+  parameter C_HAS_DPRA       = 0;
+  parameter C_HAS_I_CE       = 0;
+  parameter C_HAS_QDPO       = 0;
+  parameter C_HAS_QDPO_CE    = 0;
+  parameter C_HAS_QDPO_CLK   = 0;
+  parameter C_HAS_QDPO_RST   = 0;    // RSTB
+  parameter C_HAS_QDPO_SRST  = 0;
+  parameter C_HAS_QSPO       = 0;
+  parameter C_HAS_QSPO_CE    = 0;
+  parameter C_HAS_QSPO_RST   = 0;    // RSTA
+  parameter C_HAS_QSPO_SRST  = 0;
+  parameter C_HAS_RD_EN      = 0;
+  parameter C_HAS_SPO        = 1;
+  parameter C_HAS_SPRA       = 0;
+  parameter C_HAS_WE         = 1;
+  parameter C_LATENCY    = 0;
+  parameter C_MEM_INIT_FILE  = "null.mif";
+  parameter C_MEM_TYPE       = 1; // c_sp_ram
+  parameter C_MUX_TYPE       = 0; // c_lut_based
+  parameter C_QCE_JOINED     = 0;
+  parameter C_QUALIFY_WE     = 0;
+  parameter C_READ_MIF       = 0;
+  parameter C_REG_A_D_INPUTS = 0;
+  parameter C_REG_DPRA_INPUT = 0;
+  parameter C_SYNC_ENABLE	 = 0;
+  parameter C_WIDTH          = 16;
+  parameter radix = C_DEFAULT_DATA_RADIX;
+  parameter pipe_stages = C_LATENCY-C_REG_A_D_INPUTS;
+  parameter dpo_pipe_stages = pipe_stages+C_HAS_QDPO-C_HAS_QSPO;
+  parameter C_RAM32_FIX      = 0;	// should not be passed in to simulation model
+
+  input  [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A;
+  input  [C_WIDTH-1 : 0] D;
+  input  [C_ADDR_WIDTH-1 : 0] DPRA;
+  input  [C_ADDR_WIDTH-1 : 0] SPRA;
+  input  CLK;
+  input  WE;
+  input  I_CE;
+  input  RD_EN;
+  input  QSPO_CE;
+  input  QDPO_CE;
+  input  QDPO_CLK;
+  input  QSPO_RST;
+  input  QDPO_RST;
+  input  QSPO_SRST;
+  input  QDPO_SRST;
+  output [C_WIDTH-1 : 0] SPO;
+  output [C_WIDTH-1 : 0] QSPO;
+  output [C_WIDTH-1 : 0] DPO;
+  output [C_WIDTH-1 : 0] QDPO;
+
+	// Address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] a_int;
+	// Read Address signal connected to srl16-based memory
+	wire [C_ADDR_WIDTH - 1 : 0] spra_int;
+	// Registered Address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] a_int1;
+	// Registered Read Address signal connected to srl16-based memory
+	wire [C_ADDR_WIDTH - 1 : 0] spra_int1;
+	// DP port address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] dpra_int;
+	// DP port address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] dpra_int1;
+	// Input data signal connected to memory
+	wire [C_WIDTH - 1 : 0] d_int;
+	// Registered Input data signal connected to memory
+	wire [C_WIDTH - 1 : 0] d_int1;
+ 	// DP output register clock
+ 	wire doclk;
+    // Input data/address/WE register Clock Enable
+	wire ice;
+	// Special address register Clock Enable for ROMs
+	wire a_reg_ice;
+ 	// DP read address port register clock enable
+// 	wire dpra_ce;
+	// WE wire connected to memory
+	wire we_int;
+	// Registered WE wire connected to memory
+	wire we_int1;
+	// Clock enable for the WE register
+	wire wece;
+	// Read Enable wire connected to BUFT-type output mux
+	wire re_int;
+	// Registered Read Enable wire connected to BUFT-type output mux
+	wire re_int1;
+	// unregistered version of qspo_ce
+	wire qspo_ce_int;
+	// possibly registered version of qspo_ce
+	wire qspo_ce_reg;
+	// registered version of qspo_ce
+	wire qspo_ce_reg1;
+	// unregistered version of qdpo_ce
+	wire qdpo_ce_int;
+	// possibly registered version of qdpo_ce
+	wire qdpo_ce_reg;
+	// registered version of qdpo_ce
+	wire qdpo_ce_reg1;
+	// possibly single port registered output reset
+        wire qspo_rst_int;
+        // possibly dual port registered output reset
+        wire qdpo_rst_int;
+	// possibly single port registered output sync reset
+        wire qspo_srst_int;
+        // possibly dual port registered output sync reset
+        wire qdpo_srst_int;
+	// Direct SP output from memory
+	reg [C_WIDTH - 1 : 0] spo_async;
+	// Direct DP output from memory
+	reg [C_WIDTH - 1 : 0] dpo_async;
+	// Possibly pipelined and/or registered SP output from memory
+	wire [C_WIDTH - 1 : 0] intQSPO;
+	// Possibly pipelined and/or registered DP output from memory
+	wire [C_WIDTH - 1 : 0] intQDPO;
+	// Pipeline signals
+ 	reg [C_WIDTH - 1 : 0] spo_pipe [pipe_stages+2 : 0];
+ 	reg [C_WIDTH - 1 : 0] dpo_pipe [dpo_pipe_stages+2 : 0];
+	// Possibly pipelined SP output from memory
+ 	reg [C_WIDTH - 1 : 0] spo_pipeend;
+	// Possibly pipelined DP output from memory
+ 	reg [C_WIDTH - 1 : 0] dpo_pipeend;
+    // BUFT outputs
+    wire [C_WIDTH - 1 : 0] spo_reg;
+    wire [C_WIDTH - 1 : 0] dpo_reg;
+    wire [C_WIDTH - 1 : 0] spo_reg_tmp;
+    wire [C_WIDTH - 1 : 0] dpo_reg_tmp;
+
+	integer pipe, pipe1, pipe2, pipe3, pipe4, i, j, srl_start, srl_end;
+	
+	// Array to hold ram data
+	reg [C_WIDTH-1 : 0] ram_data [C_DEPTH-1 : 0];
+	reg [C_WIDTH-1 : 0] tmp_data1;
+	reg [C_WIDTH-1 : 0] tmp_data2;
+		
+	reg [C_WIDTH-1 : 0] default_data;
+	reg [C_WIDTH-1 : 0] spo_tmp;
+	reg [C_WIDTH-1 : 0] dpo_tmp;
+	reg [C_WIDTH-1 : 0] tmp_pipe1;
+	reg [C_WIDTH-1 : 0] tmp_pipe2;
+	reg [C_WIDTH-1 : 0] tmp_pipe3;
+	reg lastCLK;
+	reg lastdoclk;
+    
+  function integer ADDR_IS_X;
+    input [C_ADDR_WIDTH-1 : 0] value;
+    integer i;
+  begin
+    ADDR_IS_X = 0;
+    for(i = 0; i < C_ADDR_WIDTH; i = i + 1)
+      if(value[i] === 1'bx)
+        ADDR_IS_X = 1;
+  end
+  endfunction
+  
+  // Deal with the optional output signals...
+  wire [C_WIDTH - 1 : 0] SPO = (C_HAS_SPO ? (C_MUX_TYPE == `c_lut_based ? spo_async : spo_reg) : `allXs);
+  wire [C_WIDTH - 1 : 0] DPO = (C_HAS_DPO && C_MEM_TYPE == `c_dp_ram ? (C_MUX_TYPE == `c_lut_based ? dpo_async : dpo_reg) : `allXs);
+  wire [C_WIDTH - 1 : 0] QSPO = (C_HAS_QSPO ? intQSPO : `allXs);
+  wire [C_WIDTH - 1 : 0] QDPO = (C_HAS_QDPO ? intQDPO : `allXs);
+  
+  // Deal with the optional input signals...
+  
+  assign ice = (C_HAS_I_CE == 1 ? I_CE : 1'b1);
+  assign a_reg_ice = (C_MEM_TYPE == `c_rom ? qspo_ce_int : ice);
+  assign wece = (C_HAS_WE == 1 && C_REG_A_D_INPUTS == 1 && C_QUALIFY_WE == 1 ? ice : 1'b1);
+//  assign dpra_ce = (C_HAS_QDPO_CE == 1  ? QDPO_CE : 1'b1);
+  assign doclk = (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK);
+  assign qspo_ce_int = (C_HAS_QSPO_CE == 1 ? QSPO_CE : 1'b1);
+  assign qdpo_ce_int = (C_QCE_JOINED == 1 ? qspo_ce_int : (C_HAS_QDPO_CE == 1 ? QDPO_CE : ((C_HAS_QSPO == 1 && C_MEM_TYPE == `c_srl16) ? qspo_ce_int : 1'b1))); 
+  assign qspo_rst_int = (C_HAS_QSPO_RST && C_HAS_QSPO ? QSPO_RST : 1'b0);
+  assign qdpo_rst_int = (C_HAS_QDPO_RST && C_HAS_QDPO ? QDPO_RST : 1'b0);
+  assign qspo_srst_int = (C_HAS_QSPO_SRST && C_HAS_QSPO ? QSPO_SRST : 1'b0);
+  assign qdpo_srst_int = (C_HAS_QDPO_SRST && C_HAS_QDPO ? QDPO_SRST : 1'b0);
+  
+  // (Optional) registers on SP address and on optional data/we/qspo_ce signals
+  C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                qspo1_reg (.D(qspo_ce_int), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+			  .Q(qspo_ce_reg1));
+  
+  C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, (C_ADDR_WIDTH-(C_ADDR_WIDTH>4?(C_HAS_SPRA*4):0)))
+                a_rega (.D(A[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]), .CLK(CLK), .CE(a_reg_ice), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(a_int1[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]));
+  
+  C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_ADDR_WIDTH)
+                spra_reg (.D(SPRA), .CLK(CLK), .CE(qspo_ce_int), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(spra_int1));
+  
+  C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, 1)
+                we_reg (.D(WE), .CLK(CLK), .CE(wece), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(we_int1));
+  
+  C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                re_reg (.D(RD_EN), .CLK(CLK),// .CE(qspo_ce_int),
+                 .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(re_int1));                          
+  
+  C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	d_reg (.D(D), .CLK(CLK), .CE(ice), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(d_int1));                          
+  
+  C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	spo_reg1 (.D(spo_async), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(spo_reg_tmp));                          
+  
+  C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	dpo_reg1 (.D(dpo_async), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(dpo_reg_tmp));
+						   
+  // Deal with these optional registers
+  assign qspo_ce_reg = (C_REG_A_D_INPUTS == 0 ? (C_HAS_QSPO_CE == 1 ? qspo_ce_int : 1'b1) : (C_HAS_QSPO_CE == 1 ? qspo_ce_reg1 : 1'b1));
+  assign a_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : (C_ADDR_WIDTH>4 ? A[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)) : 
+  										  (C_MEM_TYPE != `c_srl16 ? a_int1 : (C_ADDR_WIDTH>4 ? a_int1[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)));
+  assign spra_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : SPRA) : 
+                                          (C_MEM_TYPE != `c_srl16 ? a_int1 : spra_int1));
+  assign we_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_WE == 1 ? WE : 1'b1) : (C_HAS_WE == 1 ? we_int1 : 1'b1));
+  assign re_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_RD_EN == 1 ? RD_EN : 1'b1) : (C_HAS_RD_EN == 1 ? re_int1 : 1'b1));
+  assign d_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_D == 1 ? D : `allXs) : (C_HAS_D == 1 ? d_int1 : `allXs));
+  assign spo_reg = (pipe_stages == 1 ? spo_reg_tmp : spo_async);
+  assign dpo_reg = (pipe_stages == 1 ? dpo_reg_tmp : dpo_async);
+  
+  // (Optional) DP Read Address and QDPO_CE registers
+  
+  C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_ADDR_WIDTH)
+                dpra_reg (.D(DPRA), .CLK(doclk), .CE(qdpo_ce_int), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(dpra_int1));
+  
+  C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                qdpo1_reg (.D(qdpo_ce_int), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(qdpo_ce_reg1));
+  
+  // Deal with these optional registers
+  assign qdpo_ce_reg = (C_REG_DPRA_INPUT == 0 ? (C_HAS_QDPO_CE == 1 ? qdpo_ce_int : (C_QCE_JOINED == 1 ? qdpo_ce_int : 1'b1)) : 
+  												(C_HAS_QDPO_CE == 1 ? qdpo_ce_reg1 : (C_QCE_JOINED == 1 || C_MEM_TYPE == `c_srl16 ? qdpo_ce_reg1 : 1'b1)));
+  assign dpra_int = (C_REG_DPRA_INPUT == 0 ? (C_HAS_DPRA == 1 ? DPRA : `allXs) : (C_HAS_DPRA == 1 ? dpra_int1 : `allXs));
+
+  // (Optional) pipeline registers
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && qspo_ce_reg === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1)
+			begin
+				spo_pipe[pipe] <= spo_pipe[pipe+1];
+			end
+			spo_pipe[pipe_stages] <= spo_async;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || qspo_ce_reg === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1)
+			begin
+				tmp_pipe1 = spo_pipe[pipe];
+				tmp_pipe2 = spo_pipe[pipe+1];
+				for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				spo_pipe[pipe] <= tmp_pipe1;
+			end
+			tmp_pipe1 = spo_pipe[pipe_stages];
+			for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== spo_async[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			spo_pipe[pipe_stages] <= tmp_pipe1;
+		end
+	end
+  
+	always@(spo_async or spo_pipe[2])
+	begin
+		if(pipe_stages < 2) // No pipeline
+			spo_pipeend <= spo_async;
+		else // Pipeline stages required
+		begin
+			spo_pipeend <= spo_pipe[2];
+		end
+	end
+       
+	always@(posedge doclk)
+	begin
+		if(doclk === 1'b1 && lastdoclk === 1'b0 && qdpo_ce_reg === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe3 = 2; pipe3 <= dpo_pipe_stages-1; pipe3 = pipe3 + 1)
+			begin
+				dpo_pipe[pipe3] <= dpo_pipe[pipe3+1];
+			end
+			dpo_pipe[dpo_pipe_stages] <= dpo_async;
+		end
+		else if((doclk === 1'bx && lastdoclk === 1'b0) || (doclk === 1'b1 && lastdoclk === 1'bx) || qdpo_ce_reg === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe4 = 2; pipe4 <= dpo_pipe_stages-1; pipe4 = pipe4 + 1)
+			begin
+				tmp_pipe3 = dpo_pipe[pipe4];
+				tmp_pipe2 = dpo_pipe[pipe4+1];
+				for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe3[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe3[pipe1] = 1'bx;
+				end
+				dpo_pipe[pipe4] <= tmp_pipe3;
+			end
+			tmp_pipe3 = dpo_pipe[dpo_pipe_stages];
+			for(pipe2 = 0; pipe2 < C_WIDTH; pipe2 = pipe2 + 1)
+			begin
+				if(tmp_pipe3[pipe2] !== dpo_async[pipe2])
+					tmp_pipe3[pipe2] = 1'bx;
+			end
+			dpo_pipe[dpo_pipe_stages] <= tmp_pipe3;
+		end
+	end
+  
+	always@(dpo_async or dpo_pipe[2])
+	begin
+		if(dpo_pipe_stages < 2) // No pipeline
+			dpo_pipeend <= dpo_async;
+		else // Pipeline stages required
+		begin
+			dpo_pipeend <= dpo_pipe[2];
+		end
+	end
+
+	// (Optional) output registers at end of optional pipelines
+	
+    C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, C_HAS_QSPO_RST, 0, 0,
+                           1, C_HAS_QSPO_SRST, 0, 0,
+                           "0", C_SYNC_ENABLE, 0, C_WIDTH)
+                qspo_reg (.D(spo_pipeend), .CLK(CLK), .CE(qspo_ce_reg), .ASET(1'b0),
+			  .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .ACLR(qspo_rst_int), .SCLR(qspo_srst_int), .Q(intQSPO));
+  
+    C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, C_HAS_QDPO_RST, 0, 0,
+                           1, C_HAS_QDPO_SRST, 0, 0,
+                           "0", C_SYNC_ENABLE, 0, C_WIDTH)
+                qdpo_reg (.D(dpo_pipeend), .CLK(doclk), .CE(qdpo_ce_reg), .ASET(1'b0),
+			  .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .ACLR(qdpo_rst_int), .SCLR(qdpo_srst_int), .Q(intQDPO));
+  
+	
+       
+  // Startup behaviour  
+  initial
+  begin
+    default_data = 'b0;
+    case (radix)
+       3 : default_data = decstr_conv(C_DEFAULT_DATA);
+       2 : default_data = binstr_conv(C_DEFAULT_DATA);
+       1 : default_data = hexstr_conv(C_DEFAULT_DATA);
+      default : $display("ERROR in %m at %d ns: BAD DATA RADIX - valid range 1 to 3", $time);
+    endcase
+
+    for(i = 0; i < C_DEPTH; i = i + 1)
+      ram_data[i] = default_data;
+    
+    if(C_READ_MIF == 1)
+    begin
+      $readmemb(C_MEM_INIT_FILE, ram_data);
+    end
+    if (C_GENERATE_MIF == 1)
+      write_meminit_file;
+	  
+	spo_tmp = 'b0;
+	dpo_tmp = 'b0;
+	lastCLK = 1'b0;
+	lastdoclk = 1'b0;
+	
+	for(i = 0; i < pipe_stages+3; i = i + 1)
+	begin
+		spo_pipe[i] = `all0s;
+	end
+	for(i = 0; i < dpo_pipe_stages+3; i = i + 1)
+	begin
+		dpo_pipe[i] = `all0s;
+	end
+	if(pipe_stages < 2) // No pipeline
+	begin
+		spo_pipeend = spo_async;
+	end
+	else
+	begin
+		spo_pipeend = spo_pipe[2];
+	end
+    if(dpo_pipe_stages < 2) // No pipeline
+	begin
+		dpo_pipeend = dpo_async;
+	end
+	else
+	begin
+		dpo_pipeend = dpo_pipe[2];
+	end
+  end
+  
+  always @(CLK)
+  	lastCLK <= CLK;
+	
+  always @(doclk)
+  	lastdoclk <= doclk;
+
+  always @(posedge CLK or a_int or we_int or spra_int or dpra_int or d_int or re_int)
+  begin
+  	if(((CLK === 1'b1 && lastCLK === 1'b0) || C_HAS_CLK == 0) && C_MEM_TYPE != `c_rom)
+	begin
+		if(ADDR_IS_X(a_int) || a_int < C_DEPTH)
+		begin
+			if(we_int === 1'bx)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+			else if(we_int === 1'b1)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							ram_data[i] = ram_data[i-1];
+						end
+						ram_data[srl_start] = d_int;
+					end
+					else
+					begin 			
+                        //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1)
+                        //begin
+                        //    $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time);
+                        //end
+						ram_data[a_int] = d_int;
+					end
+				end
+			end
+		end
+		else if(a_int >= C_DEPTH)
+			$display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH);
+	end
+	else if((C_HAS_CLK == 0 || ((CLK === 1'bx && lastCLK === 1'b0) || CLK === 1'b1 && lastCLK === 1'bx)) && C_MEM_TYPE != `c_rom)
+	begin
+		if(ADDR_IS_X(a_int) || a_int < C_DEPTH)
+		begin
+			if(we_int === 1'bx)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+			else if(we_int === 1'b1)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin 			
+                        //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1)
+                        //begin
+                        //    $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time);
+                        //end
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+		end
+		else if(a_int >= C_DEPTH)
+			$display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH);
+	end
+	
+  // Read behaviour
+	
+  	if(re_int === 1'bx)
+	begin
+		spo_tmp = `allXs;
+		dpo_tmp = `allXs;
+	end
+	else if(re_int === 1'b1)
+	begin
+		if(ADDR_IS_X(spra_int))
+			spo_tmp = `allXs;
+		else
+		begin
+			if(spra_int < C_DEPTH)
+				spo_tmp = ram_data[spra_int];
+			else if(C_MUX_TYPE == `c_buft_based)
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+			 	spo_tmp = `allZs;
+			end
+			else
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+				spo_tmp = `all0s;
+			end
+		end
+		
+		if(ADDR_IS_X(dpra_int))
+			dpo_tmp = `allXs;
+		else
+		begin
+			if(dpra_int < C_DEPTH)
+				dpo_tmp = ram_data[dpra_int];
+			else if(C_MUX_TYPE == `c_buft_based)
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+			 	dpo_tmp = `allZs;
+			end
+			else
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+				dpo_tmp = `all0s;
+			end
+		end
+	end
+	else // re_int == 0
+	begin
+		spo_tmp = `allZs;
+		dpo_tmp = `allZs;
+	end
+	
+	spo_async <= spo_tmp;
+	dpo_async <= dpo_tmp;  
+	
+  end
+  
+
+  function [C_WIDTH-1:0] binstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i;
+
+    begin
+      index = 0;
+      binstr_conv = 'b0;
+
+      for( i=C_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 : i = -1;
+          8'b00110000 : binstr_conv[index] = 1'b0;
+          8'b00110001 : binstr_conv[index] = 1'b1;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time);
+            binstr_conv[index] = 1'bx;
+          end
+        endcase
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  function [C_WIDTH-1:0] hexstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = 'b0;
+      for( i=C_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          8'b01100001 : bin = 4'b1010;
+          8'b01100010 : bin = 4'b1011;
+          8'b01100011 : bin = 4'b1100;
+          8'b01100100 : bin = 4'b1101;
+          8'b01100101 : bin = 4'b1110;
+          8'b01100110 : bin = 4'b1111;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A HEX CHARACTER", $time);
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  function [C_WIDTH-1:0] decstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      decstr_conv = 'b0;
+      for( i=C_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A DECIMAL CHARACTER", $time);
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_WIDTH)
+          begin
+            decstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+  
+  task write_meminit_file;
+  
+    integer addrs, outfile, bit_index;
+    
+    reg [C_WIDTH-1 : 0] conts;
+    reg anyX;
+    
+    begin
+      outfile = $fopen(C_MEM_INIT_FILE);
+      for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1)
+      begin
+        anyX = 1'b0;
+        conts = ram_data[addrs];
+        for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1)
+          if(conts[bit_index] === 1'bx) anyX = 1'b1;
+        if(anyX == 1'b1)  
+          $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time);
+        $fdisplay(outfile,"%b",ram_data[addrs]);
+      end
+      $fclose(outfile);
+    end
+  endtask
+
+endmodule
+
+`undef all0s
+`undef all1s
+`undef allXs
+`undef allZs
+`undef addrallXs
+
+`undef c_rom
+`undef c_sp_ram
+`undef c_dp_ram
+`undef c_srl16
+
+`undef c_lut_based
+`undef c_buft_based
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V6_0.v

@@ -0,0 +1,903 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_DIST_MEM_V6_0.v,v 1.17 2008/09/08 20:06:51 akennedy Exp $
+--
+-- Filename - C_DIST_MEM_V6_0.v
+-- Author - Xilinx
+-- Creation - 24 Mar 1999
+--
+-- Description
+--  Distributed RAM Simulation Model
+*/
+
+
+`timescale 1ns/10ps
+`define all0s 'b0
+`define all1s {C_WIDTH{1'b1}}
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+`define addrallXs {C_ADDR_WIDTH{1'bx}}
+
+`define c_rom 0
+`define c_sp_ram 1
+`define c_dp_ram 2
+`define c_srl16 3
+
+`define c_lut_based 0
+`define c_buft_based 1
+
+module C_DIST_MEM_V6_0 (A, D, DPRA, SPRA, CLK, WE, I_CE, RD_EN, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO);
+
+  parameter C_ADDR_WIDTH     = 6;
+  parameter C_DEFAULT_DATA   = "0";
+  parameter C_DEFAULT_DATA_RADIX = 1;
+  parameter C_DEPTH          = 64;
+  parameter C_ENABLE_RLOCS   = 1;
+  parameter C_GENERATE_MIF   = 0;
+  parameter C_HAS_CLK        = 1;
+  parameter C_HAS_D          = 1;
+  parameter C_HAS_DPO        = 0;
+  parameter C_HAS_DPRA       = 0;
+  parameter C_HAS_I_CE       = 0;
+  parameter C_HAS_QDPO       = 0;
+  parameter C_HAS_QDPO_CE    = 0;
+  parameter C_HAS_QDPO_CLK   = 0;
+  parameter C_HAS_QDPO_RST   = 0;    // RSTB
+  parameter C_HAS_QDPO_SRST  = 0;
+  parameter C_HAS_QSPO       = 0;
+  parameter C_HAS_QSPO_CE    = 0;
+  parameter C_HAS_QSPO_RST   = 0;    // RSTA
+  parameter C_HAS_QSPO_SRST  = 0;
+  parameter C_HAS_RD_EN      = 0;
+  parameter C_HAS_SPO        = 1;
+  parameter C_HAS_SPRA       = 0;
+  parameter C_HAS_WE         = 1;
+  parameter C_LATENCY    = 0;
+  parameter C_MEM_INIT_FILE  = "null.mif";
+  parameter C_MEM_TYPE       = 1; // c_sp_ram
+  parameter C_MUX_TYPE       = 0; // c_lut_based
+  parameter C_QCE_JOINED     = 0;
+  parameter C_QUALIFY_WE     = 0;
+  parameter C_READ_MIF       = 0;
+  parameter C_REG_A_D_INPUTS = 0;
+  parameter C_REG_DPRA_INPUT = 0;
+  parameter C_SYNC_ENABLE	 = 0;
+  parameter C_WIDTH          = 16;
+  parameter radix = C_DEFAULT_DATA_RADIX;
+  parameter pipe_stages = C_LATENCY-C_REG_A_D_INPUTS;
+  parameter dpo_pipe_stages = pipe_stages+C_HAS_QDPO-C_HAS_QSPO;
+  parameter C_RAM32_FIX      = 0;	// should not be passed in to simulation model
+
+  parameter NCELAB_DPO_PIPE_CONSTANT = (dpo_pipe_stages < 2 ? 0 : 2);
+  parameter NCELAB_SPO_PIPE_CONSTANT = (pipe_stages < 2 ? 0 : 2);
+
+  input  [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A;
+  input  [C_WIDTH-1 : 0] D;
+  input  [C_ADDR_WIDTH-1 : 0] DPRA;
+  input  [C_ADDR_WIDTH-1 : 0] SPRA;
+  input  CLK;
+  input  WE;
+  input  I_CE;
+  input  RD_EN;
+  input  QSPO_CE;
+  input  QDPO_CE;
+  input  QDPO_CLK;
+  input  QSPO_RST;
+  input  QDPO_RST;
+  input  QSPO_SRST;
+  input  QDPO_SRST;
+  output [C_WIDTH-1 : 0] SPO;
+  output [C_WIDTH-1 : 0] QSPO;
+  output [C_WIDTH-1 : 0] DPO;
+  output [C_WIDTH-1 : 0] QDPO;
+
+	// Address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] a_int;
+	// Read Address signal connected to srl16-based memory
+	wire [C_ADDR_WIDTH - 1 : 0] spra_int;
+	// Registered Address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] a_int1;
+	// Registered Read Address signal connected to srl16-based memory
+	wire [C_ADDR_WIDTH - 1 : 0] spra_int1;
+	// DP port address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] dpra_int;
+	// DP port address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] dpra_int1;
+	// Input data signal connected to memory
+	wire [C_WIDTH - 1 : 0] d_int;
+	// Registered Input data signal connected to memory
+	wire [C_WIDTH - 1 : 0] d_int1;
+ 	// DP output register clock
+ 	wire doclk;
+    // Input data/address/WE register Clock Enable
+	wire ice;
+	// Special address register Clock Enable for ROMs
+	wire a_reg_ice;
+ 	// DP read address port register clock enable
+// 	wire dpra_ce;
+	// WE wire connected to memory
+	wire we_int;
+	// Registered WE wire connected to memory
+	wire we_int1;
+	// Clock enable for the WE register
+	wire wece;
+	// Read Enable wire connected to BUFT-type output mux
+	wire re_int;
+	// Registered Read Enable wire connected to BUFT-type output mux
+	wire re_int1;
+	// unregistered version of qspo_ce
+	wire qspo_ce_int;
+	// possibly registered version of qspo_ce
+	wire qspo_ce_reg;
+	// registered version of qspo_ce
+	wire qspo_ce_reg1;
+	// unregistered version of qdpo_ce
+	wire qdpo_ce_int;
+	// possibly registered version of qdpo_ce
+	wire qdpo_ce_reg;
+	// registered version of qdpo_ce
+	wire qdpo_ce_reg1;
+	// possibly single port registered output reset
+        wire qspo_rst_int;
+        // possibly dual port registered output reset
+        wire qdpo_rst_int;
+	// possibly single port registered output sync reset
+        wire qspo_srst_int;
+        // possibly dual port registered output sync reset
+        wire qdpo_srst_int;
+	// Direct SP output from memory
+	reg [C_WIDTH - 1 : 0] spo_async;
+	// Direct DP output from memory
+	reg [C_WIDTH - 1 : 0] dpo_async;
+	// Possibly pipelined and/or registered SP output from memory
+	wire [C_WIDTH - 1 : 0] intQSPO;
+	// Possibly pipelined and/or registered DP output from memory
+	wire [C_WIDTH - 1 : 0] intQDPO;
+	// Pipeline signals
+ 	reg [C_WIDTH - 1 : 0] spo_pipe [pipe_stages+2 : 0];
+ 	reg [C_WIDTH - 1 : 0] dpo_pipe [dpo_pipe_stages+2 : 0];
+	// Possibly pipelined SP output from memory
+ 	reg [C_WIDTH - 1 : 0] spo_pipeend;
+	// Possibly pipelined DP output from memory
+ 	reg [C_WIDTH - 1 : 0] dpo_pipeend;
+    // BUFT outputs
+    wire [C_WIDTH - 1 : 0] spo_reg;
+    wire [C_WIDTH - 1 : 0] dpo_reg;
+    wire [C_WIDTH - 1 : 0] spo_reg_tmp;
+    wire [C_WIDTH - 1 : 0] dpo_reg_tmp;
+
+	integer pipe, pipe1, pipe2, pipe3, pipe4, i, j, srl_start, srl_end;
+	
+	// Array to hold ram data
+	reg [C_WIDTH-1 : 0] ram_data [C_DEPTH-1 : 0];
+	reg [C_WIDTH-1 : 0] tmp_data1;
+	reg [C_WIDTH-1 : 0] tmp_data2;
+		
+	reg [C_WIDTH-1 : 0] default_data;
+	reg [C_WIDTH-1 : 0] spo_tmp;
+	reg [C_WIDTH-1 : 0] dpo_tmp;
+	reg [C_WIDTH-1 : 0] tmp_pipe1;
+	reg [C_WIDTH-1 : 0] tmp_pipe2;
+	reg [C_WIDTH-1 : 0] tmp_pipe3;
+	reg lastCLK;
+	reg lastdoclk;
+    
+  function integer ADDR_IS_X;
+    input [C_ADDR_WIDTH-1 : 0] value;
+    integer i;
+  begin
+    ADDR_IS_X = 0;
+    for(i = 0; i < C_ADDR_WIDTH; i = i + 1)
+      if(value[i] === 1'bx)
+        ADDR_IS_X = 1;
+  end
+  endfunction
+  
+  // Deal with the optional output signals...
+  wire [C_WIDTH - 1 : 0] SPO = (C_HAS_SPO ? (C_MUX_TYPE == `c_lut_based ? spo_async : spo_reg) : `allXs);
+  wire [C_WIDTH - 1 : 0] DPO = (C_HAS_DPO && C_MEM_TYPE == `c_dp_ram ? (C_MUX_TYPE == `c_lut_based ? dpo_async : dpo_reg) : `allXs);
+  wire [C_WIDTH - 1 : 0] QSPO = (C_HAS_QSPO ? intQSPO : `allXs);
+  wire [C_WIDTH - 1 : 0] QDPO = (C_HAS_QDPO ? intQDPO : `allXs);
+  
+  // Deal with the optional input signals...
+  
+  assign ice = (C_HAS_I_CE == 1 ? I_CE : 1'b1);
+  assign a_reg_ice = (C_MEM_TYPE == `c_rom ? qspo_ce_int : ice);
+  assign wece = (C_HAS_WE == 1 && C_REG_A_D_INPUTS == 1 && C_QUALIFY_WE == 1 ? ice : 1'b1);
+//  assign dpra_ce = (C_HAS_QDPO_CE == 1  ? QDPO_CE : 1'b1);
+  assign doclk = (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK);
+  assign qspo_ce_int = (C_HAS_QSPO_CE == 1 ? QSPO_CE : 1'b1);
+  assign qdpo_ce_int = (C_QCE_JOINED == 1 ? qspo_ce_int : (C_HAS_QDPO_CE == 1 ? QDPO_CE : ((C_HAS_QSPO == 1 && C_MEM_TYPE == `c_srl16) ? qspo_ce_int : 1'b1))); 
+  assign qspo_rst_int = (C_HAS_QSPO_RST && C_HAS_QSPO ? QSPO_RST : 1'b0);
+  assign qdpo_rst_int = (C_HAS_QDPO_RST && C_HAS_QDPO ? QDPO_RST : 1'b0);
+  assign qspo_srst_int = (C_HAS_QSPO_SRST && C_HAS_QSPO ? QSPO_SRST : 1'b0);
+  assign qdpo_srst_int = (C_HAS_QDPO_SRST && C_HAS_QDPO ? QDPO_SRST : 1'b0);
+  
+  // (Optional) registers on SP address and on optional data/we/qspo_ce signals
+  C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                qspo1_reg (.D(qspo_ce_int), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+			  .Q(qspo_ce_reg1));
+  
+  C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, (C_ADDR_WIDTH-(C_ADDR_WIDTH>4?(C_HAS_SPRA*4):0)))
+                a_rega (.D(A[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]), .CLK(CLK), .CE(a_reg_ice), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(a_int1[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]));
+  
+  C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_ADDR_WIDTH)
+                spra_reg (.D(SPRA), .CLK(CLK), .CE(qspo_ce_int), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(spra_int1));
+  
+  C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, 1)
+                we_reg (.D(WE), .CLK(CLK), .CE(wece), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(we_int1));
+  
+  C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                re_reg (.D(RD_EN), .CLK(CLK),// .CE(qspo_ce_int),
+                 .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(re_int1));                          
+  
+  C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	d_reg (.D(D), .CLK(CLK), .CE(ice), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(d_int1));                          
+  
+  C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	spo_reg1 (.D(spo_async), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(spo_reg_tmp));                          
+  
+  C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	dpo_reg1 (.D(dpo_async), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(dpo_reg_tmp));
+						   
+  // Deal with these optional registers
+  assign qspo_ce_reg = (C_REG_A_D_INPUTS == 0 ? (C_HAS_QSPO_CE == 1 ? qspo_ce_int : 1'b1) : (C_HAS_QSPO_CE == 1 ? qspo_ce_reg1 : 1'b1));
+  assign a_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : (C_ADDR_WIDTH>4 ? A[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)) : 
+  										  (C_MEM_TYPE != `c_srl16 ? a_int1 : (C_ADDR_WIDTH>4 ? a_int1[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)));
+  assign spra_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : SPRA) : 
+                                          (C_MEM_TYPE != `c_srl16 ? a_int1 : spra_int1));
+  assign we_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_WE == 1 ? WE : 1'b1) : (C_HAS_WE == 1 ? we_int1 : 1'b1));
+  assign re_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_RD_EN == 1 ? RD_EN : 1'b1) : (C_HAS_RD_EN == 1 ? re_int1 : 1'b1));
+  assign d_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_D == 1 ? D : `allXs) : (C_HAS_D == 1 ? d_int1 : `allXs));
+  assign spo_reg = (pipe_stages == 1 ? spo_reg_tmp : spo_async);
+  assign dpo_reg = (pipe_stages == 1 ? dpo_reg_tmp : dpo_async);
+  
+  // (Optional) DP Read Address and QDPO_CE registers
+  
+  C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_ADDR_WIDTH)
+                dpra_reg (.D(DPRA), .CLK(doclk), .CE(qdpo_ce_int), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(dpra_int1));
+  
+  C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                qdpo1_reg (.D(qdpo_ce_int), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(qdpo_ce_reg1));
+  
+  // Deal with these optional registers
+  assign qdpo_ce_reg = (C_REG_DPRA_INPUT == 0 ? (C_HAS_QDPO_CE == 1 ? qdpo_ce_int : (C_QCE_JOINED == 1 ? qdpo_ce_int : 1'b1)) : 
+  												(C_HAS_QDPO_CE == 1 ? qdpo_ce_reg1 : (C_QCE_JOINED == 1 || C_MEM_TYPE == `c_srl16 ? qdpo_ce_reg1 : 1'b1)));
+  assign dpra_int = (C_REG_DPRA_INPUT == 0 ? (C_HAS_DPRA == 1 ? DPRA : `allXs) : (C_HAS_DPRA == 1 ? dpra_int1 : `allXs));
+
+  // (Optional) pipeline registers
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && qspo_ce_reg === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1)
+			begin
+				spo_pipe[pipe] <= spo_pipe[pipe+1];
+			end
+			spo_pipe[pipe_stages] <= spo_async;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || qspo_ce_reg === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1)
+			begin
+				tmp_pipe1 = spo_pipe[pipe];
+				tmp_pipe2 = spo_pipe[pipe+1];
+				for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				spo_pipe[pipe] <= tmp_pipe1;
+			end
+			tmp_pipe1 = spo_pipe[pipe_stages];
+			for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== spo_async[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			spo_pipe[pipe_stages] <= tmp_pipe1;
+		end
+	end
+  
+	always@(spo_async or spo_pipe[NCELAB_SPO_PIPE_CONSTANT])	//2
+	begin
+		if(pipe_stages < 2) // No pipeline
+			spo_pipeend <= spo_async;
+		else // Pipeline stages required
+		begin
+			spo_pipeend <= spo_pipe[NCELAB_SPO_PIPE_CONSTANT];	//2
+		end
+	end
+       
+	always@(posedge doclk)
+	begin
+		if(doclk === 1'b1 && lastdoclk === 1'b0 && qdpo_ce_reg === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe3 = 2; pipe3 <= dpo_pipe_stages-1; pipe3 = pipe3 + 1)
+			begin
+				dpo_pipe[pipe3] <= dpo_pipe[pipe3+1];
+			end
+			dpo_pipe[dpo_pipe_stages] <= dpo_async;
+		end
+		else if((doclk === 1'bx && lastdoclk === 1'b0) || (doclk === 1'b1 && lastdoclk === 1'bx) || qdpo_ce_reg === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe4 = 2; pipe4 <= dpo_pipe_stages-1; pipe4 = pipe4 + 1)
+			begin
+				tmp_pipe3 = dpo_pipe[pipe4];
+				tmp_pipe2 = dpo_pipe[pipe4+1];
+				for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe3[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe3[pipe1] = 1'bx;
+				end
+				dpo_pipe[pipe4] <= tmp_pipe3;
+			end
+			tmp_pipe3 = dpo_pipe[dpo_pipe_stages];
+			for(pipe2 = 0; pipe2 < C_WIDTH; pipe2 = pipe2 + 1)
+			begin
+				if(tmp_pipe3[pipe2] !== dpo_async[pipe2])
+					tmp_pipe3[pipe2] = 1'bx;
+			end
+			dpo_pipe[dpo_pipe_stages] <= tmp_pipe3;
+		end
+	end
+  
+	always@(dpo_async or dpo_pipe[NCELAB_DPO_PIPE_CONSTANT])	//2
+	begin
+		if(dpo_pipe_stages < 2) // No pipeline
+			dpo_pipeend <= dpo_async;
+		else // Pipeline stages required
+		begin
+			dpo_pipeend <= dpo_pipe[NCELAB_DPO_PIPE_CONSTANT];	//2
+		end
+	end
+
+	// (Optional) output registers at end of optional pipelines
+	
+    C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_QSPO_RST, 0, 0,
+                           1, C_HAS_QSPO_SRST, 0, 0,
+                           "0", C_SYNC_ENABLE, 0, C_WIDTH)
+                qspo_reg (.D(spo_pipeend), .CLK(CLK), .CE(qspo_ce_reg), .ASET(1'b0),
+			  .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .ACLR(qspo_rst_int), .SCLR(qspo_srst_int), .Q(intQSPO));
+  
+    C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_QDPO_RST, 0, 0,
+                           1, C_HAS_QDPO_SRST, 0, 0,
+                           "0", C_SYNC_ENABLE, 0, C_WIDTH)
+                qdpo_reg (.D(dpo_pipeend), .CLK(doclk), .CE(qdpo_ce_reg), .ASET(1'b0),
+			  .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .ACLR(qdpo_rst_int), .SCLR(qdpo_srst_int), .Q(intQDPO));
+  
+	
+       
+  // Startup behaviour  
+  initial
+  begin
+    default_data = 'b0;
+    case (radix)
+       3 : default_data = decstr_conv(C_DEFAULT_DATA);
+       2 : default_data = binstr_conv(C_DEFAULT_DATA);
+       1 : default_data = hexstr_conv(C_DEFAULT_DATA);
+      default : $display("ERROR in %m at %d ns: BAD DATA RADIX - valid range 1 to 3", $time);
+    endcase
+
+    for(i = 0; i < C_DEPTH; i = i + 1)
+      ram_data[i] = default_data;
+    
+    if(C_READ_MIF == 1)
+    begin
+      $readmemb(C_MEM_INIT_FILE, ram_data, 0 , C_DEPTH-1);
+    end
+    if (C_GENERATE_MIF == 1)
+      write_meminit_file;
+	  
+	spo_tmp = 'b0;
+	dpo_tmp = 'b0;
+	lastCLK = 1'b0;
+	lastdoclk = 1'b0;
+	
+	for(i = 0; i < pipe_stages+3; i = i + 1)
+	begin
+		spo_pipe[i] = `all0s;
+	end
+	for(i = 0; i < dpo_pipe_stages+3; i = i + 1)
+	begin
+		dpo_pipe[i] = `all0s;
+	end
+	if(pipe_stages < 2) // No pipeline
+	begin
+		spo_pipeend = spo_async;
+	end
+	else
+	begin
+		spo_pipeend = spo_pipe[NCELAB_SPO_PIPE_CONSTANT];	//2
+	end
+    if(dpo_pipe_stages < 2) // No pipeline
+	begin
+		dpo_pipeend = dpo_async;
+	end
+	else
+	begin
+		dpo_pipeend = dpo_pipe[NCELAB_DPO_PIPE_CONSTANT];	//2
+	end
+  end
+  
+  always @(CLK)
+  	lastCLK <= CLK;
+	
+  always @(doclk)
+  	lastdoclk <= doclk;
+
+  always @(posedge CLK or a_int or we_int or spra_int or dpra_int or d_int or re_int)
+  begin
+  	if(((CLK === 1'b1 && lastCLK === 1'b0) || C_HAS_CLK == 0) && C_MEM_TYPE != `c_rom)
+	begin
+		if(ADDR_IS_X(a_int) || a_int < C_DEPTH)
+		begin
+			if(we_int === 1'bx)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+			else if(we_int === 1'b1)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							ram_data[i] = ram_data[i-1];
+						end
+						ram_data[srl_start] = d_int;
+					end
+					else
+					begin 			
+                        //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1)
+                        //begin
+                        //    $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time);
+                        //end
+						ram_data[a_int] = d_int;
+					end
+				end
+			end
+		end
+		else if(a_int >= C_DEPTH)
+			$display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH);
+	end
+	else if((C_HAS_CLK == 0 || ((CLK === 1'bx && lastCLK === 1'b0) || CLK === 1'b1 && lastCLK === 1'bx)) && C_MEM_TYPE != `c_rom)
+	begin
+		if(ADDR_IS_X(a_int) || a_int < C_DEPTH)
+		begin
+			if(we_int === 1'bx)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+			else if(we_int === 1'b1)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin 			
+                        //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1)
+                        //begin
+                        //    $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time);
+                        //end
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+		end
+		else if(a_int >= C_DEPTH)
+			$display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH);
+	end
+	
+  // Read behaviour
+	
+  	if(re_int === 1'bx)
+	begin
+		spo_tmp = `allXs;
+		dpo_tmp = `allXs;
+	end
+	else if(re_int === 1'b1)
+	begin
+		if(ADDR_IS_X(spra_int))
+			spo_tmp = `allXs;
+		else
+		begin
+			if(spra_int < C_DEPTH)
+				spo_tmp = ram_data[spra_int];
+			else if(C_MUX_TYPE == `c_buft_based)
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+			 	spo_tmp = `allZs;
+			end
+			else
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+				spo_tmp = `all0s;
+			end
+		end
+		
+		if(ADDR_IS_X(dpra_int))
+			dpo_tmp = `allXs;
+		else
+		begin
+			if(dpra_int < C_DEPTH)
+				dpo_tmp = ram_data[dpra_int];
+			else if(C_MUX_TYPE == `c_buft_based)
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+			 	dpo_tmp = `allZs;
+			end
+			else
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+				dpo_tmp = `all0s;
+			end
+		end
+	end
+	else // re_int == 0
+	begin
+		spo_tmp = `allZs;
+		dpo_tmp = `allZs;
+	end
+	
+	spo_async <= spo_tmp;
+	dpo_async <= dpo_tmp;  
+	
+  end
+  
+
+  function [C_WIDTH-1:0] binstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i;
+
+    begin
+      index = 0;
+      binstr_conv = 'b0;
+
+      for( i=C_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 : i = -1;
+          8'b00110000 : binstr_conv[index] = 1'b0;
+          8'b00110001 : binstr_conv[index] = 1'b1;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time);
+            binstr_conv[index] = 1'bx;
+          end
+        endcase
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  function [C_WIDTH-1:0] hexstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = 'b0;
+      for( i=C_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          8'b01100001 : bin = 4'b1010;
+          8'b01100010 : bin = 4'b1011;
+          8'b01100011 : bin = 4'b1100;
+          8'b01100100 : bin = 4'b1101;
+          8'b01100101 : bin = 4'b1110;
+          8'b01100110 : bin = 4'b1111;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A HEX CHARACTER", $time);
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  function [C_WIDTH-1:0] decstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j,ten;
+    reg [3:0] bin;
+	reg [C_WIDTH-1:0] temp, result;
+
+    begin
+      index = 0;
+      decstr_conv = 'b0;
+	  result = 'b0;
+      for( i=0; i<C_WIDTH; i=i+1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = C_WIDTH;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A DECIMAL CHARACTER", $time);
+            bin = 4'bx;
+          end
+        endcase
+        ten = 1;
+		for (j= 0; j< index; j=j+1)
+			ten = 10*ten;
+		temp = bin * ten;
+		result = result + temp;
+		decstr_conv = result;
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+  
+  task write_meminit_file;
+  
+    integer addrs, outfile, bit_index;
+    
+    reg [C_WIDTH-1 : 0] conts;
+    reg anyX;
+    
+    begin
+      outfile = $fopen(C_MEM_INIT_FILE);
+      for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1)
+      begin
+        anyX = 1'b0;
+        conts = ram_data[addrs];
+        for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1)
+          if(conts[bit_index] === 1'bx) anyX = 1'b1;
+        if(anyX == 1'b1)  
+          $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time);
+        $fdisplay(outfile,"%b",ram_data[addrs]);
+      end
+      $fclose(outfile);
+    end
+  endtask
+
+endmodule
+
+`undef all0s
+`undef all1s
+`undef allXs
+`undef allZs
+`undef addrallXs
+
+`undef c_rom
+`undef c_sp_ram
+`undef c_dp_ram
+`undef c_srl16
+
+`undef c_lut_based
+`undef c_buft_based
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V7_0.v

@@ -0,0 +1,944 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Revision: 1.13 $ $Date: 2008/09/08 20:06:53 $
+--
+-- Filename - C_DIST_MEM_V7_0.v
+-- Author - Xilinx
+-- Creation - 24 Mar 1999
+--
+-- Description
+--  Distributed RAM Simulation Model
+*/
+
+
+`timescale 1ns/10ps
+`define all0s 'b0
+`define all1s {C_WIDTH{1'b1}}
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+`define addrallXs {C_ADDR_WIDTH{1'bx}}
+
+`define c_rom 0
+`define c_sp_ram 1
+`define c_dp_ram 2
+`define c_srl16 3
+
+`define c_lut_based 0
+`define c_buft_based 1
+
+module C_DIST_MEM_V7_0 (A, D, DPRA, SPRA, CLK, WE, I_CE, RD_EN, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO);
+
+  parameter C_ADDR_WIDTH     = 6;
+  parameter C_DEFAULT_DATA   = "0";
+  parameter C_DEFAULT_DATA_RADIX = 1;
+  parameter C_DEPTH          = 64;
+  parameter C_ENABLE_RLOCS   = 1;
+  parameter C_GENERATE_MIF   = 0;
+  parameter C_HAS_CLK        = 1;
+  parameter C_HAS_D          = 1;
+  parameter C_HAS_DPO        = 0;
+  parameter C_HAS_DPRA       = 0;
+  parameter C_HAS_I_CE       = 0;
+  parameter C_HAS_QDPO       = 0;
+  parameter C_HAS_QDPO_CE    = 0;
+  parameter C_HAS_QDPO_CLK   = 0;
+  parameter C_HAS_QDPO_RST   = 0;    // RSTB
+  parameter C_HAS_QDPO_SRST  = 0;
+  parameter C_HAS_QSPO       = 0;
+  parameter C_HAS_QSPO_CE    = 0;
+  parameter C_HAS_QSPO_RST   = 0;    // RSTA
+  parameter C_HAS_QSPO_SRST  = 0;
+  parameter C_HAS_RD_EN      = 0;
+  parameter C_HAS_SPO        = 1;
+  parameter C_HAS_SPRA       = 0;
+  parameter C_HAS_WE         = 1;
+  parameter C_LATENCY    = 0;
+  parameter C_MEM_INIT_FILE  = "null.mif";
+  parameter C_MEM_TYPE       = 1; // c_sp_ram
+  parameter C_MUX_TYPE       = 0; // c_lut_based
+  parameter C_QCE_JOINED     = 0;
+  parameter C_QUALIFY_WE     = 0;
+  parameter C_READ_MIF       = 0;
+  parameter C_REG_A_D_INPUTS = 0;
+  parameter C_REG_DPRA_INPUT = 0;
+  parameter C_SYNC_ENABLE	 = 0;
+  parameter C_WIDTH          = 16;
+  parameter radix = C_DEFAULT_DATA_RADIX;
+  parameter pipe_stages = C_LATENCY-C_REG_A_D_INPUTS;
+  parameter dpo_pipe_stages = pipe_stages+1-C_HAS_QSPO;	// replaced C_HAS_QDPO for 1 as this parameter is only valid when C_HAS_QDPO anyway
+  parameter C_RAM32_FIX      = 0;	// should not be passed in to simulation model
+
+  parameter NCELAB_DPO_PIPE_CONSTANT = (dpo_pipe_stages < 2 ? 0 : 2);
+  parameter NCELAB_SPO_PIPE_CONSTANT = (pipe_stages < 2 ? 0 : 2);
+
+  input  [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A;
+  input  [C_WIDTH-1 : 0] D;
+  input  [C_ADDR_WIDTH-1 : 0] DPRA;
+  input  [C_ADDR_WIDTH-1 : 0] SPRA;
+  input  CLK;
+  input  WE;
+  input  I_CE;
+  input  RD_EN;
+  input  QSPO_CE;
+  input  QDPO_CE;
+  input  QDPO_CLK;
+  input  QSPO_RST;
+  input  QDPO_RST;
+  input  QSPO_SRST;
+  input  QDPO_SRST;
+  output [C_WIDTH-1 : 0] SPO;
+  output [C_WIDTH-1 : 0] QSPO;
+  output [C_WIDTH-1 : 0] DPO;
+  output [C_WIDTH-1 : 0] QDPO;
+
+	// Address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] a_int;
+	// Read Address signal connected to srl16-based memory
+	wire [C_ADDR_WIDTH - 1 : 0] spra_int;
+	// Registered Address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] a_int1;
+	// Registered Read Address signal connected to srl16-based memory
+	wire [C_ADDR_WIDTH - 1 : 0] spra_int1;
+	// DP port address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] dpra_int;
+	// DP port address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] dpra_int1;
+	// Input data signal connected to memory
+	wire [C_WIDTH - 1 : 0] d_int;
+	// Registered Input data signal connected to memory
+	wire [C_WIDTH - 1 : 0] d_int1;
+ 	// DP output register clock
+ 	wire doclk;
+    // Input data/address/WE register Clock Enable
+	wire ice;
+	// Special address register Clock Enable for ROMs
+	wire a_reg_ice;
+ 	// DP read address port register clock enable
+// 	wire dpra_ce;
+	// WE wire connected to memory
+	wire we_int;
+	// Registered WE wire connected to memory
+	wire we_int1;
+	// Clock enable for the WE register
+	wire wece;
+	// Read Enable wire connected to BUFT-type output mux
+	wire re_int;
+	// Registered Read Enable wire connected to BUFT-type output mux
+	wire re_int1;
+	// unregistered version of qspo_ce
+	wire qspo_ce_int;
+	// possibly registered version of qspo_ce
+	wire qspo_ce_reg;
+	// registered version of qspo_ce
+	wire qspo_ce_reg1;
+	// unregistered version of qdpo_ce
+	wire qdpo_ce_int;
+	// possibly registered version of qdpo_ce
+	wire qdpo_ce_reg;
+	// registered version of qdpo_ce
+	wire qdpo_ce_reg1;
+	// possibly single port registered output reset
+        wire qspo_rst_int;
+        // possibly dual port registered output reset
+        wire qdpo_rst_int;
+	// possibly single port registered output sync reset
+        wire qspo_srst_int;
+        // possibly dual port registered output sync reset
+        wire qdpo_srst_int;
+	// Direct SP output from memory
+	reg [C_WIDTH - 1 : 0] spo_async;
+	// Direct DP output from memory
+	reg [C_WIDTH - 1 : 0] dpo_async;
+	// Possibly pipelined and/or registered SP output from memory
+	wire [C_WIDTH - 1 : 0] intQSPO;
+	// Possibly pipelined and/or registered DP output from memory
+	wire [C_WIDTH - 1 : 0] intQDPO;
+	// Pipeline signals
+ 	reg [C_WIDTH - 1 : 0] spo_pipe [pipe_stages+2 : 0];
+ 	reg [C_WIDTH - 1 : 0] dpo_pipe [dpo_pipe_stages+2 : 0];
+	// Possibly pipelined SP output from memory
+ 	reg [C_WIDTH - 1 : 0] spo_pipeend;
+	// Possibly pipelined DP output from memory
+ 	reg [C_WIDTH - 1 : 0] dpo_pipeend;
+    // BUFT outputs
+    wire [C_WIDTH - 1 : 0] spo_reg;
+    wire [C_WIDTH - 1 : 0] dpo_reg;
+    wire [C_WIDTH - 1 : 0] spo_reg_tmp;
+    wire [C_WIDTH - 1 : 0] dpo_reg_tmp;
+
+	integer pipe, pipe1, pipe2, pipe3, pipe4, i, j, srl_start, srl_end;
+	
+	// Array to hold ram data
+	reg [C_WIDTH-1 : 0] ram_data [C_DEPTH-1 : 0];
+	reg [C_WIDTH-1 : 0] tmp_data1;
+	reg [C_WIDTH-1 : 0] tmp_data2;
+		
+	reg [C_WIDTH-1 : 0] default_data;
+	reg [C_WIDTH-1 : 0] spo_tmp;
+	reg [C_WIDTH-1 : 0] dpo_tmp;
+	reg [C_WIDTH-1 : 0] tmp_pipe1;
+	reg [C_WIDTH-1 : 0] tmp_pipe2;
+	reg [C_WIDTH-1 : 0] tmp_pipe3;
+	reg lastCLK;
+	reg lastdoclk;
+
+    reg start;
+    
+  function integer ADDR_IS_X;
+    input [C_ADDR_WIDTH-1 : 0] value;
+    integer i;
+  begin
+    ADDR_IS_X = 0;
+    for(i = 0; i < C_ADDR_WIDTH; i = i + 1)
+      if(value[i] === 1'bx)
+        ADDR_IS_X = 1;
+  end
+  endfunction
+  
+  // Deal with the optional output signals...
+  wire [C_WIDTH - 1 : 0] SPO = (C_HAS_SPO ? (C_MUX_TYPE == `c_lut_based ? spo_async : spo_reg) : `allXs);
+  wire [C_WIDTH - 1 : 0] DPO = (C_HAS_DPO && C_MEM_TYPE == `c_dp_ram ? (C_MUX_TYPE == `c_lut_based ? dpo_async : dpo_reg) : `allXs);
+  wire [C_WIDTH - 1 : 0] QSPO = (C_HAS_QSPO ? intQSPO : `allXs);
+  wire [C_WIDTH - 1 : 0] QDPO = (C_HAS_QDPO ? intQDPO : `allXs);
+  
+  // Deal with the optional input signals...
+  
+  assign ice = (C_HAS_I_CE == 1 ? I_CE : 1'b1);
+  assign a_reg_ice = (C_MEM_TYPE == `c_rom ? qspo_ce_int : ice);
+  assign wece = (C_HAS_WE == 1 && C_REG_A_D_INPUTS == 1 && C_QUALIFY_WE == 1 ? ice : 1'b1);
+//  assign dpra_ce = (C_HAS_QDPO_CE == 1  ? QDPO_CE : 1'b1);
+  assign doclk = (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK);
+  assign qspo_ce_int = (C_HAS_QSPO_CE == 1 ? QSPO_CE : 1'b1);
+  assign qdpo_ce_int = (C_QCE_JOINED == 1 ? qspo_ce_int : (C_HAS_QDPO_CE == 1 ? QDPO_CE : ((C_HAS_QSPO == 1 && C_MEM_TYPE == `c_srl16) ? qspo_ce_int : 1'b1))); 
+  assign qspo_rst_int = (C_HAS_QSPO_RST && C_HAS_QSPO ? QSPO_RST : 1'b0);
+  assign qdpo_rst_int = (C_HAS_QDPO_RST && C_HAS_QDPO ? QDPO_RST : 1'b0);
+  assign qspo_srst_int = (C_HAS_QSPO_SRST && C_HAS_QSPO ? QSPO_SRST : 1'b0);
+  assign qdpo_srst_int = (C_HAS_QDPO_SRST && C_HAS_QDPO ? QDPO_SRST : 1'b0);
+  
+  // (Optional) registers on SP address and on optional data/we/qspo_ce signals
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                qspo1_reg (.D(qspo_ce_int), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+			  .Q(qspo_ce_reg1));
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, (C_ADDR_WIDTH-(C_ADDR_WIDTH>4?(C_HAS_SPRA*4):0)))
+                a_rega (.D(A[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]), .CLK(CLK), .CE(a_reg_ice), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(a_int1[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]));
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_ADDR_WIDTH)
+                spra_reg (.D(SPRA), .CLK(CLK), .CE(qspo_ce_int), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(spra_int1));
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, 1)
+                we_reg (.D(WE), .CLK(CLK), .CE(wece), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(we_int1));
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                re_reg (.D(RD_EN), .CLK(CLK),// .CE(qspo_ce_int),
+                 .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(re_int1));                          
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	d_reg (.D(D), .CLK(CLK), .CE(ice), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(d_int1));                          
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	spo_reg1 (.D(spo_async), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(spo_reg_tmp));                          
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	dpo_reg1 (.D(dpo_async), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(dpo_reg_tmp));
+						   
+  // Deal with these optional registers
+  assign qspo_ce_reg = (C_REG_A_D_INPUTS == 0 ? (C_HAS_QSPO_CE == 1 ? qspo_ce_int : 1'b1) : (C_HAS_QSPO_CE == 1 ? qspo_ce_reg1 : 1'b1));
+  assign a_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : (C_ADDR_WIDTH>4 ? A[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)) : 
+  										  (C_MEM_TYPE != `c_srl16 ? a_int1 : (C_ADDR_WIDTH>4 ? a_int1[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)));
+  assign spra_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : SPRA) : 
+                                          (C_MEM_TYPE != `c_srl16 ? a_int1 : spra_int1));
+  assign we_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_WE == 1 ? WE : 1'b1) : (C_HAS_WE == 1 ? we_int1 : 1'b1));
+  assign re_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_RD_EN == 1 ? RD_EN : 1'b1) : (C_HAS_RD_EN == 1 ? re_int1 : 1'b1));
+  assign d_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_D == 1 ? D : `allXs) : (C_HAS_D == 1 ? d_int1 : `allXs));
+  assign spo_reg = (pipe_stages == 1 ? spo_reg_tmp : spo_async);
+  assign dpo_reg = (pipe_stages == 1 ? dpo_reg_tmp : dpo_async);
+  
+  // (Optional) DP Read Address and QDPO_CE registers
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_ADDR_WIDTH)
+                dpra_reg (.D(DPRA), .CLK(doclk), .CE(qdpo_ce_int), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(dpra_int1));
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                qdpo1_reg (.D(qdpo_ce_int), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(qdpo_ce_reg1));
+  
+  // Deal with these optional registers
+  assign qdpo_ce_reg = (C_REG_DPRA_INPUT == 0 ? (C_HAS_QDPO_CE == 1 ? qdpo_ce_int : (C_QCE_JOINED == 1 ? qdpo_ce_int : 1'b1)) : 
+  												(C_HAS_QDPO_CE == 1 ? qdpo_ce_reg1 : (C_QCE_JOINED == 1 || C_MEM_TYPE == `c_srl16 ? qdpo_ce_reg1 : 1'b1)));
+  assign dpra_int = (C_REG_DPRA_INPUT == 0 ? (C_HAS_DPRA == 1 ? DPRA : `allXs) : (C_HAS_DPRA == 1 ? dpra_int1 : `allXs));
+
+  // (Optional) pipeline registers
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && qspo_ce_reg === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1)
+			begin
+				spo_pipe[pipe] <= spo_pipe[pipe+1];
+			end
+			spo_pipe[pipe_stages] <= spo_async;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || qspo_ce_reg === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1)
+			begin
+				tmp_pipe1 = spo_pipe[pipe];
+				tmp_pipe2 = spo_pipe[pipe+1];
+				for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				spo_pipe[pipe] <= tmp_pipe1;
+			end
+			tmp_pipe1 = spo_pipe[pipe_stages];
+			for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== spo_async[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			spo_pipe[pipe_stages] <= tmp_pipe1;
+		end
+	end
+  
+	always@(spo_async or spo_pipe[NCELAB_SPO_PIPE_CONSTANT])	//2
+	begin
+		if(pipe_stages < 2) // No pipeline
+			spo_pipeend <= spo_async;
+		else // Pipeline stages required
+		begin
+			spo_pipeend <= spo_pipe[NCELAB_SPO_PIPE_CONSTANT];	//2
+		end
+	end
+       
+	always@(posedge doclk)
+	begin
+		if(doclk === 1'b1 && lastdoclk === 1'b0 && qdpo_ce_reg === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe3 = 2; pipe3 <= dpo_pipe_stages-1; pipe3 = pipe3 + 1)
+			begin
+				dpo_pipe[pipe3] <= dpo_pipe[pipe3+1];
+			end
+			dpo_pipe[dpo_pipe_stages] <= dpo_async;
+		end
+		else if((doclk === 1'bx && lastdoclk === 1'b0) || (doclk === 1'b1 && lastdoclk === 1'bx) || qdpo_ce_reg === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe4 = 2; pipe4 <= dpo_pipe_stages-1; pipe4 = pipe4 + 1)
+			begin
+				tmp_pipe3 = dpo_pipe[pipe4];
+				tmp_pipe2 = dpo_pipe[pipe4+1];
+				for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe3[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe3[pipe1] = 1'bx;
+				end
+				dpo_pipe[pipe4] <= tmp_pipe3;
+			end
+			tmp_pipe3 = dpo_pipe[dpo_pipe_stages];
+			for(pipe2 = 0; pipe2 < C_WIDTH; pipe2 = pipe2 + 1)
+			begin
+				if(tmp_pipe3[pipe2] !== dpo_async[pipe2])
+					tmp_pipe3[pipe2] = 1'bx;
+			end
+			dpo_pipe[dpo_pipe_stages] <= tmp_pipe3;
+		end
+	end
+  
+	always@(dpo_async or dpo_pipe[NCELAB_DPO_PIPE_CONSTANT])	//2
+	begin
+		if(dpo_pipe_stages < 2) // No pipeline
+			dpo_pipeend <= dpo_async;
+		else // Pipeline stages required
+		begin
+			dpo_pipeend <= dpo_pipe[NCELAB_DPO_PIPE_CONSTANT];	//2
+		end
+	end
+
+	// (Optional) output registers at end of optional pipelines
+	
+    C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_QSPO_RST, 0, 0,
+                           1, C_HAS_QSPO_SRST, 0, 0,
+                           "0", C_SYNC_ENABLE, 0, C_WIDTH)
+                qspo_reg (.D(spo_pipeend), .CLK(CLK), .CE(qspo_ce_reg), .ASET(1'b0),
+			  .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .ACLR(qspo_rst_int), .SCLR(qspo_srst_int), .Q(intQSPO));
+  
+    C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_QDPO_RST, 0, 0,
+                           1, C_HAS_QDPO_SRST, 0, 0,
+                           "0", C_SYNC_ENABLE, 0, C_WIDTH)
+                qdpo_reg (.D(dpo_pipeend), .CLK(doclk), .CE(qdpo_ce_reg), .ASET(1'b0),
+			  .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .ACLR(qdpo_rst_int), .SCLR(qdpo_srst_int), .Q(intQDPO));
+  
+	
+       
+  // Startup behaviour  
+  initial
+  begin
+    default_data = 'b0;
+    case (radix)
+       3 : default_data = decstr_conv(C_DEFAULT_DATA);
+       2 : default_data = binstr_conv(C_DEFAULT_DATA);
+       1 : default_data = hexstr_conv(C_DEFAULT_DATA);
+      default : $display("ERROR in %m at %d ns: BAD DATA RADIX - valid range 1 to 3", $time);
+    endcase
+
+    for(i = 0; i < C_DEPTH; i = i + 1)
+      ram_data[i] = default_data;
+    
+    if(C_READ_MIF == 1)
+    begin
+      $readmemb(C_MEM_INIT_FILE, ram_data, 0 , C_DEPTH-1);
+    end
+    if (C_GENERATE_MIF == 1)
+      write_meminit_file;
+	  
+	spo_tmp = 'b0;
+	dpo_tmp = 'b0;
+	lastCLK = 1'b0;
+	lastdoclk = 1'b0;
+	
+	spo_async = spo_tmp;
+	dpo_async = dpo_tmp;
+	
+	for(i = 0; i < pipe_stages+3; i = i + 1)
+	begin
+		spo_pipe[i] = `all0s;
+	end
+	for(i = 0; i < dpo_pipe_stages+3; i = i + 1)
+	begin
+		dpo_pipe[i] = `all0s;
+	end
+	if(pipe_stages < 2) // No pipeline
+	begin
+		spo_pipeend = spo_async;
+	end
+	else
+	begin
+		spo_pipeend = spo_pipe[NCELAB_SPO_PIPE_CONSTANT];	//2
+	end
+    if(dpo_pipe_stages < 2) // No pipeline
+	begin
+		dpo_pipeend = dpo_async;
+	end
+	else
+	begin
+		dpo_pipeend = dpo_pipe[NCELAB_DPO_PIPE_CONSTANT];	//2
+	end
+
+    start <= 0;
+  end
+  
+  always @(CLK)
+  	lastCLK <= CLK;
+	
+  always @(doclk)
+  	lastdoclk <= doclk;
+
+  always @(posedge CLK or a_int or we_int or spra_int or dpra_int or d_int or re_int or spo_async or dpo_async or start)
+  begin
+  	if ($realtime != 0 || start == 0)	// gets around race condition at startup (CR 171445)
+	                                    // added start to ensure that this process is still run at startup
+										// but after all the intials have completed to fix CR 175826
+	begin
+  	if(((CLK === 1'b1 && lastCLK === 1'b0) || C_HAS_CLK == 0) && C_MEM_TYPE != `c_rom)
+	begin
+		if(ADDR_IS_X(a_int) || a_int < C_DEPTH)
+		begin
+			if(we_int === 1'bx)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+			else if(we_int === 1'b1)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							ram_data[i] = ram_data[i-1];
+						end
+						ram_data[srl_start] = d_int;
+					end
+					else
+					begin 			
+                        //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1)
+                        //begin
+                        //    $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time);
+                        //end
+						ram_data[a_int] = d_int;
+					end
+				end
+			end
+		end
+		else if(a_int >= C_DEPTH)
+			$display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH);
+	end
+	else if((C_HAS_CLK == 0 || ((CLK === 1'bx && lastCLK === 1'b0) || CLK === 1'b1 && lastCLK === 1'bx)) && C_MEM_TYPE != `c_rom)
+	begin
+		if(ADDR_IS_X(a_int) || a_int < C_DEPTH)
+		begin
+			if(we_int === 1'bx)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+			else if(we_int === 1'b1)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin 			
+                        //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1)
+                        //begin
+                        //    $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time);
+                        //end
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+		end
+		else if(a_int >= C_DEPTH)
+			$display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH);
+	end
+	
+  // Read behaviour
+	
+  	if(re_int === 1'bx)
+	begin
+		spo_tmp = `allXs;
+		dpo_tmp = `allXs;
+	end
+	else if(re_int === 1'b1)
+	begin
+		if(ADDR_IS_X(spra_int))
+			spo_tmp = `allXs;
+		else
+		begin
+			if(spra_int < C_DEPTH)
+				spo_tmp = ram_data[spra_int];
+			else if(C_MUX_TYPE == `c_buft_based)
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+			 	spo_tmp = `allZs;
+			end
+			else
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+				spo_tmp = `all0s;
+			end
+		end
+		
+		if(ADDR_IS_X(dpra_int))
+			dpo_tmp = `allXs;
+		else
+		begin
+			if(dpra_int < C_DEPTH)
+				dpo_tmp = ram_data[dpra_int];
+			else if(C_MUX_TYPE == `c_buft_based)
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+			 	dpo_tmp = `allZs;
+			end
+			else
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+				dpo_tmp = `all0s;
+			end
+		end
+	end
+	else // re_int == 0
+	begin
+		spo_tmp = `all1s;
+		dpo_tmp = `all1s;
+	end
+	
+	spo_async <= spo_tmp;
+	dpo_async <= dpo_tmp;  
+	end
+	
+  end
+  
+
+  function [C_WIDTH-1:0] binstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i;
+
+    begin
+      index = 0;
+      binstr_conv = 'b0;
+
+      for( i=C_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 : i = -1;
+          8'b00110000 : binstr_conv[index] = 1'b0;
+          8'b00110001 : binstr_conv[index] = 1'b1;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time);
+            binstr_conv[index] = 1'bx;
+          end
+        endcase
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  function [C_WIDTH-1:0] hexstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = 'b0;
+      for( i=C_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          8'b01100001 : bin = 4'b1010;
+          8'b01100010 : bin = 4'b1011;
+          8'b01100011 : bin = 4'b1100;
+          8'b01100100 : bin = 4'b1101;
+          8'b01100101 : bin = 4'b1110;
+          8'b01100110 : bin = 4'b1111;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A HEX CHARACTER", $time);
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  function [C_WIDTH-1:0] decstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j,ten;
+    reg [3:0] bin;
+	reg [C_WIDTH-1:0] temp, result;
+
+    begin
+      index = 0;
+      decstr_conv = 'b0;
+	  result = 'b0;
+      for( i=0; i<C_WIDTH; i=i+1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = C_WIDTH;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A DECIMAL CHARACTER", $time);
+            bin = 4'bx;
+          end
+        endcase
+        ten = 1;
+		for (j= 0; j< index; j=j+1)
+			ten = 10*ten;
+		temp = bin * ten;
+		result = result + temp;
+		decstr_conv = result;
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+  
+  task write_meminit_file;
+  
+    integer addrs, outfile, bit_index;
+    
+    reg [C_WIDTH-1 : 0] conts;
+    reg anyX;
+    
+    begin
+      outfile = $fopen(C_MEM_INIT_FILE);
+      for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1)
+      begin
+        anyX = 1'b0;
+        conts = ram_data[addrs];
+        for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1)
+          if(conts[bit_index] === 1'bx) anyX = 1'b1;
+        if(anyX == 1'b1)  
+          $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time);
+        $fdisplay(outfile,"%b",ram_data[addrs]);
+      end
+      $fclose(outfile);
+    end
+  endtask
+
+endmodule
+
+`undef all0s
+`undef all1s
+`undef allXs
+`undef allZs
+`undef addrallXs
+
+`undef c_rom
+`undef c_sp_ram
+`undef c_dp_ram
+`undef c_srl16
+
+`undef c_lut_based
+`undef c_buft_based
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V7_1.v

@@ -0,0 +1,944 @@
+// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Revision: 1.12 $ $Date: 2008/09/08 20:06:54 $
+--
+-- Filename - C_DIST_MEM_V7_1.v
+-- Author - Xilinx
+-- Creation - 24 Mar 1999
+--
+-- Description
+--  Distributed RAM Simulation Model
+*/
+
+
+`timescale 1ns/10ps
+`define all0s 'b0
+`define all1s {C_WIDTH{1'b1}}
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+`define addrallXs {C_ADDR_WIDTH{1'bx}}
+
+`define c_rom 0
+`define c_sp_ram 1
+`define c_dp_ram 2
+`define c_srl16 3
+
+`define c_lut_based 0
+`define c_buft_based 1
+
+module C_DIST_MEM_V7_1 (A, D, DPRA, SPRA, CLK, WE, I_CE, RD_EN, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO);
+
+  parameter C_ADDR_WIDTH     = 6;
+  parameter C_DEFAULT_DATA   = "0";
+  parameter C_DEFAULT_DATA_RADIX = 1;
+  parameter C_DEPTH          = 64;
+  parameter C_ENABLE_RLOCS   = 1;
+  parameter C_GENERATE_MIF   = 0;
+  parameter C_HAS_CLK        = 1;
+  parameter C_HAS_D          = 1;
+  parameter C_HAS_DPO        = 0;
+  parameter C_HAS_DPRA       = 0;
+  parameter C_HAS_I_CE       = 0;
+  parameter C_HAS_QDPO       = 0;
+  parameter C_HAS_QDPO_CE    = 0;
+  parameter C_HAS_QDPO_CLK   = 0;
+  parameter C_HAS_QDPO_RST   = 0;    // RSTB
+  parameter C_HAS_QDPO_SRST  = 0;
+  parameter C_HAS_QSPO       = 0;
+  parameter C_HAS_QSPO_CE    = 0;
+  parameter C_HAS_QSPO_RST   = 0;    // RSTA
+  parameter C_HAS_QSPO_SRST  = 0;
+  parameter C_HAS_RD_EN      = 0;
+  parameter C_HAS_SPO        = 1;
+  parameter C_HAS_SPRA       = 0;
+  parameter C_HAS_WE         = 1;
+  parameter C_LATENCY    = 0;
+  parameter C_MEM_INIT_FILE  = "null.mif";
+  parameter C_MEM_TYPE       = 1; // c_sp_ram
+  parameter C_MUX_TYPE       = 0; // c_lut_based
+  parameter C_QCE_JOINED     = 0;
+  parameter C_QUALIFY_WE     = 0;
+  parameter C_READ_MIF       = 0;
+  parameter C_REG_A_D_INPUTS = 0;
+  parameter C_REG_DPRA_INPUT = 0;
+  parameter C_SYNC_ENABLE	 = 0;
+  parameter C_WIDTH          = 16;
+  parameter radix = C_DEFAULT_DATA_RADIX;
+  parameter pipe_stages = C_LATENCY-C_REG_A_D_INPUTS;
+  parameter dpo_pipe_stages = pipe_stages+1-C_HAS_QSPO;	// replaced C_HAS_QDPO for 1 as this parameter is only valid when C_HAS_QDPO anyway
+  parameter C_RAM32_FIX      = 0;	// should not be passed in to simulation model
+
+  parameter NCELAB_DPO_PIPE_CONSTANT = (dpo_pipe_stages < 2 ? 0 : 2);
+  parameter NCELAB_SPO_PIPE_CONSTANT = (pipe_stages < 2 ? 0 : 2);
+
+  input  [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A;
+  input  [C_WIDTH-1 : 0] D;
+  input  [C_ADDR_WIDTH-1 : 0] DPRA;
+  input  [C_ADDR_WIDTH-1 : 0] SPRA;
+  input  CLK;
+  input  WE;
+  input  I_CE;
+  input  RD_EN;
+  input  QSPO_CE;
+  input  QDPO_CE;
+  input  QDPO_CLK;
+  input  QSPO_RST;
+  input  QDPO_RST;
+  input  QSPO_SRST;
+  input  QDPO_SRST;
+  output [C_WIDTH-1 : 0] SPO;
+  output [C_WIDTH-1 : 0] QSPO;
+  output [C_WIDTH-1 : 0] DPO;
+  output [C_WIDTH-1 : 0] QDPO;
+
+	// Address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] a_int;
+	// Read Address signal connected to srl16-based memory
+	wire [C_ADDR_WIDTH - 1 : 0] spra_int;
+	// Registered Address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] a_int1;
+	// Registered Read Address signal connected to srl16-based memory
+	wire [C_ADDR_WIDTH - 1 : 0] spra_int1;
+	// DP port address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] dpra_int;
+	// DP port address signal connected to memory
+	wire [C_ADDR_WIDTH - 1 : 0] dpra_int1;
+	// Input data signal connected to memory
+	wire [C_WIDTH - 1 : 0] d_int;
+	// Registered Input data signal connected to memory
+	wire [C_WIDTH - 1 : 0] d_int1;
+ 	// DP output register clock
+ 	wire doclk;
+    // Input data/address/WE register Clock Enable
+	wire ice;
+	// Special address register Clock Enable for ROMs
+	wire a_reg_ice;
+ 	// DP read address port register clock enable
+// 	wire dpra_ce;
+	// WE wire connected to memory
+	wire we_int;
+	// Registered WE wire connected to memory
+	wire we_int1;
+	// Clock enable for the WE register
+	wire wece;
+	// Read Enable wire connected to BUFT-type output mux
+	wire re_int;
+	// Registered Read Enable wire connected to BUFT-type output mux
+	wire re_int1;
+	// unregistered version of qspo_ce
+	wire qspo_ce_int;
+	// possibly registered version of qspo_ce
+	wire qspo_ce_reg;
+	// registered version of qspo_ce
+	wire qspo_ce_reg1;
+	// unregistered version of qdpo_ce
+	wire qdpo_ce_int;
+	// possibly registered version of qdpo_ce
+	wire qdpo_ce_reg;
+	// registered version of qdpo_ce
+	wire qdpo_ce_reg1;
+	// possibly single port registered output reset
+        wire qspo_rst_int;
+        // possibly dual port registered output reset
+        wire qdpo_rst_int;
+	// possibly single port registered output sync reset
+        wire qspo_srst_int;
+        // possibly dual port registered output sync reset
+        wire qdpo_srst_int;
+	// Direct SP output from memory
+	reg [C_WIDTH - 1 : 0] spo_async;
+	// Direct DP output from memory
+	reg [C_WIDTH - 1 : 0] dpo_async;
+	// Possibly pipelined and/or registered SP output from memory
+	wire [C_WIDTH - 1 : 0] intQSPO;
+	// Possibly pipelined and/or registered DP output from memory
+	wire [C_WIDTH - 1 : 0] intQDPO;
+	// Pipeline signals
+ 	reg [C_WIDTH - 1 : 0] spo_pipe [pipe_stages+2 : 0];
+ 	reg [C_WIDTH - 1 : 0] dpo_pipe [dpo_pipe_stages+2 : 0];
+	// Possibly pipelined SP output from memory
+ 	reg [C_WIDTH - 1 : 0] spo_pipeend;
+	// Possibly pipelined DP output from memory
+ 	reg [C_WIDTH - 1 : 0] dpo_pipeend;
+    // BUFT outputs
+    wire [C_WIDTH - 1 : 0] spo_reg;
+    wire [C_WIDTH - 1 : 0] dpo_reg;
+    wire [C_WIDTH - 1 : 0] spo_reg_tmp;
+    wire [C_WIDTH - 1 : 0] dpo_reg_tmp;
+
+	integer pipe, pipe1, pipe2, pipe3, pipe4, i, j, srl_start, srl_end;
+	
+	// Array to hold ram data
+	reg [C_WIDTH-1 : 0] ram_data [C_DEPTH-1 : 0];
+	reg [C_WIDTH-1 : 0] tmp_data1;
+	reg [C_WIDTH-1 : 0] tmp_data2;
+		
+	reg [C_WIDTH-1 : 0] default_data;
+	reg [C_WIDTH-1 : 0] spo_tmp;
+	reg [C_WIDTH-1 : 0] dpo_tmp;
+	reg [C_WIDTH-1 : 0] tmp_pipe1;
+	reg [C_WIDTH-1 : 0] tmp_pipe2;
+	reg [C_WIDTH-1 : 0] tmp_pipe3;
+	reg lastCLK;
+	reg lastdoclk;
+
+    reg start;
+    
+  function integer ADDR_IS_X;
+    input [C_ADDR_WIDTH-1 : 0] value;
+    integer i;
+  begin
+    ADDR_IS_X = 0;
+    for(i = 0; i < C_ADDR_WIDTH; i = i + 1)
+      if(value[i] === 1'bx)
+        ADDR_IS_X = 1;
+  end
+  endfunction
+  
+  // Deal with the optional output signals...
+  wire [C_WIDTH - 1 : 0] SPO = (C_HAS_SPO ? (C_MUX_TYPE == `c_lut_based ? spo_async : spo_reg) : `allXs);
+  wire [C_WIDTH - 1 : 0] DPO = (C_HAS_DPO && C_MEM_TYPE == `c_dp_ram ? (C_MUX_TYPE == `c_lut_based ? dpo_async : dpo_reg) : `allXs);
+  wire [C_WIDTH - 1 : 0] QSPO = (C_HAS_QSPO ? intQSPO : `allXs);
+  wire [C_WIDTH - 1 : 0] QDPO = (C_HAS_QDPO ? intQDPO : `allXs);
+  
+  // Deal with the optional input signals...
+  
+  assign ice = (C_HAS_I_CE == 1 ? I_CE : 1'b1);
+  assign a_reg_ice = (C_MEM_TYPE == `c_rom ? qspo_ce_int : ice);
+  assign wece = (C_HAS_WE == 1 && C_REG_A_D_INPUTS == 1 && C_QUALIFY_WE == 1 ? ice : 1'b1);
+//  assign dpra_ce = (C_HAS_QDPO_CE == 1  ? QDPO_CE : 1'b1);
+  assign doclk = (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK);
+  assign qspo_ce_int = (C_HAS_QSPO_CE == 1 ? QSPO_CE : 1'b1);
+  assign qdpo_ce_int = (C_QCE_JOINED == 1 ? qspo_ce_int : (C_HAS_QDPO_CE == 1 ? QDPO_CE : ((C_HAS_QSPO == 1 && C_MEM_TYPE == `c_srl16) ? qspo_ce_int : 1'b1))); 
+  assign qspo_rst_int = (C_HAS_QSPO_RST && C_HAS_QSPO ? QSPO_RST : 1'b0);
+  assign qdpo_rst_int = (C_HAS_QDPO_RST && C_HAS_QDPO ? QDPO_RST : 1'b0);
+  assign qspo_srst_int = (C_HAS_QSPO_SRST && C_HAS_QSPO ? QSPO_SRST : 1'b0);
+  assign qdpo_srst_int = (C_HAS_QDPO_SRST && C_HAS_QDPO ? QDPO_SRST : 1'b0);
+  
+  // (Optional) registers on SP address and on optional data/we/qspo_ce signals
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                qspo1_reg (.D(qspo_ce_int), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+			  .Q(qspo_ce_reg1));
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, (C_ADDR_WIDTH-(C_ADDR_WIDTH>4?(C_HAS_SPRA*4):0)))
+                a_rega (.D(A[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]), .CLK(CLK), .CE(a_reg_ice), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(a_int1[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]));
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_ADDR_WIDTH)
+                spra_reg (.D(SPRA), .CLK(CLK), .CE(qspo_ce_int), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(spra_int1));
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, 1)
+                we_reg (.D(WE), .CLK(CLK), .CE(wece), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(we_int1));
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                re_reg (.D(RD_EN), .CLK(CLK),// .CE(qspo_ce_int),
+                 .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(re_int1));                          
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	d_reg (.D(D), .CLK(CLK), .CE(ice), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(d_int1));                          
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	spo_reg1 (.D(spo_async), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(spo_reg_tmp));                          
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, C_WIDTH)
+                	dpo_reg1 (.D(dpo_async), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                           .Q(dpo_reg_tmp));
+						   
+  // Deal with these optional registers
+  assign qspo_ce_reg = (C_REG_A_D_INPUTS == 0 ? (C_HAS_QSPO_CE == 1 ? qspo_ce_int : 1'b1) : (C_HAS_QSPO_CE == 1 ? qspo_ce_reg1 : 1'b1));
+  assign a_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : (C_ADDR_WIDTH>4 ? A[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)) : 
+  										  (C_MEM_TYPE != `c_srl16 ? a_int1 : (C_ADDR_WIDTH>4 ? a_int1[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)));
+  assign spra_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : SPRA) : 
+                                          (C_MEM_TYPE != `c_srl16 ? a_int1 : spra_int1));
+  assign we_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_WE == 1 ? WE : 1'b1) : (C_HAS_WE == 1 ? we_int1 : 1'b1));
+  assign re_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_RD_EN == 1 ? RD_EN : 1'b1) : (C_HAS_RD_EN == 1 ? re_int1 : 1'b1));
+  assign d_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_D == 1 ? D : `allXs) : (C_HAS_D == 1 ? d_int1 : `allXs));
+  assign spo_reg = (pipe_stages == 1 ? spo_reg_tmp : spo_async);
+  assign dpo_reg = (pipe_stages == 1 ? dpo_reg_tmp : dpo_async);
+  
+  // (Optional) DP Read Address and QDPO_CE registers
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           1, 0, 0, 0,
+                           "0", 0, 0, C_ADDR_WIDTH)
+                dpra_reg (.D(DPRA), .CLK(doclk), .CE(qdpo_ce_int), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(dpra_int1));
+  
+  C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0,
+                           0, 0, 0, 0,
+                           "0", 0, 0, 1)
+                qdpo1_reg (.D(qdpo_ce_int), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0),
+			  .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .Q(qdpo_ce_reg1));
+  
+  // Deal with these optional registers
+  assign qdpo_ce_reg = (C_REG_DPRA_INPUT == 0 ? (C_HAS_QDPO_CE == 1 ? qdpo_ce_int : (C_QCE_JOINED == 1 ? qdpo_ce_int : 1'b1)) : 
+  												(C_HAS_QDPO_CE == 1 ? qdpo_ce_reg1 : (C_QCE_JOINED == 1 || C_MEM_TYPE == `c_srl16 ? qdpo_ce_reg1 : 1'b1)));
+  assign dpra_int = (C_REG_DPRA_INPUT == 0 ? (C_HAS_DPRA == 1 ? DPRA : `allXs) : (C_HAS_DPRA == 1 ? dpra_int1 : `allXs));
+
+  // (Optional) pipeline registers
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && qspo_ce_reg === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1)
+			begin
+				spo_pipe[pipe] <= spo_pipe[pipe+1];
+			end
+			spo_pipe[pipe_stages] <= spo_async;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || qspo_ce_reg === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1)
+			begin
+				tmp_pipe1 = spo_pipe[pipe];
+				tmp_pipe2 = spo_pipe[pipe+1];
+				for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe1[pipe1] = 1'bx;
+				end
+				spo_pipe[pipe] <= tmp_pipe1;
+			end
+			tmp_pipe1 = spo_pipe[pipe_stages];
+			for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+			begin
+				if(tmp_pipe1[pipe1] !== spo_async[pipe1])
+					tmp_pipe1[pipe1] = 1'bx;
+			end
+			spo_pipe[pipe_stages] <= tmp_pipe1;
+		end
+	end
+  
+	always@(spo_async or spo_pipe[NCELAB_SPO_PIPE_CONSTANT])	//2
+	begin
+		if(pipe_stages < 2) // No pipeline
+			spo_pipeend <= spo_async;
+		else // Pipeline stages required
+		begin
+			spo_pipeend <= spo_pipe[NCELAB_SPO_PIPE_CONSTANT];	//2
+		end
+	end
+       
+	always@(posedge doclk)
+	begin
+		if(doclk === 1'b1 && lastdoclk === 1'b0 && qdpo_ce_reg === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe3 = 2; pipe3 <= dpo_pipe_stages-1; pipe3 = pipe3 + 1)
+			begin
+				dpo_pipe[pipe3] <= dpo_pipe[pipe3+1];
+			end
+			dpo_pipe[dpo_pipe_stages] <= dpo_async;
+		end
+		else if((doclk === 1'bx && lastdoclk === 1'b0) || (doclk === 1'b1 && lastdoclk === 1'bx) || qdpo_ce_reg === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe4 = 2; pipe4 <= dpo_pipe_stages-1; pipe4 = pipe4 + 1)
+			begin
+				tmp_pipe3 = dpo_pipe[pipe4];
+				tmp_pipe2 = dpo_pipe[pipe4+1];
+				for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1)
+				begin
+					if(tmp_pipe3[pipe1] !== tmp_pipe2[pipe1])
+						tmp_pipe3[pipe1] = 1'bx;
+				end
+				dpo_pipe[pipe4] <= tmp_pipe3;
+			end
+			tmp_pipe3 = dpo_pipe[dpo_pipe_stages];
+			for(pipe2 = 0; pipe2 < C_WIDTH; pipe2 = pipe2 + 1)
+			begin
+				if(tmp_pipe3[pipe2] !== dpo_async[pipe2])
+					tmp_pipe3[pipe2] = 1'bx;
+			end
+			dpo_pipe[dpo_pipe_stages] <= tmp_pipe3;
+		end
+	end
+  
+	always@(dpo_async or dpo_pipe[NCELAB_DPO_PIPE_CONSTANT])	//2
+	begin
+		if(dpo_pipe_stages < 2) // No pipeline
+			dpo_pipeend <= dpo_async;
+		else // Pipeline stages required
+		begin
+			dpo_pipeend <= dpo_pipe[NCELAB_DPO_PIPE_CONSTANT];	//2
+		end
+	end
+
+	// (Optional) output registers at end of optional pipelines
+	
+    C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_QSPO_RST, 0, 0,
+                           1, C_HAS_QSPO_SRST, 0, 0,
+                           "0", C_SYNC_ENABLE, 0, C_WIDTH)
+                qspo_reg (.D(spo_pipeend), .CLK(CLK), .CE(qspo_ce_reg), .ASET(1'b0),
+			  .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .ACLR(qspo_rst_int), .SCLR(qspo_srst_int), .Q(intQSPO));
+  
+    C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_QDPO_RST, 0, 0,
+                           1, C_HAS_QDPO_SRST, 0, 0,
+                           "0", C_SYNC_ENABLE, 0, C_WIDTH)
+                qdpo_reg (.D(dpo_pipeend), .CLK(doclk), .CE(qdpo_ce_reg), .ASET(1'b0),
+			  .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0),
+                          .ACLR(qdpo_rst_int), .SCLR(qdpo_srst_int), .Q(intQDPO));
+  
+	
+       
+  // Startup behaviour  
+  initial
+  begin
+    default_data = 'b0;
+    case (radix)
+       3 : default_data = decstr_conv(C_DEFAULT_DATA);
+       2 : default_data = binstr_conv(C_DEFAULT_DATA);
+       1 : default_data = hexstr_conv(C_DEFAULT_DATA);
+      default : $display("ERROR in %m at %d ns: BAD DATA RADIX - valid range 1 to 3", $time);
+    endcase
+
+    for(i = 0; i < C_DEPTH; i = i + 1)
+      ram_data[i] = default_data;
+    
+    if(C_READ_MIF == 1)
+    begin
+      $readmemb(C_MEM_INIT_FILE, ram_data, 0 , C_DEPTH-1);
+    end
+    if (C_GENERATE_MIF == 1)
+      write_meminit_file;
+	  
+	spo_tmp = 'b0;
+	dpo_tmp = 'b0;
+	lastCLK = 1'b0;
+	lastdoclk = 1'b0;
+	
+	spo_async = spo_tmp;
+	dpo_async = dpo_tmp;
+	
+	for(i = 0; i < pipe_stages+3; i = i + 1)
+	begin
+		spo_pipe[i] = `all0s;
+	end
+	for(i = 0; i < dpo_pipe_stages+3; i = i + 1)
+	begin
+		dpo_pipe[i] = `all0s;
+	end
+	if(pipe_stages < 2) // No pipeline
+	begin
+		spo_pipeend = spo_async;
+	end
+	else
+	begin
+		spo_pipeend = spo_pipe[NCELAB_SPO_PIPE_CONSTANT];	//2
+	end
+    if(dpo_pipe_stages < 2) // No pipeline
+	begin
+		dpo_pipeend = dpo_async;
+	end
+	else
+	begin
+		dpo_pipeend = dpo_pipe[NCELAB_DPO_PIPE_CONSTANT];	//2
+	end
+
+    start <= 0;
+  end
+  
+  always @(CLK)
+  	lastCLK <= CLK;
+	
+  always @(doclk)
+  	lastdoclk <= doclk;
+
+  always @(posedge CLK or a_int or we_int or spra_int or dpra_int or d_int or re_int or spo_async or dpo_async or start)
+  begin
+  	if ($realtime != 0 || start == 0)	// gets around race condition at startup (CR 171445)
+	                                    // added start to ensure that this process is still run at startup
+										// but after all the intials have completed to fix CR 175826
+	begin
+  	if(((CLK === 1'b1 && lastCLK === 1'b0) || C_HAS_CLK == 0) && C_MEM_TYPE != `c_rom)
+	begin
+		if(ADDR_IS_X(a_int) || a_int < C_DEPTH)
+		begin
+			if(we_int === 1'bx)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+			else if(we_int === 1'b1)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							ram_data[i] = ram_data[i-1];
+						end
+						ram_data[srl_start] = d_int;
+					end
+					else
+					begin 			
+                        //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1)
+                        //begin
+                        //    $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time);
+                        //end
+						ram_data[a_int] = d_int;
+					end
+				end
+			end
+		end
+		else if(a_int >= C_DEPTH)
+			$display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH);
+	end
+	else if((C_HAS_CLK == 0 || ((CLK === 1'bx && lastCLK === 1'b0) || CLK === 1'b1 && lastCLK === 1'bx)) && C_MEM_TYPE != `c_rom)
+	begin
+		if(ADDR_IS_X(a_int) || a_int < C_DEPTH)
+		begin
+			if(we_int === 1'bx)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+			else if(we_int === 1'b1)
+			begin
+				if(ADDR_IS_X(a_int))
+				begin
+					for(i = 0; i < C_DEPTH; i = i + 1) 
+						ram_data[i] = `allXs;
+  				end
+				else 
+				begin
+					if(C_MEM_TYPE == `c_srl16)
+					begin
+						srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int
+						srl_end = srl_start+16;
+						if(srl_end > C_DEPTH)
+							srl_end = C_DEPTH;
+						for(i = srl_end-1; i > srl_start; i = i - 1)
+						begin // Shift data through the SRL16s
+							tmp_data1 = ram_data[i];
+							tmp_data2 = ram_data[i-1];
+							for(j = 0; j < C_WIDTH; j = j + 1)
+							begin
+								if(tmp_data1[j] !== tmp_data2[j])
+									tmp_data1[j] = 1'bx;
+							end
+							ram_data[i] = tmp_data1;
+						end
+						tmp_data1 = ram_data[srl_start];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[srl_start] = tmp_data1;
+					end
+					else
+					begin 			
+                        //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1)
+                        //begin
+                        //    $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time);
+                        //end
+						tmp_data1 = ram_data[a_int];
+						for(j = 0; j < C_WIDTH; j = j + 1)
+						begin
+							if(tmp_data1[j] !== d_int[j])
+								tmp_data1[j] = 1'bx;
+						end
+						ram_data[a_int] = tmp_data1;
+					end
+				end
+			end
+		end
+		else if(a_int >= C_DEPTH)
+			$display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH);
+	end
+	
+  // Read behaviour
+	
+  	if(re_int === 1'bx)
+	begin
+		spo_tmp = `allXs;
+		dpo_tmp = `allXs;
+	end
+	else if(re_int === 1'b1)
+	begin
+		if(ADDR_IS_X(spra_int))
+			spo_tmp = `allXs;
+		else
+		begin
+			if(spra_int < C_DEPTH)
+				spo_tmp = ram_data[spra_int];
+			else if(C_MUX_TYPE == `c_buft_based)
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+			 	spo_tmp = `allZs;
+			end
+			else
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+				spo_tmp = `all0s;
+			end
+		end
+		
+		if(ADDR_IS_X(dpra_int))
+			dpo_tmp = `allXs;
+		else
+		begin
+			if(dpra_int < C_DEPTH)
+				dpo_tmp = ram_data[dpra_int];
+			else if(C_MUX_TYPE == `c_buft_based)
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+			 	dpo_tmp = `allZs;
+			end
+			else
+			begin
+				$display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH);
+				dpo_tmp = `all0s;
+			end
+		end
+	end
+	else // re_int == 0
+	begin
+		spo_tmp = `all1s;
+		dpo_tmp = `all1s;
+	end
+	
+	spo_async <= spo_tmp;
+	dpo_async <= dpo_tmp;  
+	end
+	
+  end
+  
+
+  function [C_WIDTH-1:0] binstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i;
+
+    begin
+      index = 0;
+      binstr_conv = 'b0;
+
+      for( i=C_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 : i = -1;
+          8'b00110000 : binstr_conv[index] = 1'b0;
+          8'b00110001 : binstr_conv[index] = 1'b1;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time);
+            binstr_conv[index] = 1'bx;
+          end
+        endcase
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  function [C_WIDTH-1:0] hexstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = 'b0;
+      for( i=C_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          8'b01100001 : bin = 4'b1010;
+          8'b01100010 : bin = 4'b1011;
+          8'b01100011 : bin = 4'b1100;
+          8'b01100100 : bin = 4'b1101;
+          8'b01100101 : bin = 4'b1110;
+          8'b01100110 : bin = 4'b1111;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A HEX CHARACTER", $time);
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  function [C_WIDTH-1:0] decstr_conv;
+    input [(C_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j,ten;
+    reg [3:0] bin;
+	reg [C_WIDTH-1:0] temp, result;
+
+    begin
+      index = 0;
+      decstr_conv = 'b0;
+	  result = 'b0;
+      for( i=0; i<C_WIDTH; i=i+1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = C_WIDTH;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          default :
+          begin
+            $display("ERROR in %m at time %d ns: NOT A DECIMAL CHARACTER", $time);
+            bin = 4'bx;
+          end
+        endcase
+        ten = 1;
+		for (j= 0; j< index; j=j+1)
+			ten = 10*ten;
+		temp = bin * ten;
+		result = result + temp;
+		decstr_conv = result;
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+  
+  task write_meminit_file;
+  
+    integer addrs, outfile, bit_index;
+    
+    reg [C_WIDTH-1 : 0] conts;
+    reg anyX;
+    
+    begin
+      outfile = $fopen(C_MEM_INIT_FILE);
+      for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1)
+      begin
+        anyX = 1'b0;
+        conts = ram_data[addrs];
+        for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1)
+          if(conts[bit_index] === 1'bx) anyX = 1'b1;
+        if(anyX == 1'b1)  
+          $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time);
+        $fdisplay(outfile,"%b",ram_data[addrs]);
+      end
+      $fclose(outfile);
+    end
+  endtask
+
+endmodule
+
+`undef all0s
+`undef all1s
+`undef allXs
+`undef allZs
+`undef addrallXs
+
+`undef c_rom
+`undef c_sp_ram
+`undef c_dp_ram
+`undef c_srl16
+
+`undef c_lut_based
+`undef c_buft_based
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V4_0.v

@@ -0,0 +1,538 @@
+/* $Id: C_GATE_BIT_BUS_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_GATE_BIT_BUS_V4_0.v
+-- Author - Xilinx
+-- Creation - 25 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_BUS_V4_0 module
+*/
+
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+
+module C_GATE_BIT_BUS_V4_0 (I, CTRL, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUT_INV_MASK 	= "";
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_WIDTH 			= 16; 			
+	
+
+	input [C_WIDTH-1 : 0] I;
+	input CTRL;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+	wire [C_WIDTH-1 : 0] intQ;
+	
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}});
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}});
+	
+	
+	integer j;
+	
+	reg [C_WIDTH-1 : 0] tmpsig;
+	reg [C_WIDTH-1 : 0] tmpres;
+	
+	// Output register
+	C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+		#1;
+		
+		tmpsig = to_bits(C_INPUT_INV_MASK);
+		if(CTRL === 1'bx)
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1) // Inversion of input bit
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+			end
+		end
+		else // CTRL is not unknown
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1)
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & ~I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & ~I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | ~I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | ~I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ ~I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ ~I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+			end
+		end
+					
+		intO <= tmpres;
+	end
+	
+	always@(I or CTRL) 
+	begin
+		
+		if(CTRL === 1'bx)
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1) // Inversion of input bit
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+			end
+		end
+		else // CTRL is not unknown
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1)
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & ~I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & ~I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | ~I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | ~I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ ~I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ ~I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+			end
+		end
+					
+		intO <= #1 tmpres;
+	end
+
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V5_0.v

@@ -0,0 +1,539 @@
+/* $Id: C_GATE_BIT_BUS_V5_0.v,v 1.17 2008/09/08 20:05:55 akennedy Exp $
+--
+-- Filename - C_GATE_BIT_BUS_V5_0.v
+-- Author - Xilinx
+-- Creation - 25 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_BUS_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+
+module C_GATE_BIT_BUS_V5_0 (I, CTRL, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUT_INV_MASK 	= "";
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_WIDTH 			= 16; 			
+	
+
+	input [C_WIDTH-1 : 0] I;
+	input CTRL;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+	wire [C_WIDTH-1 : 0] intQ;
+	
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}});
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}});
+	
+	
+	integer j;
+	
+	reg [C_WIDTH-1 : 0] tmpsig;
+	reg [C_WIDTH-1 : 0] tmpres;
+	
+	// Output register
+	C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+		#1;
+		
+		tmpsig = to_bits(C_INPUT_INV_MASK);
+		if(CTRL === 1'bx)
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1) // Inversion of input bit
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+			end
+		end
+		else // CTRL is not unknown
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1)
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & ~I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & ~I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | ~I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | ~I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ ~I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ ~I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+			end
+		end
+					
+		intO <= tmpres;
+	end
+	
+	always@(I or CTRL) 
+	begin
+		
+		if(CTRL === 1'bx)
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1) // Inversion of input bit
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+			end
+		end
+		else // CTRL is not unknown
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1)
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & ~I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & ~I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | ~I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | ~I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ ~I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ ~I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+			end
+		end
+					
+		intO <= #1 tmpres;
+	end
+
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor
+
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V6_0.v

@@ -0,0 +1,548 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_GATE_BIT_BUS_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_GATE_BIT_BUS_V6_0.v
+-- Author - Xilinx
+-- Creation - 25 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_BUS_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+
+module C_GATE_BIT_BUS_V6_0 (I, CTRL, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUT_INV_MASK 	= "";
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_WIDTH 			= 16; 			
+	
+
+	input [C_WIDTH-1 : 0] I;
+	input CTRL;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+	wire [C_WIDTH-1 : 0] intQ;
+	
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}});
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}});
+	
+	
+	integer j;
+	
+	reg [C_WIDTH-1 : 0] tmpsig;
+	reg [C_WIDTH-1 : 0] tmpres;
+	
+	// Output register
+	C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+		#1;
+		
+		tmpsig = to_bits(C_INPUT_INV_MASK);
+		if(CTRL === 1'bx)
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1) // Inversion of input bit
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+			end
+		end
+		else // CTRL is not unknown
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1)
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & ~I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & ~I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | ~I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | ~I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ ~I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ ~I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+			end
+		end
+					
+		intO <= tmpres;
+	end
+	
+	always@(I or CTRL) 
+	begin
+		
+		if(CTRL === 1'bx)
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1) // Inversion of input bit
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+			end
+		end
+		else // CTRL is not unknown
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1)
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & ~I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & ~I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | ~I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | ~I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ ~I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ ~I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+			end
+		end
+					
+		intO <= #1 tmpres;
+	end
+
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor
+
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V7_0.v

@@ -0,0 +1,577 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Id: C_GATE_BIT_BUS_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_GATE_BIT_BUS_V7_0.v
+-- Author - Xilinx
+-- Creation - 25 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_BUS_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+
+module C_GATE_BIT_BUS_V7_0 (I, CTRL, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUT_INV_MASK 	= "";
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_WIDTH 			= 16; 			
+	
+
+	input [C_WIDTH-1 : 0] I;
+	input CTRL;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+	wire [C_WIDTH-1 : 0] intQ;
+	
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}});
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}});
+	
+	
+	integer j;
+	
+	reg [C_WIDTH-1 : 0] tmpsig;
+	reg [C_WIDTH-1 : 0] tmpres;
+	
+	// Output register
+	C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+		#1;
+		
+		tmpsig = to_bits(C_INPUT_INV_MASK);
+		if(CTRL === 1'bx)
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1) // Inversion of input bit
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+			end
+		end
+		else // CTRL is not unknown
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1)
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & ~I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & ~I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | ~I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | ~I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ ~I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ ~I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+			end
+		end
+					
+		intO <= tmpres;
+	end
+	
+	always@(I or CTRL) 
+	begin
+		
+		if(CTRL === 1'bx)
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1) // Inversion of input bit
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+						tmpres[j] = 1'bx;
+					else if(C_GATE_TYPE == 5) // XNOR gate
+						tmpres[j] = 1'bx;
+				end
+			end
+		end
+		else // CTRL is not unknown
+		begin
+			for(j = 0; j < C_WIDTH; j = j + 1)
+			begin
+				if(tmpsig[j] == 1)
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & ~I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & ~I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | ~I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | ~I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ ~I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ ~I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+				else // No input inversion on bit j of input	
+				begin
+					if(C_GATE_TYPE == 0) // AND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL & I[j];
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 1) // NAND gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL & I[j]);
+						else if(CTRL === 1'b0)
+							tmpres[j] = 1'b0;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 2) // OR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL | I[j];
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 3) // NOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL | I[j]);
+						else if(CTRL === 1'b1)
+							tmpres[j] = 1'b1;
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 4) // XOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = CTRL ^ I[j];
+						else
+							tmpres[j] = 1'bx;
+					end
+					else if(C_GATE_TYPE == 5) // XNOR gate
+					begin
+						if(I[j] !== 1'bx)
+							tmpres[j] = ~(CTRL ^ I[j]);
+						else
+							tmpres[j] = 1'bx;
+					end
+				end
+			end
+		end
+					
+		intO <= #1 tmpres;
+	end
+
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor
+
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V4_0.v

@@ -0,0 +1,418 @@
+/* $Id: C_GATE_BIT_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_GATE_BIT_V4_0.v
+-- Author - Xilinx
+-- Creation - 25 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V4_0 module
+*/
+
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+
+module C_GATE_BIT_V4_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_ENABLE_RLOCS	= 0;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUTS 			= 2; 	
+	parameter C_INPUT_INV_MASK 	= "";
+	parameter C_PIPE_STAGES 	= 0;    
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	
+
+	input [C_INPUTS-1 : 0] I;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output O;
+	output Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	reg intO;
+	wire intQ;
+	reg lastCLK;
+	
+	reg [C_PIPE_STAGES+2 : 0] intQpipe; 
+	reg intQpipeend;
+	 
+	wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);
+	wire O = (C_HAS_O == 1 ? intO : 1'bx);
+	
+	// Sort out default values for missing ports
+	
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	
+	integer j;
+	integer pipe;
+
+	reg [C_INPUTS-1 : 0] tmpsig;
+	reg tmpres;
+	
+	// Output register
+	C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+			  
+	initial 
+	begin
+	
+		#1;
+	
+		intQpipe = 'b0;
+		
+		if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
+			tmpres = 1;
+		else
+			tmpres = 0;
+			
+		tmpsig = to_bits(C_INPUT_INV_MASK);
+		
+		for(j = 0; j < C_INPUTS; j = j + 1)
+		begin
+			if(tmpsig[j] == 1)
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+			else // No input inversion on bit j of input	
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+			end
+		end
+		
+		if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5)
+			tmpres = ~tmpres;
+		
+		intO <= tmpres;
+
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend = intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend = intQpipe[2];
+		end
+	end
+	
+	always @(CLK)
+  		lastCLK <= CLK;
+
+	always@(I) 
+	begin
+		if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
+			tmpres = 1;
+		else
+			tmpres = 0;
+		for(j = 0; j < C_INPUTS; j = j + 1)
+		begin
+			if(tmpsig[j] == 1)
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+			else // No input inversion on bit j of input	
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+			end
+		end
+		
+		if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5)
+			tmpres = ~tmpres;
+		
+		intO <= #1 tmpres;
+	end
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				intQpipe[pipe] <= intQpipe[pipe+1];
+			end
+			intQpipe[C_PIPE_STAGES] <= intO;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				if(intQpipe[pipe] !== intQpipe[pipe+1])
+					intQpipe[pipe] <= 1'bx;
+			end
+			if(intQpipe[C_PIPE_STAGES] !== intO)
+				intQpipe[C_PIPE_STAGES] <= 1'bx;
+		end
+	end
+	
+	always@(intO or intQpipe[2])
+	begin
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend <= intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend <= intQpipe[2];
+		end
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_INPUTS - 1 : 0] to_bits;
+	input [C_INPUTS*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_INPUTS; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V5_0.v

@@ -0,0 +1,550 @@
+/* $Id: C_GATE_BIT_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $
+--
+-- Filename - C_GATE_BIT_V5_0.v
+-- Author - Xilinx
+-- Creation - 25 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+
+module C_GATE_BIT_V5_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, T, EN, O, Q);
+
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_ENABLE_RLOCS	= 0;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUTS 			= 2; 	
+	parameter C_INPUT_INV_MASK 	= "";
+	parameter C_PIPE_STAGES 	= 0;    
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	
+
+	input [C_INPUTS-1 : 0] I;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input T;
+	input EN;
+	output O;
+	output Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	reg intO;
+	wire intQ;
+	reg lastCLK;
+	
+	reg [C_PIPE_STAGES+2 : 0] intQpipe; 
+	reg intQpipeend;
+	 
+	wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);
+	wire O = (C_HAS_O == 1 ? intO : 1'bx);
+	
+	// Sort out default values for missing ports
+	
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	
+	integer j;
+	integer pipe;
+
+	reg [C_INPUTS-1 : 0] tmpsig;
+	reg tmpres;
+	
+	// Output register
+	C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+			  
+	initial 
+	begin
+	
+		#1;
+	
+		intQpipe = 'b0;
+		
+		if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
+			tmpres = 1;
+		else
+			tmpres = 0;
+			
+		tmpsig = to_bits(C_INPUT_INV_MASK);
+		
+		for(j = 0; j < C_INPUTS; j = j + 1)
+		begin
+			if(tmpsig[j] == 1)
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+			else // No input inversion on bit j of input	
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+                        if (T == 0)
+    						tmpres = I[j];
+                        else
+                            tmpres = 1'b1;
+					else 
+						tmpres = 1'b1;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !== 1'bx)
+                        if (EN == 0)
+    						tmpres = I[j];
+                        else
+                            tmpres = 1'b1;
+					else 
+						tmpres = 1'b1;
+				end
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+		end
+		
+		if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6)
+			tmpres = ~tmpres;
+		
+		intO <= tmpres;
+
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend = intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend = intQpipe[2];
+		end
+	end
+	
+	always @(CLK)
+  		lastCLK <= CLK;
+
+	always@(I or T or EN) 
+	begin
+		if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
+			tmpres = 1;
+		else
+			tmpres = 0;
+		for(j = 0; j < C_INPUTS; j = j + 1)
+		begin
+			if(tmpsig[j] == 1)
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7 ) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+                        if (T == 0)
+    						tmpres = ~I[j];
+                        else 
+                            tmpres = 1'b1;
+                    else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !==  1'bx)
+                        if (EN == 0)
+						tmpres = ~I[j];
+                        else 
+                        tmpres = 1'b1;
+					else 
+						tmpres = 1'bx;
+                end
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+			else // No input inversion on bit j of input	
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+                        if (T == 0)
+       						tmpres = I[j];
+	                    else 
+	                        tmpres = 1'b1;
+    				else 
+						tmpres = 1'b1;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !== 1'bx)
+                        if (EN == 0)
+       						tmpres = I[j];
+	                    else 
+	                        tmpres = 1'b1;
+    				else 
+						tmpres = 1'b1;
+				end
+
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+		end
+		
+		if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6)
+			tmpres = ~tmpres;
+		
+		intO <= #1 tmpres;
+	end
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				intQpipe[pipe] <= intQpipe[pipe+1];
+			end
+			intQpipe[C_PIPE_STAGES] <= intO;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				if(intQpipe[pipe] !== intQpipe[pipe+1])
+					intQpipe[pipe] <= 1'bx;
+			end
+			if(intQpipe[C_PIPE_STAGES] !== intO)
+				intQpipe[C_PIPE_STAGES] <= 1'bx;
+		end
+	end
+	
+	always@(intO or intQpipe[2])
+	begin
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend <= intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend <= intQpipe[2];
+		end
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_INPUTS - 1 : 0] to_bits;
+	input [C_INPUTS*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_INPUTS; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V6_0.v

@@ -0,0 +1,559 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_GATE_BIT_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_GATE_BIT_V6_0.v
+-- Author - Xilinx
+-- Creation - 25 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+
+module C_GATE_BIT_V6_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, T, EN, O, Q);
+
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_ENABLE_RLOCS	= 0;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUTS 			= 2; 	
+	parameter C_INPUT_INV_MASK 	= "";
+	parameter C_PIPE_STAGES 	= 0;    
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	
+
+	input [C_INPUTS-1 : 0] I;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input T;
+	input EN;
+	output O;
+	output Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	reg intO;
+	wire intQ;
+	reg lastCLK;
+	
+	reg [C_PIPE_STAGES+2 : 0] intQpipe; 
+	reg intQpipeend;
+	 
+	wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);
+	wire O = (C_HAS_O == 1 ? intO : 1'bx);
+	
+	// Sort out default values for missing ports
+	
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	
+	integer j;
+	integer pipe;
+
+	reg [C_INPUTS-1 : 0] tmpsig;
+	reg tmpres;
+	
+	// Output register
+	C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+			  
+	initial 
+	begin
+	
+//		#1;
+	
+		intQpipe = 'b0;
+		
+		if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
+			tmpres = 1;
+		else
+			tmpres = 0;
+			
+		tmpsig = to_bits(C_INPUT_INV_MASK);
+		
+		for(j = 0; j < C_INPUTS; j = j + 1)
+		begin
+			if(tmpsig[j] == 1)
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+			else // No input inversion on bit j of input	
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+                        if (T == 0)
+    						tmpres = I[j];
+                        else
+                            tmpres = 1'b1;
+					else 
+						tmpres = 1'b1;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !== 1'bx)
+                        if (EN == 0)
+    						tmpres = I[j];
+                        else
+                            tmpres = 1'b1;
+					else 
+						tmpres = 1'b1;
+				end
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+		end
+		
+		if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6)
+			tmpres = ~tmpres;
+		
+		intO <= tmpres;
+
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend = intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend = intQpipe[2];
+		end
+	end
+	
+	always @(CLK)
+  		lastCLK <= CLK;
+
+	always@(I or T or EN) 
+	begin
+		if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
+			tmpres = 1;
+		else
+			tmpres = 0;
+		for(j = 0; j < C_INPUTS; j = j + 1)
+		begin
+			if(tmpsig[j] == 1)
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7 ) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+                        if (T == 0)
+    						tmpres = ~I[j];
+                        else 
+                            tmpres = 1'b1;
+                    else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !==  1'bx)
+                        if (EN == 0)
+						tmpres = ~I[j];
+                        else 
+                        tmpres = 1'b1;
+					else 
+						tmpres = 1'bx;
+                end
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+			else // No input inversion on bit j of input	
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+                        if (T == 0)
+       						tmpres = I[j];
+	                    else 
+	                        tmpres = 1'b1;
+    				else 
+						tmpres = 1'b1;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !== 1'bx)
+                        if (EN == 0)
+       						tmpres = I[j];
+	                    else 
+	                        tmpres = 1'b1;
+    				else 
+						tmpres = 1'b1;
+				end
+
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+		end
+		
+		if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6)
+			tmpres = ~tmpres;
+		
+		intO <= #1 tmpres;
+	end
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				intQpipe[pipe] <= intQpipe[pipe+1];
+			end
+			intQpipe[C_PIPE_STAGES] <= intO;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				if(intQpipe[pipe] !== intQpipe[pipe+1])
+					intQpipe[pipe] <= 1'bx;
+			end
+			if(intQpipe[C_PIPE_STAGES] !== intO)
+				intQpipe[C_PIPE_STAGES] <= 1'bx;
+		end
+	end
+	
+	always@(intO or intQpipe[2])
+	begin
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend <= intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend <= intQpipe[2];
+		end
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_INPUTS - 1 : 0] to_bits;
+	input [C_INPUTS*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_INPUTS; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V7_0.v

@@ -0,0 +1,588 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Id: C_GATE_BIT_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_GATE_BIT_V7_0.v
+-- Author - Xilinx
+-- Creation - 25 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+
+module C_GATE_BIT_V7_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, T, EN, O, Q);
+
+	parameter C_AINIT_VAL 		= "0";
+	parameter C_ENABLE_RLOCS	= 0;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUTS 			= 2; 	
+	parameter C_INPUT_INV_MASK 	= "";
+	parameter C_PIPE_STAGES 	= 0;    
+	parameter C_SINIT_VAL 		= "0";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	
+
+	input [C_INPUTS-1 : 0] I;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	input T;
+	input EN;
+	output O;
+	output Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	reg intO;
+	wire intQ;
+	reg lastCLK;
+	
+	reg [C_PIPE_STAGES+2 : 0] intQpipe; 
+	reg intQpipeend;
+	 
+	wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);
+	wire O = (C_HAS_O == 1 ? intO : 1'bx);
+	
+	// Sort out default values for missing ports
+	
+	assign intCE = defval(CE, C_HAS_CE, 1);
+	
+	integer j;
+	integer pipe;
+
+	reg [C_INPUTS-1 : 0] tmpsig;
+	reg tmpres;
+	
+	// Output register
+	C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+			  
+	initial 
+	begin
+	
+//		#1;
+	
+		intQpipe = 'b0;
+		
+		if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
+			tmpres = 1;
+		else
+			tmpres = 0;
+			
+		tmpsig = to_bits(C_INPUT_INV_MASK);
+		
+		for(j = 0; j < C_INPUTS; j = j + 1)
+		begin
+			if(tmpsig[j] == 1)
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+			else // No input inversion on bit j of input	
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+                        if (T == 0)
+    						tmpres = I[j];
+                        else
+                            tmpres = 1'b1;
+					else 
+						tmpres = 1'b1;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !== 1'bx)
+                        if (EN == 0)
+    						tmpres = I[j];
+                        else
+                            tmpres = 1'b1;
+					else 
+						tmpres = 1'b1;
+				end
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+		end
+		
+		if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6)
+			tmpres = ~tmpres;
+		
+		intO <= tmpres;
+
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend = intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend = intQpipe[2];
+		end
+	end
+	
+	always @(CLK)
+  		lastCLK <= CLK;
+
+	always@(I or T or EN) 
+	begin
+		if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate?
+			tmpres = 1;
+		else
+			tmpres = 0;
+		for(j = 0; j < C_INPUTS; j = j + 1)
+		begin
+			if(tmpsig[j] == 1)
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & ~I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | ~I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7 ) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+                        if (T == 0)
+    						tmpres = ~I[j];
+                        else 
+                            tmpres = 1'b1;
+                    else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !==  1'bx)
+                        if (EN == 0)
+						tmpres = ~I[j];
+                        else 
+                        tmpres = 1'b1;
+					else 
+						tmpres = 1'bx;
+                end
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = ~I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+			else // No input inversion on bit j of input	
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres & I[j];
+					else if(tmpres === 1'b1)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres | I[j];
+					else if(tmpres === 1'b0)
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 4) // XOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+				else if(C_GATE_TYPE == 5) // XNOR gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = tmpres ^ I[j];
+					else
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 7) // Buffer
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+                else if(C_GATE_TYPE == 8) // BUFT
+				begin
+					if(I[j] !== 1'bx)
+                        if (T == 0)
+       						tmpres = I[j];
+	                    else 
+	                        tmpres = 1'b1;
+    				else 
+						tmpres = 1'b1;
+				end
+                else if(C_GATE_TYPE == 9) // BUFE
+				begin
+					if(I[j] !== 1'bx)
+                        if (EN == 0)
+       						tmpres = I[j];
+	                    else 
+	                        tmpres = 1'b1;
+    				else 
+						tmpres = 1'b1;
+				end
+
+                else  // INV gate
+				begin
+					if(I[j] !== 1'bx)
+						tmpres = I[j];
+					else 
+						tmpres = 1'bx;
+				end
+			end
+		end
+		
+		if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6)
+			tmpres = ~tmpres;
+		
+		intO <= #1 tmpres;
+	end
+
+	always@(posedge CLK)
+	begin
+		if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				intQpipe[pipe] <= intQpipe[pipe+1];
+			end
+			intQpipe[C_PIPE_STAGES] <= intO;
+		end
+		else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines!
+		begin
+			for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1)
+			begin
+				if(intQpipe[pipe] !== intQpipe[pipe+1])
+					intQpipe[pipe] <= 1'bx;
+			end
+			if(intQpipe[C_PIPE_STAGES] !== intO)
+				intQpipe[C_PIPE_STAGES] <= 1'bx;
+		end
+	end
+	
+	always@(intO or intQpipe[2])
+	begin
+		if(C_PIPE_STAGES < 2) // No pipeline
+			intQpipeend <= intO;
+		else // Pipeline stages required
+		begin
+			intQpipeend <= intQpipe[2];
+		end
+	end
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_INPUTS - 1 : 0] to_bits;
+	input [C_INPUTS*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_INPUTS; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V4_0.v

@@ -0,0 +1,365 @@
+/* $Id: C_GATE_BUS_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_GATE_BUS_V4_0.v
+-- Author - Xilinx
+-- Creation - 26 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BUS_V4_0 module
+*/
+
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+`define c_inv 6
+`define c_buf 7
+
+module C_GATE_BUS_V4_0 (IA, IB, IC, ID, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUTS 			= 2; 	
+	parameter C_INPUT_A_INV_MASK = "";
+	parameter C_INPUT_B_INV_MASK = "";
+	parameter C_INPUT_C_INV_MASK = "";
+	parameter C_INPUT_D_INV_MASK = "";
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_WIDTH 			= 16; 			
+	
+
+	input [C_WIDTH-1 : 0] IA;
+	input [C_WIDTH-1 : 0] IB;
+	input [C_WIDTH-1 : 0] IC;
+	input [C_WIDTH-1 : 0] ID;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	reg [C_WIDTH-1 : 0] intIA;
+	reg [C_WIDTH-1 : 0] intIB;
+	reg [C_WIDTH-1 : 0] intIC;
+	reg [C_WIDTH-1 : 0] intID;
+	reg [C_WIDTH-1 : 0] intO;
+	wire [C_WIDTH-1 : 0] intQ;
+		 
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}});
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}});
+		
+	
+	integer j;
+	
+	reg [C_WIDTH-1 : 0] tmpres;
+	
+	// Output register
+	C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+	
+		#1;
+		
+		if(C_INPUTS == 4) 
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			intID = ID ^ to_bits(C_INPUT_D_INV_MASK);
+		end
+		else if(C_INPUTS == 3)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				intID = {C_WIDTH{1'b1}};
+			else
+					intID = 'b0;
+		end
+		else if(C_INPUTS == 2)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+			begin
+				intIC = {C_WIDTH{1'b1}};
+				intID = {C_WIDTH{1'b1}};
+			end
+			else
+			begin
+				intIC = 'b0;
+				intID = 'b0;
+			end
+		end	
+		else // inv or buf gates
+		begin
+			intID = {C_WIDTH{1'b0}};
+			intIC = {C_WIDTH{1'b0}};
+			intIB = {C_WIDTH{1'b0}};
+			intIA = IA;
+		end
+					
+		for(j = 0; j < C_WIDTH; j = j + 1)
+		begin
+			if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx)
+			begin // Unknown's on at least one input
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE > 3) // other gate
+					tmpres[j] = 1'bx;
+			end
+			else
+			begin // No unknowns in inputs
+				if(C_GATE_TYPE == 0) // AND gate
+					tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j];
+				else if(C_GATE_TYPE == 1) // NAND gate
+					tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]);
+				else if(C_GATE_TYPE == 2) // OR gate
+					tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j];
+				else if(C_GATE_TYPE == 3) // NOR gate
+					tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]);
+				else if(C_GATE_TYPE == 4) // XOR gate
+					tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j];
+				else if(C_GATE_TYPE == 5) // XNOR gate
+					tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]);
+				else if(C_GATE_TYPE == 6) // INV gate
+					tmpres[j] = ~(intIA[j]);
+				else if(C_GATE_TYPE == 7) // BUF gate
+					tmpres[j] = intIA[j];
+			end
+		end
+		
+		intO <= tmpres;
+	end
+	
+	always@(IA or IB or IC or ID) 
+	begin
+		if(C_INPUTS == 4) 
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			intID = ID ^ to_bits(C_INPUT_D_INV_MASK);
+		end
+		else if(C_INPUTS == 3)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				intID = {C_WIDTH{1'b1}};
+			else
+				intID = 'b0;
+		end
+		else if(C_INPUTS == 2)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				begin
+				intIC = {C_WIDTH{1'b1}};
+				intID = {C_WIDTH{1'b1}};
+			end
+			else
+			begin
+				intIC = 'b0;
+				intID = 'b0;
+			end
+		end
+		else // inv or buf gates
+		begin
+			intID = {C_WIDTH{1'b0}};
+			intIC = {C_WIDTH{1'b0}};
+			intIB = {C_WIDTH{1'b0}};
+			intIA = IA;
+		end
+						
+		for(j = 0; j < C_WIDTH; j = j + 1)
+		begin
+			if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx)
+			begin // Unknown's on at least one input
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE > 3) // other gate
+					tmpres[j] = 1'bx;
+			end
+			else
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+					tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j];
+				else if(C_GATE_TYPE == 1) // NAND gate
+					tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]);
+				else if(C_GATE_TYPE == 2) // OR gate
+					tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j];
+				else if(C_GATE_TYPE == 3) // NOR gate
+					tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]);
+				else if(C_GATE_TYPE == 4) // XOR gate
+					tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j];
+				else if(C_GATE_TYPE == 5) // XNOR gate
+					tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]);
+				else if(C_GATE_TYPE == 6) // INV gate
+					tmpres[j] = ~(intIA[j]);
+				else if(C_GATE_TYPE == 7) // BUF gate
+					tmpres[j] = intIA[j];
+			end
+		end
+		
+		intO <= #1 tmpres;
+	end
+
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor
+`undef c_inv
+`undef c_buf
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V5_0.v

@@ -0,0 +1,365 @@
+/* $Id: C_GATE_BUS_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $
+--
+-- Filename - C_GATE_BUS_V5_0.v
+-- Author - Xilinx
+-- Creation - 26 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BUS_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+`define c_inv 6
+`define c_buf 7
+
+module C_GATE_BUS_V5_0 (IA, IB, IC, ID, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUTS 			= 2; 	
+	parameter C_INPUT_A_INV_MASK = "";
+	parameter C_INPUT_B_INV_MASK = "";
+	parameter C_INPUT_C_INV_MASK = "";
+	parameter C_INPUT_D_INV_MASK = "";
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_WIDTH 			= 16; 			
+	
+
+	input [C_WIDTH-1 : 0] IA;
+	input [C_WIDTH-1 : 0] IB;
+	input [C_WIDTH-1 : 0] IC;
+	input [C_WIDTH-1 : 0] ID;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	reg [C_WIDTH-1 : 0] intIA;
+	reg [C_WIDTH-1 : 0] intIB;
+	reg [C_WIDTH-1 : 0] intIC;
+	reg [C_WIDTH-1 : 0] intID;
+	reg [C_WIDTH-1 : 0] intO;
+	wire [C_WIDTH-1 : 0] intQ;
+		 
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}});
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}});
+		
+	
+	integer j;
+	
+	reg [C_WIDTH-1 : 0] tmpres;
+	
+	// Output register
+	C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+	
+		#1;
+		
+		if(C_INPUTS == 4) 
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			intID = ID ^ to_bits(C_INPUT_D_INV_MASK);
+		end
+		else if(C_INPUTS == 3)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				intID = {C_WIDTH{1'b1}};
+			else
+					intID = 'b0;
+		end
+		else if(C_INPUTS == 2)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+			begin
+				intIC = {C_WIDTH{1'b1}};
+				intID = {C_WIDTH{1'b1}};
+			end
+			else
+			begin
+				intIC = 'b0;
+				intID = 'b0;
+			end
+		end	
+		else // inv or buf gates
+		begin
+			intID = {C_WIDTH{1'b0}};
+			intIC = {C_WIDTH{1'b0}};
+			intIB = {C_WIDTH{1'b0}};
+			intIA = IA;
+		end
+					
+		for(j = 0; j < C_WIDTH; j = j + 1)
+		begin
+			if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx)
+			begin // Unknown's on at least one input
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE > 3) // other gate
+					tmpres[j] = 1'bx;
+			end
+			else
+			begin // No unknowns in inputs
+				if(C_GATE_TYPE == 0) // AND gate
+					tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j];
+				else if(C_GATE_TYPE == 1) // NAND gate
+					tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]);
+				else if(C_GATE_TYPE == 2) // OR gate
+					tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j];
+				else if(C_GATE_TYPE == 3) // NOR gate
+					tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]);
+				else if(C_GATE_TYPE == 4) // XOR gate
+					tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j];
+				else if(C_GATE_TYPE == 5) // XNOR gate
+					tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]);
+				else if(C_GATE_TYPE == 6) // INV gate
+					tmpres[j] = ~(intIA[j]);
+				else if(C_GATE_TYPE == 7) // BUF gate
+					tmpres[j] = intIA[j];
+			end
+		end
+		
+		intO <= tmpres;
+	end
+	
+	always@(IA or IB or IC or ID) 
+	begin
+		if(C_INPUTS == 4) 
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			intID = ID ^ to_bits(C_INPUT_D_INV_MASK);
+		end
+		else if(C_INPUTS == 3)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				intID = {C_WIDTH{1'b1}};
+			else
+				intID = 'b0;
+		end
+		else if(C_INPUTS == 2)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				begin
+				intIC = {C_WIDTH{1'b1}};
+				intID = {C_WIDTH{1'b1}};
+			end
+			else
+			begin
+				intIC = 'b0;
+				intID = 'b0;
+			end
+		end
+		else // inv or buf gates
+		begin
+			intID = {C_WIDTH{1'b0}};
+			intIC = {C_WIDTH{1'b0}};
+			intIB = {C_WIDTH{1'b0}};
+			intIA = IA;
+		end
+						
+		for(j = 0; j < C_WIDTH; j = j + 1)
+		begin
+			if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx)
+			begin // Unknown's on at least one input
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE > 3) // other gate
+					tmpres[j] = 1'bx;
+			end
+			else
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+					tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j];
+				else if(C_GATE_TYPE == 1) // NAND gate
+					tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]);
+				else if(C_GATE_TYPE == 2) // OR gate
+					tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j];
+				else if(C_GATE_TYPE == 3) // NOR gate
+					tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]);
+				else if(C_GATE_TYPE == 4) // XOR gate
+					tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j];
+				else if(C_GATE_TYPE == 5) // XNOR gate
+					tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]);
+				else if(C_GATE_TYPE == 6) // INV gate
+					tmpres[j] = ~(intIA[j]);
+				else if(C_GATE_TYPE == 7) // BUF gate
+					tmpres[j] = intIA[j];
+			end
+		end
+		
+		intO <= #1 tmpres;
+	end
+
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor
+`undef c_inv
+`undef c_buf
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V6_0.v

@@ -0,0 +1,374 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_GATE_BUS_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_GATE_BUS_V6_0.v
+-- Author - Xilinx
+-- Creation - 26 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BUS_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+`define c_inv 6
+`define c_buf 7
+
+module C_GATE_BUS_V6_0 (IA, IB, IC, ID, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUTS 			= 2; 	
+	parameter C_INPUT_A_INV_MASK = "";
+	parameter C_INPUT_B_INV_MASK = "";
+	parameter C_INPUT_C_INV_MASK = "";
+	parameter C_INPUT_D_INV_MASK = "";
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_WIDTH 			= 16; 			
+	
+
+	input [C_WIDTH-1 : 0] IA;
+	input [C_WIDTH-1 : 0] IB;
+	input [C_WIDTH-1 : 0] IC;
+	input [C_WIDTH-1 : 0] ID;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	reg [C_WIDTH-1 : 0] intIA;
+	reg [C_WIDTH-1 : 0] intIB;
+	reg [C_WIDTH-1 : 0] intIC;
+	reg [C_WIDTH-1 : 0] intID;
+	reg [C_WIDTH-1 : 0] intO;
+	wire [C_WIDTH-1 : 0] intQ;
+		 
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}});
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}});
+		
+	
+	integer j;
+	
+	reg [C_WIDTH-1 : 0] tmpres;
+	
+	// Output register
+	C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+	
+		#1;
+		
+		if(C_INPUTS == 4) 
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			intID = ID ^ to_bits(C_INPUT_D_INV_MASK);
+		end
+		else if(C_INPUTS == 3)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				intID = {C_WIDTH{1'b1}};
+			else
+					intID = 'b0;
+		end
+		else if(C_INPUTS == 2)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+			begin
+				intIC = {C_WIDTH{1'b1}};
+				intID = {C_WIDTH{1'b1}};
+			end
+			else
+			begin
+				intIC = 'b0;
+				intID = 'b0;
+			end
+		end	
+		else // inv or buf gates
+		begin
+			intID = {C_WIDTH{1'b0}};
+			intIC = {C_WIDTH{1'b0}};
+			intIB = {C_WIDTH{1'b0}};
+			intIA = IA;
+		end
+					
+		for(j = 0; j < C_WIDTH; j = j + 1)
+		begin
+			if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx)
+			begin // Unknown's on at least one input
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE > 3) // other gate
+					tmpres[j] = 1'bx;
+			end
+			else
+			begin // No unknowns in inputs
+				if(C_GATE_TYPE == 0) // AND gate
+					tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j];
+				else if(C_GATE_TYPE == 1) // NAND gate
+					tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]);
+				else if(C_GATE_TYPE == 2) // OR gate
+					tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j];
+				else if(C_GATE_TYPE == 3) // NOR gate
+					tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]);
+				else if(C_GATE_TYPE == 4) // XOR gate
+					tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j];
+				else if(C_GATE_TYPE == 5) // XNOR gate
+					tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]);
+				else if(C_GATE_TYPE == 6) // INV gate
+					tmpres[j] = ~(intIA[j]);
+				else if(C_GATE_TYPE == 7) // BUF gate
+					tmpres[j] = intIA[j];
+			end
+		end
+		
+		intO <= tmpres;
+	end
+	
+	always@(IA or IB or IC or ID) 
+	begin
+		if(C_INPUTS == 4) 
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			intID = ID ^ to_bits(C_INPUT_D_INV_MASK);
+		end
+		else if(C_INPUTS == 3)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				intID = {C_WIDTH{1'b1}};
+			else
+				intID = 'b0;
+		end
+		else if(C_INPUTS == 2)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				begin
+				intIC = {C_WIDTH{1'b1}};
+				intID = {C_WIDTH{1'b1}};
+			end
+			else
+			begin
+				intIC = 'b0;
+				intID = 'b0;
+			end
+		end
+		else // inv or buf gates
+		begin
+			intID = {C_WIDTH{1'b0}};
+			intIC = {C_WIDTH{1'b0}};
+			intIB = {C_WIDTH{1'b0}};
+			intIA = IA;
+		end
+						
+		for(j = 0; j < C_WIDTH; j = j + 1)
+		begin
+			if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx)
+			begin // Unknown's on at least one input
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE > 3) // other gate
+					tmpres[j] = 1'bx;
+			end
+			else
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+					tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j];
+				else if(C_GATE_TYPE == 1) // NAND gate
+					tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]);
+				else if(C_GATE_TYPE == 2) // OR gate
+					tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j];
+				else if(C_GATE_TYPE == 3) // NOR gate
+					tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]);
+				else if(C_GATE_TYPE == 4) // XOR gate
+					tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j];
+				else if(C_GATE_TYPE == 5) // XNOR gate
+					tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]);
+				else if(C_GATE_TYPE == 6) // INV gate
+					tmpres[j] = ~(intIA[j]);
+				else if(C_GATE_TYPE == 7) // BUF gate
+					tmpres[j] = intIA[j];
+			end
+		end
+		
+		intO <= #1 tmpres;
+	end
+
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor
+`undef c_inv
+`undef c_buf
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V7_0.v

@@ -0,0 +1,374 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_GATE_BUS_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_GATE_BUS_V7_0.v
+-- Author - Xilinx
+-- Creation - 26 Jan 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BUS_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_and 0
+`define c_nand 1
+`define c_or 2
+`define c_nor 3
+`define c_xor 4
+`define c_xnor 5
+`define c_inv 6
+`define c_buf 7
+
+module C_GATE_BUS_V7_0 (IA, IB, IC, ID, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_GATE_TYPE 		= `c_and;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_O 			= 0;
+	parameter C_HAS_Q 			= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUTS 			= 2; 	
+	parameter C_INPUT_A_INV_MASK = "";
+	parameter C_INPUT_B_INV_MASK = "";
+	parameter C_INPUT_C_INV_MASK = "";
+	parameter C_INPUT_D_INV_MASK = "";
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;
+	parameter C_SYNC_PRIORITY 	= `c_clear;		
+	parameter C_WIDTH 			= 16; 			
+	
+
+	input [C_WIDTH-1 : 0] IA;
+	input [C_WIDTH-1 : 0] IB;
+	input [C_WIDTH-1 : 0] IC;
+	input [C_WIDTH-1 : 0] ID;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	reg [C_WIDTH-1 : 0] intIA;
+	reg [C_WIDTH-1 : 0] intIB;
+	reg [C_WIDTH-1 : 0] intIC;
+	reg [C_WIDTH-1 : 0] intID;
+	reg [C_WIDTH-1 : 0] intO;
+	wire [C_WIDTH-1 : 0] intQ;
+		 
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}});
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}});
+		
+	
+	integer j;
+	
+	reg [C_WIDTH-1 : 0] tmpres;
+	
+	// Output register
+	C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(intQ)); 
+
+	initial 
+	begin
+	
+		#1;
+		
+		if(C_INPUTS == 4) 
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			intID = ID ^ to_bits(C_INPUT_D_INV_MASK);
+		end
+		else if(C_INPUTS == 3)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				intID = {C_WIDTH{1'b1}};
+			else
+					intID = 'b0;
+		end
+		else if(C_INPUTS == 2)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+			begin
+				intIC = {C_WIDTH{1'b1}};
+				intID = {C_WIDTH{1'b1}};
+			end
+			else
+			begin
+				intIC = 'b0;
+				intID = 'b0;
+			end
+		end	
+		else // inv or buf gates
+		begin
+			intID = {C_WIDTH{1'b0}};
+			intIC = {C_WIDTH{1'b0}};
+			intIB = {C_WIDTH{1'b0}};
+			intIA = IA;
+		end
+					
+		for(j = 0; j < C_WIDTH; j = j + 1)
+		begin
+			if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx)
+			begin // Unknown's on at least one input
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE > 3) // other gate
+					tmpres[j] = 1'bx;
+			end
+			else
+			begin // No unknowns in inputs
+				if(C_GATE_TYPE == 0) // AND gate
+					tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j];
+				else if(C_GATE_TYPE == 1) // NAND gate
+					tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]);
+				else if(C_GATE_TYPE == 2) // OR gate
+					tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j];
+				else if(C_GATE_TYPE == 3) // NOR gate
+					tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]);
+				else if(C_GATE_TYPE == 4) // XOR gate
+					tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j];
+				else if(C_GATE_TYPE == 5) // XNOR gate
+					tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]);
+				else if(C_GATE_TYPE == 6) // INV gate
+					tmpres[j] = ~(intIA[j]);
+				else if(C_GATE_TYPE == 7) // BUF gate
+					tmpres[j] = intIA[j];
+			end
+		end
+		
+		intO <= tmpres;
+	end
+	
+	always@(IA or IB or IC or ID) 
+	begin
+		if(C_INPUTS == 4) 
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			intID = ID ^ to_bits(C_INPUT_D_INV_MASK);
+		end
+		else if(C_INPUTS == 3)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			intIC = IC ^ to_bits(C_INPUT_C_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				intID = {C_WIDTH{1'b1}};
+			else
+				intID = 'b0;
+		end
+		else if(C_INPUTS == 2)
+		begin
+			intIA = IA ^ to_bits(C_INPUT_A_INV_MASK);
+			intIB = IB ^ to_bits(C_INPUT_B_INV_MASK);
+			if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate!
+				begin
+				intIC = {C_WIDTH{1'b1}};
+				intID = {C_WIDTH{1'b1}};
+			end
+			else
+			begin
+				intIC = 'b0;
+				intID = 'b0;
+			end
+		end
+		else // inv or buf gates
+		begin
+			intID = {C_WIDTH{1'b0}};
+			intIC = {C_WIDTH{1'b0}};
+			intIB = {C_WIDTH{1'b0}};
+			intIA = IA;
+		end
+						
+		for(j = 0; j < C_WIDTH; j = j + 1)
+		begin
+			if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx)
+			begin // Unknown's on at least one input
+				if(C_GATE_TYPE == 0) // AND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 1) // NAND gate
+				begin
+					if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 2) // OR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b1;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE == 3) // NOR gate
+				begin
+					if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1)
+						tmpres[j] = 1'b0;
+					else
+						tmpres[j] = 1'bx;
+				end
+				else if(C_GATE_TYPE > 3) // other gate
+					tmpres[j] = 1'bx;
+			end
+			else
+			begin
+				if(C_GATE_TYPE == 0) // AND gate
+					tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j];
+				else if(C_GATE_TYPE == 1) // NAND gate
+					tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]);
+				else if(C_GATE_TYPE == 2) // OR gate
+					tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j];
+				else if(C_GATE_TYPE == 3) // NOR gate
+					tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]);
+				else if(C_GATE_TYPE == 4) // XOR gate
+					tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j];
+				else if(C_GATE_TYPE == 5) // XNOR gate
+					tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]);
+				else if(C_GATE_TYPE == 6) // INV gate
+					tmpres[j] = ~(intIA[j]);
+				else if(C_GATE_TYPE == 7) // BUF gate
+					tmpres[j] = intIA[j];
+			end
+		end
+		
+		intO <= #1 tmpres;
+	end
+
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	begin
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is this character a '0'? (ASCII = 48 = 00110000)
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0)
+					to_bits[i-1] = 0;
+			  // Or is it a '1'? 
+			else if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 1 && 
+				instring[(i*8)-3] == 1 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 1)
+
+					to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+			else 
+			begin
+				$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+				$finish;
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_and
+`undef c_nand
+`undef c_or
+`undef c_nor
+`undef c_xor
+`undef c_xnor
+`undef c_inv
+`undef c_buf
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V4_0.v

@@ -0,0 +1,191 @@
+/* $Id: C_MUX_BIT_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_MUX_BIT_V4_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BIT_V4_0 module
+*/
+
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+module C_MUX_BIT_V4_0 (M, S, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 	        = 0;
+	parameter C_HAS_O 	        = 0;
+	parameter C_HAS_Q 		= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUTS 		= 2;
+        parameter C_LATENCY             = 0;
+	parameter C_PIPE_STAGES         = 0;
+	parameter C_SEL_WIDTH 		= 1; 			
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;		
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+
+        // Parameters used to drive additional registers for pipelining.
+
+        parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0);
+        parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0);
+	parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0);
+        parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0);
+        parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0);
+
+        parameter PIPE2_HAS_ACLR = (C_LATENCY == 2 ? C_HAS_ACLR : 1'b0);
+        parameter PIPE2_HAS_AINIT = (C_LATENCY == 2 ? C_HAS_AINIT : 1'b0);
+	parameter PIPE2_HAS_ASET = (C_LATENCY == 2 ? C_HAS_ASET : 1'b0);
+        parameter PIPE2_HAS_SSET = (C_LATENCY == 2 ? C_HAS_SSET : 1'b0);
+        parameter PIPE2_HAS_SINIT = (C_LATENCY == 2 ? C_HAS_SINIT : 1'b0);
+
+
+	input [C_INPUTS-1 : 0] M;
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output O;
+	output Q;
+	 
+	// Internal values to drive signals when input is missing
+
+	reg intO;
+	reg intQ;
+//	reg lastCLK;
+
+        wire STAGE1;
+        wire STAGE2;
+        wire STAGE3;	
+	 
+	wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);
+	wire O = (C_HAS_O == 1 ? intO : 1'bx);
+	
+	// Sort out default values for missing ports		
+	
+	integer j, k;
+	integer m, unknown;
+	
+	// Register on output by default
+	C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE1)); 
+
+	C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE2_HAS_ACLR, PIPE2_HAS_AINIT, PIPE2_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE2_HAS_SINIT, PIPE2_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE2));       
+
+        C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg3 (.D(STAGE2), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE3));
+
+	initial 
+	begin
+
+		#1;
+
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1)
+				k = k + m;
+			else if(S[j] === 1'bz || S[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+		
+		if(unknown == 1)
+			intO <= 1'bx;
+		else
+			intO <= M[k-1];
+			
+	end
+	
+//	always @(CLK)
+//  		lastCLK <= CLK;
+
+	always@(M or S)
+	begin
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1)
+				k = k + m;
+			else if(S[j] === 1'bz || S[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+		
+		if(unknown == 1)
+			intO <= #1 1'bx;
+		else
+			intO <= #1 M[k-1];
+	end
+
+
+        // Register Output Settings
+        always
+        begin
+           //------------------------------
+           //-- REGISTER CLOCKED OUTPUTS --
+           //------------------------------
+              if (C_LATENCY === 1)
+                 intQ = STAGE1;
+              
+              else if (C_LATENCY === 2)
+                 intQ = STAGE2;
+              
+              else
+                 intQ = STAGE3;
+
+              @(STAGE1 or STAGE2 or STAGE3);
+        end
+
+		
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V5_0.v

@@ -0,0 +1,190 @@
+/* $Id: C_MUX_BIT_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $
+--
+-- Filename - C_MUX_BIT_V5_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BIT_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+module C_MUX_BIT_V5_0 (M, S, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 	        = 0;
+	parameter C_HAS_O 	        = 0;
+	parameter C_HAS_Q 		= 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_INPUTS 		= 2;
+        parameter C_LATENCY             = 0;
+	parameter C_PIPE_STAGES         = 0;
+	parameter C_SEL_WIDTH 		= 1; 			
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;		
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+
+        // Parameters used to drive additional registers for pipelining.
+
+        parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0);
+        parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0);
+	parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0);
+        parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0);
+        parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0);
+
+        parameter PIPE2_HAS_ACLR = (C_LATENCY == 2 ? C_HAS_ACLR : 1'b0);
+        parameter PIPE2_HAS_AINIT = (C_LATENCY == 2 ? C_HAS_AINIT : 1'b0);
+	parameter PIPE2_HAS_ASET = (C_LATENCY == 2 ? C_HAS_ASET : 1'b0);
+        parameter PIPE2_HAS_SSET = (C_LATENCY == 2 ? C_HAS_SSET : 1'b0);
+        parameter PIPE2_HAS_SINIT = (C_LATENCY == 2 ? C_HAS_SINIT : 1'b0);
+
+
+	input [C_INPUTS-1 : 0] M;
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output O;
+	output Q;
+	 
+	// Internal values to drive signals when input is missing
+
+	reg intO;
+	reg intQ;
+//	reg lastCLK;
+
+        wire STAGE1;
+        wire STAGE2;
+        wire STAGE3;	
+	 
+	wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);
+	wire O = (C_HAS_O == 1 ? intO : 1'bx);
+	
+	// Sort out default values for missing ports		
+	
+	integer j, k;
+	integer m, unknown;
+	
+	// Register on output by default
+	C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE1)); 
+
+	C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE2_HAS_ACLR, PIPE2_HAS_AINIT, PIPE2_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE2_HAS_SINIT, PIPE2_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE2));       
+
+        C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg3 (.D(STAGE2), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE3));
+
+	initial 
+	begin
+
+		#1;
+
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1)
+				k = k + m;
+			else if(S[j] === 1'bz || S[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+		
+		if(unknown == 1)
+			intO <= 1'bx;
+		else
+			intO <= M[k-1];
+			
+	end
+	
+//	always @(CLK)
+//  		lastCLK <= CLK;
+
+	always@(M or S)
+	begin
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1)
+				k = k + m;
+			else if(S[j] === 1'bz || S[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+		
+		if(unknown == 1)
+			intO <= #1 1'bx;
+		else
+			intO <= #1 M[k-1];
+	end
+
+
+        // Register Output Settings
+        always
+        begin
+           //------------------------------
+           //-- REGISTER CLOCKED OUTPUTS --
+           //------------------------------
+              if (C_LATENCY === 1)
+                 intQ = STAGE1;
+              
+              else if (C_LATENCY === 2)
+                 intQ = STAGE2;
+              
+              else
+                 intQ = STAGE3;
+
+              @(STAGE1 or STAGE2 or STAGE3);
+        end
+
+		
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V6_0.v

@@ -0,0 +1,222 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_MUX_BIT_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_MUX_BIT_V6_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BIT_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+module C_MUX_BIT_V6_0 (M, S, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+    parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 	        = 0;
+	parameter C_HAS_O 	        = 0;
+	parameter C_HAS_Q           = 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+    parameter C_HEIGHT          = 0;   
+	parameter C_INPUTS          = 2;
+    parameter C_LATENCY         = 0;
+	parameter C_PIPE_STAGES     = 0;
+	parameter C_SEL_WIDTH 		= 1; 			
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;		
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+
+        // Parameters used to drive additional registers for pipelining.
+
+        parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0);
+        parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0);
+	    parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0);
+        parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0);
+        parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0);
+
+        parameter PIPE2_HAS_ACLR = (C_LATENCY == 2 ? C_HAS_ACLR : 1'b0);
+        parameter PIPE2_HAS_AINIT = (C_LATENCY == 2 ? C_HAS_AINIT : 1'b0);
+	    parameter PIPE2_HAS_ASET = (C_LATENCY == 2 ? C_HAS_ASET : 1'b0);
+        parameter PIPE2_HAS_SSET = (C_LATENCY == 2 ? C_HAS_SSET : 1'b0);
+        parameter PIPE2_HAS_SINIT = (C_LATENCY == 2 ? C_HAS_SINIT : 1'b0);
+
+
+	input [C_INPUTS-1 : 0] M;
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output O;
+	output Q;
+	 
+	// Internal values to drive signals when input is missing
+
+	reg intO;
+	reg intQ;
+//	reg lastCLK;
+
+        wire STAGE1;
+        wire STAGE2;
+        wire STAGE3;	
+	 
+	wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);
+	wire O = (C_HAS_O == 1 ? intO : 1'bx);
+	
+	// Sort out default values for missing ports		
+	
+	integer j, k;
+	integer m, unknown;
+	
+	// Register on output by default 
+	
+	C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE1)); 			   
+			  
+
+	C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE2_HAS_ACLR, PIPE2_HAS_AINIT, PIPE2_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE2_HAS_SINIT, PIPE2_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE2));       		   
+
+
+	/* These two register could be used if full options were desired for internal
+	pipelining registers...
+
+		C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE1));
+
+        C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE2));		 */
+
+
+
+        C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg3 (.D(STAGE2), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE3));
+
+	initial 
+	begin
+
+		#1;
+
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1)
+				k = k + m;
+			else if(S[j] === 1'bz || S[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+		
+		if(unknown == 1)
+			intO <= 1'bx;
+		else
+			intO <= M[k-1];
+			
+	end
+	
+//	always @(CLK)
+//  		lastCLK <= CLK;
+
+	always@(M or S)
+	begin
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1)
+				k = k + m;
+			else if(S[j] === 1'bz || S[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+		
+		if(unknown == 1)
+			intO <= #1 1'bx;
+		else
+			intO <= #1 M[k-1];
+	end
+
+
+        // Register Output Settings
+        always
+        begin
+           //------------------------------
+           //-- REGISTER CLOCKED OUTPUTS --
+           //------------------------------
+              if (C_LATENCY === 1)
+                 intQ = STAGE1;
+              
+              else if (C_LATENCY === 2)
+                 intQ = STAGE2;
+              
+              else
+                 intQ = STAGE3;
+
+              @(STAGE1 or STAGE2 or STAGE3);
+        end
+
+		
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V7_0.v

@@ -0,0 +1,251 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Id: C_MUX_BIT_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_MUX_BIT_V7_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BIT_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+module C_MUX_BIT_V7_0 (M, S, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+    parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 	        = 0;
+	parameter C_HAS_O 	        = 0;
+	parameter C_HAS_Q           = 1;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+    parameter C_HEIGHT          = 0;   
+	parameter C_INPUTS          = 2;
+    parameter C_LATENCY         = 0;
+	parameter C_PIPE_STAGES     = 0;
+	parameter C_SEL_WIDTH 		= 1; 			
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;		
+	parameter C_SYNC_PRIORITY 	= `c_clear;
+
+        // Parameters used to drive additional registers for pipelining.
+
+        parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0);
+        parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0);
+	    parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0);
+        parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0);
+        parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0);
+
+        parameter PIPE2_HAS_ACLR = (C_LATENCY == 2 ? C_HAS_ACLR : 1'b0);
+        parameter PIPE2_HAS_AINIT = (C_LATENCY == 2 ? C_HAS_AINIT : 1'b0);
+	    parameter PIPE2_HAS_ASET = (C_LATENCY == 2 ? C_HAS_ASET : 1'b0);
+        parameter PIPE2_HAS_SSET = (C_LATENCY == 2 ? C_HAS_SSET : 1'b0);
+        parameter PIPE2_HAS_SINIT = (C_LATENCY == 2 ? C_HAS_SINIT : 1'b0);
+
+
+	input [C_INPUTS-1 : 0] M;
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output O;
+	output Q;
+	 
+	// Internal values to drive signals when input is missing
+
+	reg intO;
+	reg intQ;
+//	reg lastCLK;
+
+        wire STAGE1;
+        wire STAGE2;
+        wire STAGE3;	
+	 
+	wire Q = (C_HAS_Q == 1 ? intQ : 1'bx);
+	wire O = (C_HAS_O == 1 ? intO : 1'bx);
+	
+	// Sort out default values for missing ports		
+	
+	integer j, k;
+	integer m, unknown;
+	
+	// Register on output by default 
+	
+	C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE1)); 			   
+			  
+
+	C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE2_HAS_ACLR, PIPE2_HAS_AINIT, PIPE2_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE2_HAS_SINIT, PIPE2_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE2));       		   
+
+
+	/* These two register could be used if full options were desired for internal
+	pipelining registers...
+
+		C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE1));
+
+        C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE2));		 */
+
+
+
+        C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1)
+		reg3 (.D(STAGE2), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE3));
+
+	initial 
+	begin
+
+		#1;
+
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1)
+				k = k + m;
+			else if(S[j] === 1'bz || S[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+		
+		if(unknown == 1)
+			intO <= 1'bx;
+		else
+			intO <= M[k-1];
+			
+	end
+	
+//	always @(CLK)
+//  		lastCLK <= CLK;
+
+	always@(M or S)
+	begin
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(S[j] === 1)
+				k = k + m;
+			else if(S[j] === 1'bz || S[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+		
+		if(unknown == 1)
+			intO <= #1 1'bx;
+		else
+			intO <= #1 M[k-1];
+	end
+
+
+        // Register Output Settings
+        always
+        begin
+           //------------------------------
+           //-- REGISTER CLOCKED OUTPUTS --
+           //------------------------------
+              if (C_LATENCY === 1)
+                 intQ = STAGE1;
+              
+              else if (C_LATENCY === 2)
+                 intQ = STAGE2;
+              
+              else
+                 intQ = STAGE3;
+
+              @(STAGE1 or STAGE2 or STAGE3);
+        end
+
+		
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V4_0.v

@@ -0,0 +1,399 @@
+/* $Id: C_MUX_BUS_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_MUX_BUS_V4_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BUS_V4_0 module
+*/
+
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_lut_based 0
+`define c_buft_based 1
+
+
+
+`define allmyXs {C_WIDTH{1'bx}}
+`define allmyZs {C_WIDTH{1'bz}}
+
+module C_MUX_BUS_V4_0 (MA, MB, MC, MD, ME, MF, MG, MH, 
+                       MAA, MAB, MAC, MAD, MAE, MAF, MAG, MAH,
+                       MBA, MBB, MBC, MBD, MBE, MBF, MBG, MBH, 
+                       MCA, MCB, MCC, MCD, MCE, MCF, MCG, MCH, 
+                       S, CLK, CE, EN, ACLR, ASET, AINIT, 
+                       SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 		= 0;
+	parameter C_HAS_EN 		= 0;
+	parameter C_HAS_O 		= 0;
+	parameter C_HAS_Q 		= 1;
+	parameter C_HAS_SCLR 		= 1;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 1;
+	parameter C_INPUTS 		= 2;
+        parameter C_LATENCY             = 1; 				
+	parameter C_MUX_TYPE 		= `c_lut_based;
+	parameter C_SEL_WIDTH 		= 1; 				
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 2;
+
+    // Parameters, used to drive additional register, for pipelining.
+    parameter PIPE_HAS_ACLR  = (C_LATENCY == 1 ? C_HAS_ACLR  : 1'b0);
+    parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0);
+    parameter PIPE_HAS_ASET  = (C_LATENCY == 1 ? C_HAS_ASET  : 1'b0);
+    parameter PIPE_HAS_SSET  = (C_LATENCY == 1 ? C_HAS_SSET  : 1'b0);
+    parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0);
+
+
+	input [C_WIDTH-1 : 0] MA;
+	input [C_WIDTH-1 : 0] MB;
+	input [C_WIDTH-1 : 0] MC;
+	input [C_WIDTH-1 : 0] MD;
+	input [C_WIDTH-1 : 0] ME;
+	input [C_WIDTH-1 : 0] MF;
+	input [C_WIDTH-1 : 0] MG;
+	input [C_WIDTH-1 : 0] MH;
+        input [C_WIDTH-1 : 0] MAA;
+	input [C_WIDTH-1 : 0] MAB;
+	input [C_WIDTH-1 : 0] MAC;
+	input [C_WIDTH-1 : 0] MAD;
+	input [C_WIDTH-1 : 0] MAE;
+	input [C_WIDTH-1 : 0] MAF;
+	input [C_WIDTH-1 : 0] MAG;
+	input [C_WIDTH-1 : 0] MAH;
+        input [C_WIDTH-1 : 0] MBA;
+	input [C_WIDTH-1 : 0] MBB;
+	input [C_WIDTH-1 : 0] MBC;
+	input [C_WIDTH-1 : 0] MBD;
+	input [C_WIDTH-1 : 0] MBE;
+	input [C_WIDTH-1 : 0] MBF;
+	input [C_WIDTH-1 : 0] MBG;
+	input [C_WIDTH-1 : 0] MBH;
+        input [C_WIDTH-1 : 0] MCA;
+	input [C_WIDTH-1 : 0] MCB;
+	input [C_WIDTH-1 : 0] MCC;
+	input [C_WIDTH-1 : 0] MCD;
+	input [C_WIDTH-1 : 0] MCE;
+	input [C_WIDTH-1 : 0] MCF;
+	input [C_WIDTH-1 : 0] MCG;
+	input [C_WIDTH-1 : 0] MCH;
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input EN;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_WIDTH-1 : 0] intMA = MA;
+	wire [C_WIDTH-1 : 0] intMB = MB;
+	wire [C_WIDTH-1 : 0] intMC = (C_INPUTS > 2 ? MC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMD = (C_INPUTS > 3 ? MD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intME = (C_INPUTS > 4 ? ME : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMF = (C_INPUTS > 5 ? MF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMG = (C_INPUTS > 6 ? MG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMH = (C_INPUTS > 7 ? MH : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAA = (C_INPUTS > 8 ? MAA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAB = (C_INPUTS > 9 ? MAB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAC = (C_INPUTS > 10 ? MAC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAD = (C_INPUTS > 11 ? MAD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAE = (C_INPUTS > 12 ? MAE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAF = (C_INPUTS > 13 ? MAF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAG = (C_INPUTS > 14 ? MAG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAH = (C_INPUTS > 15 ? MAH : `allmyXs);
+        wire [C_WIDTH-1 : 0] intMBA = (C_INPUTS > 16 ? MBA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBB = (C_INPUTS > 17 ? MBB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBC = (C_INPUTS > 18 ? MBC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBD = (C_INPUTS > 19 ? MBD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBE = (C_INPUTS > 20 ? MBE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBF = (C_INPUTS > 21 ? MBF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBG = (C_INPUTS > 22 ? MBG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBH = (C_INPUTS > 23 ? MBH : `allmyXs);
+        wire [C_WIDTH-1 : 0] intMCA = (C_INPUTS > 24 ? MCA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCB = (C_INPUTS > 25 ? MCB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCC = (C_INPUTS > 26 ? MCC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCD = (C_INPUTS > 27 ? MCD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCE = (C_INPUTS > 28 ? MCE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCF = (C_INPUTS > 29 ? MCF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCG = (C_INPUTS > 30 ? MCG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCH = (C_INPUTS > 31 ? MCH : `allmyXs);
+
+	reg  [C_WIDTH-1 : 0] intO;
+	reg [C_WIDTH-1 : 0] intQ;
+
+        wire [C_WIDTH-1 : 0] STAGE1;
+	wire [C_WIDTH-1 : 0] STAGE2;
+	wire [C_SEL_WIDTH-1 : 0] intS = S;	 
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allmyXs);
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allmyXs);
+	wire intEN;
+	
+
+	assign intEN = defval(EN, C_HAS_EN, 1);
+
+
+	integer j, k, j1, k1;
+	integer m, unknown, m1, unknown1;
+	
+	// Register on output by default
+
+        C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+	      REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), 
+			  .Q(STAGE1)); 
+        
+        
+        C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		  REG2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE2)); 
+
+
+	initial 
+	begin
+
+		#1;
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(intS[j] === 1)
+				k = k + m;
+			else if(intS[j] === 1'bz || intS[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+
+		if(intEN === 1'b0)
+			intO <= #1 `allmyZs;
+		else if(intEN === 1'bx)
+			intO <= #1 `allmyXs;
+		else if(unknown == 1)
+			intO <= #1 `allmyXs;
+		else if (k == 1) 
+			intO <= #1 intMA;
+		else if (k == 2) 
+			intO <= #1 intMB;
+		else if (k == 3) 
+			intO <= #1 intMC;
+		else if (k == 4) 
+			intO <= #1 intMD;
+		else if (k == 5) 
+			intO <= #1 intME;
+		else if (k == 6) 
+			intO <= #1 intMF;
+		else if (k == 7) 
+			intO <= #1 intMG;
+		else if (k == 8) 
+			intO <= #1 intMH;
+                 else if (k == 9) 
+			intO <= #1 intMAA;
+		else if (k == 10) 
+			intO <= #1 intMAB;
+		else if (k == 11) 
+			intO <= #1 intMAC;
+		else if (k == 12) 
+			intO <= #1 intMAD;
+		else if (k == 13) 
+			intO <= #1 intMAE;
+		else if (k == 14) 
+			intO <= #1 intMAF;
+		else if (k == 15) 
+			intO <= #1 intMAG;
+		else if (k == 16) 
+			intO <= #1 intMAH;
+		else if (k == 17) 
+			intO <= #1 intMBA;
+		else if (k == 18) 
+			intO <= #1 intMBB;
+		else if (k == 19) 
+			intO <= #1 intMBC;
+		else if (k == 20) 
+			intO <= #1 intMBD;
+		else if (k == 21) 
+			intO <= #1 intMBE;
+		else if (k == 22) 
+			intO <= #1 intMBF;
+		else if (k == 23) 
+			intO <= #1 intMBG;
+		else if (k == 24) 
+			intO <= #1 intMBH;
+		else if (k == 25) 
+			intO <= #1 intMCA;
+		else if (k == 26) 
+			intO <= #1 intMCB;
+		else if (k == 27) 
+			intO <= #1 intMCC;
+		else if (k == 28) 
+			intO <= #1 intMCD;
+		else if (k == 29) 
+			intO <= #1 intMCE;
+		else if (k == 30) 
+			intO <= #1 intMCF;
+		else if (k == 31) 
+			intO <= #1 intMCG;
+		else if (k == 32) 
+			intO <= #1 intMCH;
+		else
+			intO <= #1 `allmyXs;
+
+	end
+	
+	always@(intMA or intMB or intMC or intMD or intME or intMF or intMG or intMH or 
+	        intMAA or intMAB or intMAC or intMAD or intMAE or intMAF or intMAG or intMAH or
+                intMBA or intMBB or intMBC or intMBD or intMBE or intMBF or intMBG or intMBH or
+                intMCA or intMCB or intMCC or intMCD or intMCE or intMCF or intMCG or intMCH or
+	        intEN or intS)
+	begin
+		
+		k1 = 1;
+		m1 = 1; 
+		unknown1 = 0;
+		for(j1 = 0; j1 < C_SEL_WIDTH; j1 = j1 + 1)
+		begin
+			if(intS[j1] === 1)
+				k1 = k1 + m1;
+			else if(intS[j1] === 1'bz || intS[j1] === 1'bx)
+				unknown1 = 1;
+			m1 = m1 * 2;
+		end
+
+		
+		if(intEN === 1'b0)
+			intO = #1 `allmyZs;
+		else if(intEN === 1'bx)
+			intO = #1 `allmyXs;
+		else if(unknown1 == 1)
+			intO <= #1 `allmyXs;
+		else if (k1 == 1) 
+			intO <= #1 intMA;
+		else if (k1 == 2) 
+			intO <= #1 intMB;
+		else if (k1 == 3) 
+			intO <= #1 intMC;
+		else if (k1 == 4) 
+			intO <= #1 intMD;
+		else if (k1 == 5) 
+			intO <= #1 intME;
+		else if (k1 == 6) 
+			intO <= #1 intMF;
+		else if (k1 == 7) 
+			intO <= #1 intMG;
+		else if (k1 == 8) 
+			intO <= #1 intMH;
+		else if (k1 == 9) 
+			intO <= #1 intMAA;
+		else if (k1 == 10) 
+			intO <= #1 intMAB;
+		else if (k1 == 11) 
+			intO <= #1 intMAC;
+		else if (k1 == 12) 
+			intO <= #1 intMAD;
+		else if (k1 == 13) 
+			intO <= #1 intMAE;
+		else if (k1 == 14) 
+			intO <= #1 intMAF;
+		else if (k1 == 15) 
+			intO <= #1 intMAG;
+		else if (k1 == 16) 
+			intO <= #1 intMAH;
+		else if (k1 == 17) 
+			intO <= #1 intMBA;
+		else if (k1 == 18) 
+			intO <= #1 intMBB;
+		else if (k1 == 19) 
+			intO <= #1 intMBC;
+		else if (k1 == 20) 
+			intO <= #1 intMBD;
+		else if (k1 == 21) 
+			intO <= #1 intMBE;
+		else if (k1 == 22) 
+			intO <= #1 intMBF;
+		else if (k1 == 23) 
+			intO <= #1 intMBG;
+		else if (k1 == 24) 
+			intO <= #1 intMBH;
+		else if (k1 == 25) 
+			intO <= #1 intMCA;
+		else if (k1 == 26) 
+			intO <= #1 intMCB;
+		else if (k1 == 27) 
+			intO <= #1 intMCC;
+		else if (k1 == 28) 
+			intO <= #1 intMCD;
+		else if (k1 == 29) 
+			intO <= #1 intMCE;
+		else if (k1 == 30) 
+			intO <= #1 intMCF;
+		else if (k1 == 31) 
+			intO <= #1 intMCG;
+		else if (k1 == 32) 
+			intO <= #1 intMCH;
+		else
+			intO <= #1 `allmyXs;  
+                           
+	end
+	
+// Register output settings       
+always   
+begin
+     //------------------------------
+     //-- REGISTER CLOCKED OUTPUTS --
+     //------------------------------
+        if (C_LATENCY === 1)
+             intQ = STAGE1;
+            else
+             intQ = STAGE2; 
+        @(STAGE1 or STAGE2);       
+end
+     
+		
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_lut_based
+`undef c_buft_based
+
+`undef allmyXs
+`undef allmyZs
+
+
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V5_0.v

@@ -0,0 +1,396 @@
+/* $Id: C_MUX_BUS_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $
+--
+-- Filename - C_MUX_BUS_V5_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BUS_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_lut_based 0
+`define c_buft_based 1
+
+
+
+`define allmyXs {C_WIDTH{1'bx}}
+`define allmyZs {C_WIDTH{1'bz}}
+
+module C_MUX_BUS_V5_0 (MA, MB, MC, MD, ME, MF, MG, MH, 
+                       MAA, MAB, MAC, MAD, MAE, MAF, MAG, MAH,
+                       MBA, MBB, MBC, MBD, MBE, MBF, MBG, MBH, 
+                       MCA, MCB, MCC, MCD, MCE, MCF, MCG, MCH, 
+                       S, CLK, CE, EN, ACLR, ASET, AINIT, 
+                       SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 		= 0;
+	parameter C_HAS_EN 		= 0;
+	parameter C_HAS_O 		= 0;
+	parameter C_HAS_Q 		= 1;
+	parameter C_HAS_SCLR 		= 1;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 1;
+	parameter C_INPUTS 		= 2;
+        parameter C_LATENCY             = 1; 				
+	parameter C_MUX_TYPE 		= `c_lut_based;
+	parameter C_SEL_WIDTH 		= 1; 				
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 2;
+
+    // Parameters, used to drive additional register, for pipelining.
+    parameter PIPE_HAS_ACLR  = (C_LATENCY == 1 ? C_HAS_ACLR  : 1'b0);
+    parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0);
+    parameter PIPE_HAS_ASET  = (C_LATENCY == 1 ? C_HAS_ASET  : 1'b0);
+    parameter PIPE_HAS_SSET  = (C_LATENCY == 1 ? C_HAS_SSET  : 1'b0);
+    parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0);
+
+
+	input [C_WIDTH-1 : 0] MA;
+	input [C_WIDTH-1 : 0] MB;
+	input [C_WIDTH-1 : 0] MC;
+	input [C_WIDTH-1 : 0] MD;
+	input [C_WIDTH-1 : 0] ME;
+	input [C_WIDTH-1 : 0] MF;
+	input [C_WIDTH-1 : 0] MG;
+	input [C_WIDTH-1 : 0] MH;
+        input [C_WIDTH-1 : 0] MAA;
+	input [C_WIDTH-1 : 0] MAB;
+	input [C_WIDTH-1 : 0] MAC;
+	input [C_WIDTH-1 : 0] MAD;
+	input [C_WIDTH-1 : 0] MAE;
+	input [C_WIDTH-1 : 0] MAF;
+	input [C_WIDTH-1 : 0] MAG;
+	input [C_WIDTH-1 : 0] MAH;
+        input [C_WIDTH-1 : 0] MBA;
+	input [C_WIDTH-1 : 0] MBB;
+	input [C_WIDTH-1 : 0] MBC;
+	input [C_WIDTH-1 : 0] MBD;
+	input [C_WIDTH-1 : 0] MBE;
+	input [C_WIDTH-1 : 0] MBF;
+	input [C_WIDTH-1 : 0] MBG;
+	input [C_WIDTH-1 : 0] MBH;
+        input [C_WIDTH-1 : 0] MCA;
+	input [C_WIDTH-1 : 0] MCB;
+	input [C_WIDTH-1 : 0] MCC;
+	input [C_WIDTH-1 : 0] MCD;
+	input [C_WIDTH-1 : 0] MCE;
+	input [C_WIDTH-1 : 0] MCF;
+	input [C_WIDTH-1 : 0] MCG;
+	input [C_WIDTH-1 : 0] MCH;
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input EN;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_WIDTH-1 : 0] intMA = MA;
+	wire [C_WIDTH-1 : 0] intMB = MB;
+	wire [C_WIDTH-1 : 0] intMC = (C_INPUTS > 2 ? MC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMD = (C_INPUTS > 3 ? MD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intME = (C_INPUTS > 4 ? ME : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMF = (C_INPUTS > 5 ? MF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMG = (C_INPUTS > 6 ? MG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMH = (C_INPUTS > 7 ? MH : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAA = (C_INPUTS > 8 ? MAA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAB = (C_INPUTS > 9 ? MAB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAC = (C_INPUTS > 10 ? MAC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAD = (C_INPUTS > 11 ? MAD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAE = (C_INPUTS > 12 ? MAE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAF = (C_INPUTS > 13 ? MAF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAG = (C_INPUTS > 14 ? MAG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAH = (C_INPUTS > 15 ? MAH : `allmyXs);
+        wire [C_WIDTH-1 : 0] intMBA = (C_INPUTS > 16 ? MBA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBB = (C_INPUTS > 17 ? MBB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBC = (C_INPUTS > 18 ? MBC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBD = (C_INPUTS > 19 ? MBD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBE = (C_INPUTS > 20 ? MBE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBF = (C_INPUTS > 21 ? MBF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBG = (C_INPUTS > 22 ? MBG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBH = (C_INPUTS > 23 ? MBH : `allmyXs);
+        wire [C_WIDTH-1 : 0] intMCA = (C_INPUTS > 24 ? MCA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCB = (C_INPUTS > 25 ? MCB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCC = (C_INPUTS > 26 ? MCC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCD = (C_INPUTS > 27 ? MCD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCE = (C_INPUTS > 28 ? MCE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCF = (C_INPUTS > 29 ? MCF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCG = (C_INPUTS > 30 ? MCG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCH = (C_INPUTS > 31 ? MCH : `allmyXs);
+
+	reg  [C_WIDTH-1 : 0] intO;
+	reg [C_WIDTH-1 : 0] intQ;
+
+        wire [C_WIDTH-1 : 0] STAGE1;
+	wire [C_WIDTH-1 : 0] STAGE2;
+	wire [C_SEL_WIDTH-1 : 0] intS = S;	 
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allmyXs);
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allmyXs);
+	wire intEN;
+	
+
+	assign intEN = defval(EN, C_HAS_EN, 1);
+
+
+	integer j, k, j1, k1;
+	integer m, unknown, m1, unknown1;
+	
+	// Register on output by default
+
+        C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+	      REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), 
+			  .Q(STAGE1)); 
+        
+        
+        C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		  REG2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE2)); 
+
+
+	initial 
+	begin
+
+		#1;
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(intS[j] === 1)
+				k = k + m;
+			else if(intS[j] === 1'bz || intS[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+
+		if(intEN === 1'b0)
+			intO <= #1 `allmyZs;
+		else if(intEN === 1'bx)
+			intO <= #1 `allmyXs;
+		else if(unknown == 1)
+			intO <= #1 `allmyXs;
+		else if (k == 1) 
+			intO <= #1 intMA;
+		else if (k == 2) 
+			intO <= #1 intMB;
+		else if (k == 3) 
+			intO <= #1 intMC;
+		else if (k == 4) 
+			intO <= #1 intMD;
+		else if (k == 5) 
+			intO <= #1 intME;
+		else if (k == 6) 
+			intO <= #1 intMF;
+		else if (k == 7) 
+			intO <= #1 intMG;
+		else if (k == 8) 
+			intO <= #1 intMH;
+                 else if (k == 9) 
+			intO <= #1 intMAA;
+		else if (k == 10) 
+			intO <= #1 intMAB;
+		else if (k == 11) 
+			intO <= #1 intMAC;
+		else if (k == 12) 
+			intO <= #1 intMAD;
+		else if (k == 13) 
+			intO <= #1 intMAE;
+		else if (k == 14) 
+			intO <= #1 intMAF;
+		else if (k == 15) 
+			intO <= #1 intMAG;
+		else if (k == 16) 
+			intO <= #1 intMAH;
+		else if (k == 17) 
+			intO <= #1 intMBA;
+		else if (k == 18) 
+			intO <= #1 intMBB;
+		else if (k == 19) 
+			intO <= #1 intMBC;
+		else if (k == 20) 
+			intO <= #1 intMBD;
+		else if (k == 21) 
+			intO <= #1 intMBE;
+		else if (k == 22) 
+			intO <= #1 intMBF;
+		else if (k == 23) 
+			intO <= #1 intMBG;
+		else if (k == 24) 
+			intO <= #1 intMBH;
+		else if (k == 25) 
+			intO <= #1 intMCA;
+		else if (k == 26) 
+			intO <= #1 intMCB;
+		else if (k == 27) 
+			intO <= #1 intMCC;
+		else if (k == 28) 
+			intO <= #1 intMCD;
+		else if (k == 29) 
+			intO <= #1 intMCE;
+		else if (k == 30) 
+			intO <= #1 intMCF;
+		else if (k == 31) 
+			intO <= #1 intMCG;
+		else if (k == 32) 
+			intO <= #1 intMCH;
+		else
+			intO <= #1 `allmyXs;
+
+	end
+	
+	always@(intMA or intMB or intMC or intMD or intME or intMF or intMG or intMH or 
+	        intMAA or intMAB or intMAC or intMAD or intMAE or intMAF or intMAG or intMAH or
+                intMBA or intMBB or intMBC or intMBD or intMBE or intMBF or intMBG or intMBH or
+                intMCA or intMCB or intMCC or intMCD or intMCE or intMCF or intMCG or intMCH or
+	        intEN or intS)
+	begin
+		
+		k1 = 1;
+		m1 = 1; 
+		unknown1 = 0;
+		for(j1 = 0; j1 < C_SEL_WIDTH; j1 = j1 + 1)
+		begin
+			if(intS[j1] === 1)
+				k1 = k1 + m1;
+			else if(intS[j1] === 1'bz || intS[j1] === 1'bx)
+				unknown1 = 1;
+			m1 = m1 * 2;
+		end
+
+		
+		if(intEN === 1'b0)
+			intO = #1 `allmyZs;
+		else if(intEN === 1'bx)
+			intO = #1 `allmyXs;
+		else if(unknown1 == 1)
+			intO <= #1 `allmyXs;
+		else if (k1 == 1) 
+			intO <= #1 intMA;
+		else if (k1 == 2) 
+			intO <= #1 intMB;
+		else if (k1 == 3) 
+			intO <= #1 intMC;
+		else if (k1 == 4) 
+			intO <= #1 intMD;
+		else if (k1 == 5) 
+			intO <= #1 intME;
+		else if (k1 == 6) 
+			intO <= #1 intMF;
+		else if (k1 == 7) 
+			intO <= #1 intMG;
+		else if (k1 == 8) 
+			intO <= #1 intMH;
+		else if (k1 == 9) 
+			intO <= #1 intMAA;
+		else if (k1 == 10) 
+			intO <= #1 intMAB;
+		else if (k1 == 11) 
+			intO <= #1 intMAC;
+		else if (k1 == 12) 
+			intO <= #1 intMAD;
+		else if (k1 == 13) 
+			intO <= #1 intMAE;
+		else if (k1 == 14) 
+			intO <= #1 intMAF;
+		else if (k1 == 15) 
+			intO <= #1 intMAG;
+		else if (k1 == 16) 
+			intO <= #1 intMAH;
+		else if (k1 == 17) 
+			intO <= #1 intMBA;
+		else if (k1 == 18) 
+			intO <= #1 intMBB;
+		else if (k1 == 19) 
+			intO <= #1 intMBC;
+		else if (k1 == 20) 
+			intO <= #1 intMBD;
+		else if (k1 == 21) 
+			intO <= #1 intMBE;
+		else if (k1 == 22) 
+			intO <= #1 intMBF;
+		else if (k1 == 23) 
+			intO <= #1 intMBG;
+		else if (k1 == 24) 
+			intO <= #1 intMBH;
+		else if (k1 == 25) 
+			intO <= #1 intMCA;
+		else if (k1 == 26) 
+			intO <= #1 intMCB;
+		else if (k1 == 27) 
+			intO <= #1 intMCC;
+		else if (k1 == 28) 
+			intO <= #1 intMCD;
+		else if (k1 == 29) 
+			intO <= #1 intMCE;
+		else if (k1 == 30) 
+			intO <= #1 intMCF;
+		else if (k1 == 31) 
+			intO <= #1 intMCG;
+		else if (k1 == 32) 
+			intO <= #1 intMCH;
+		else
+			intO <= #1 `allmyXs;  
+                           
+	end
+	
+// Register output settings       
+always   
+begin
+     //------------------------------
+     //-- REGISTER CLOCKED OUTPUTS --
+     //------------------------------
+        if (C_LATENCY === 1)
+             intQ = STAGE1;
+            else
+             intQ = STAGE2; 
+        @(STAGE1 or STAGE2);       
+end
+     
+		
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_lut_based
+`undef c_buft_based
+
+`undef allmyXs
+`undef allmyZs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V6_0.v

@@ -0,0 +1,415 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_MUX_BUS_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_MUX_BUS_V6_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BUS_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_lut_based 0
+`define c_buft_based 1
+
+
+
+`define allmyXs {C_WIDTH{1'bx}}
+`define allmyZs {C_WIDTH{1'bz}}
+
+module C_MUX_BUS_V6_0 (MA, MB, MC, MD, ME, MF, MG, MH, 
+                       MAA, MAB, MAC, MAD, MAE, MAF, MAG, MAH,
+                       MBA, MBB, MBC, MBD, MBE, MBF, MBG, MBH, 
+                       MCA, MCB, MCC, MCD, MCE, MCF, MCG, MCH, 
+                       S, CLK, CE, EN, ACLR, ASET, AINIT, 
+                       SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 		    = 0;
+	parameter C_HAS_EN          = 0;
+	parameter C_HAS_O           = 0;
+	parameter C_HAS_Q           = 1;
+	parameter C_HAS_SCLR 		= 1;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 1;
+	parameter C_HEIGHT          = 0;
+	parameter C_INPUTS 		    = 2;
+    parameter C_LATENCY         = 1; 				
+	parameter C_MUX_TYPE 		= `c_lut_based;
+	parameter C_SEL_WIDTH 		= 1; 				
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 2;
+
+    // Parameters, used to drive additional register, for pipelining.
+    parameter PIPE_HAS_ACLR  = (C_LATENCY == 1 ? C_HAS_ACLR  : 1'b0);
+    parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0);
+    parameter PIPE_HAS_ASET  = (C_LATENCY == 1 ? C_HAS_ASET  : 1'b0);
+    parameter PIPE_HAS_SSET  = (C_LATENCY == 1 ? C_HAS_SSET  : 1'b0);
+    parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0);
+
+
+	input [C_WIDTH-1 : 0] MA;
+	input [C_WIDTH-1 : 0] MB;
+	input [C_WIDTH-1 : 0] MC;
+	input [C_WIDTH-1 : 0] MD;
+	input [C_WIDTH-1 : 0] ME;
+	input [C_WIDTH-1 : 0] MF;
+	input [C_WIDTH-1 : 0] MG;
+	input [C_WIDTH-1 : 0] MH;
+    input [C_WIDTH-1 : 0] MAA;
+	input [C_WIDTH-1 : 0] MAB;
+	input [C_WIDTH-1 : 0] MAC;
+	input [C_WIDTH-1 : 0] MAD;
+	input [C_WIDTH-1 : 0] MAE;
+	input [C_WIDTH-1 : 0] MAF;
+	input [C_WIDTH-1 : 0] MAG;
+	input [C_WIDTH-1 : 0] MAH;
+    input [C_WIDTH-1 : 0] MBA;
+	input [C_WIDTH-1 : 0] MBB;
+	input [C_WIDTH-1 : 0] MBC;
+	input [C_WIDTH-1 : 0] MBD;
+	input [C_WIDTH-1 : 0] MBE;
+	input [C_WIDTH-1 : 0] MBF;
+	input [C_WIDTH-1 : 0] MBG;
+	input [C_WIDTH-1 : 0] MBH;
+    input [C_WIDTH-1 : 0] MCA;
+	input [C_WIDTH-1 : 0] MCB;
+	input [C_WIDTH-1 : 0] MCC;
+	input [C_WIDTH-1 : 0] MCD;
+	input [C_WIDTH-1 : 0] MCE;
+	input [C_WIDTH-1 : 0] MCF;
+	input [C_WIDTH-1 : 0] MCG;
+	input [C_WIDTH-1 : 0] MCH;
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input EN;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_WIDTH-1 : 0] intMA = MA;
+	wire [C_WIDTH-1 : 0] intMB = MB;
+	wire [C_WIDTH-1 : 0] intMC = (C_INPUTS > 2 ? MC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMD = (C_INPUTS > 3 ? MD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intME = (C_INPUTS > 4 ? ME : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMF = (C_INPUTS > 5 ? MF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMG = (C_INPUTS > 6 ? MG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMH = (C_INPUTS > 7 ? MH : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAA = (C_INPUTS > 8 ? MAA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAB = (C_INPUTS > 9 ? MAB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAC = (C_INPUTS > 10 ? MAC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAD = (C_INPUTS > 11 ? MAD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAE = (C_INPUTS > 12 ? MAE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAF = (C_INPUTS > 13 ? MAF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAG = (C_INPUTS > 14 ? MAG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAH = (C_INPUTS > 15 ? MAH : `allmyXs);
+    wire [C_WIDTH-1 : 0] intMBA = (C_INPUTS > 16 ? MBA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBB = (C_INPUTS > 17 ? MBB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBC = (C_INPUTS > 18 ? MBC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBD = (C_INPUTS > 19 ? MBD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBE = (C_INPUTS > 20 ? MBE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBF = (C_INPUTS > 21 ? MBF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBG = (C_INPUTS > 22 ? MBG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBH = (C_INPUTS > 23 ? MBH : `allmyXs);
+    wire [C_WIDTH-1 : 0] intMCA = (C_INPUTS > 24 ? MCA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCB = (C_INPUTS > 25 ? MCB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCC = (C_INPUTS > 26 ? MCC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCD = (C_INPUTS > 27 ? MCD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCE = (C_INPUTS > 28 ? MCE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCF = (C_INPUTS > 29 ? MCF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCG = (C_INPUTS > 30 ? MCG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCH = (C_INPUTS > 31 ? MCH : `allmyXs);
+
+	reg  [C_WIDTH-1 : 0] intO;
+	reg [C_WIDTH-1 : 0] intQ;
+
+        wire [C_WIDTH-1 : 0] STAGE1;
+	wire [C_WIDTH-1 : 0] STAGE2;
+	wire [C_SEL_WIDTH-1 : 0] intS = S;	 
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allmyXs);
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allmyXs);
+	wire intEN;
+	
+
+	assign intEN = defval(EN, C_HAS_EN, 1);
+
+
+	integer j, k, j1, k1;
+	integer m, unknown, m1, unknown1;
+	
+	// Register on output by default
+
+        
+        C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+	      REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), 
+			  .Q(STAGE1)); 
+        
+        /* Just in case someone would want full register options on this register...
+        C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+	      REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), 
+			  .Q(STAGE1)); 
+        */
+
+        C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		  REG2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE2)); 
+
+
+	initial 
+	begin
+
+		#1;
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(intS[j] === 1)
+				k = k + m;
+			else if(intS[j] === 1'bz || intS[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+
+		if(intEN === 1'b0)
+			intO <= #1 `allmyZs;
+		else if(intEN === 1'bx)
+			intO <= #1 `allmyXs;
+		else if(unknown == 1)
+			intO <= #1 `allmyXs;
+		else if (k == 1) 
+			intO <= #1 intMA;
+		else if (k == 2) 
+			intO <= #1 intMB;
+		else if (k == 3) 
+			intO <= #1 intMC;
+		else if (k == 4) 
+			intO <= #1 intMD;
+		else if (k == 5) 
+			intO <= #1 intME;
+		else if (k == 6) 
+			intO <= #1 intMF;
+		else if (k == 7) 
+			intO <= #1 intMG;
+		else if (k == 8) 
+			intO <= #1 intMH;
+                 else if (k == 9) 
+			intO <= #1 intMAA;
+		else if (k == 10) 
+			intO <= #1 intMAB;
+		else if (k == 11) 
+			intO <= #1 intMAC;
+		else if (k == 12) 
+			intO <= #1 intMAD;
+		else if (k == 13) 
+			intO <= #1 intMAE;
+		else if (k == 14) 
+			intO <= #1 intMAF;
+		else if (k == 15) 
+			intO <= #1 intMAG;
+		else if (k == 16) 
+			intO <= #1 intMAH;
+		else if (k == 17) 
+			intO <= #1 intMBA;
+		else if (k == 18) 
+			intO <= #1 intMBB;
+		else if (k == 19) 
+			intO <= #1 intMBC;
+		else if (k == 20) 
+			intO <= #1 intMBD;
+		else if (k == 21) 
+			intO <= #1 intMBE;
+		else if (k == 22) 
+			intO <= #1 intMBF;
+		else if (k == 23) 
+			intO <= #1 intMBG;
+		else if (k == 24) 
+			intO <= #1 intMBH;
+		else if (k == 25) 
+			intO <= #1 intMCA;
+		else if (k == 26) 
+			intO <= #1 intMCB;
+		else if (k == 27) 
+			intO <= #1 intMCC;
+		else if (k == 28) 
+			intO <= #1 intMCD;
+		else if (k == 29) 
+			intO <= #1 intMCE;
+		else if (k == 30) 
+			intO <= #1 intMCF;
+		else if (k == 31) 
+			intO <= #1 intMCG;
+		else if (k == 32) 
+			intO <= #1 intMCH;
+		else
+			intO <= #1 `allmyXs;
+
+	end
+	
+	always@(intMA or intMB or intMC or intMD or intME or intMF or intMG or intMH or 
+	        intMAA or intMAB or intMAC or intMAD or intMAE or intMAF or intMAG or intMAH or
+                intMBA or intMBB or intMBC or intMBD or intMBE or intMBF or intMBG or intMBH or
+                intMCA or intMCB or intMCC or intMCD or intMCE or intMCF or intMCG or intMCH or
+	        intEN or intS)
+	begin
+		
+		k1 = 1;
+		m1 = 1; 
+		unknown1 = 0;
+		for(j1 = 0; j1 < C_SEL_WIDTH; j1 = j1 + 1)
+		begin
+			if(intS[j1] === 1)
+				k1 = k1 + m1;
+			else if(intS[j1] === 1'bz || intS[j1] === 1'bx)
+				unknown1 = 1;
+			m1 = m1 * 2;
+		end
+
+		
+		if(intEN === 1'b0)
+			intO = #1 `allmyZs;
+		else if(intEN === 1'bx)
+			intO = #1 `allmyXs;
+		else if(unknown1 == 1)
+			intO <= #1 `allmyXs;
+		else if (k1 == 1) 
+			intO <= #1 intMA;
+		else if (k1 == 2) 
+			intO <= #1 intMB;
+		else if (k1 == 3) 
+			intO <= #1 intMC;
+		else if (k1 == 4) 
+			intO <= #1 intMD;
+		else if (k1 == 5) 
+			intO <= #1 intME;
+		else if (k1 == 6) 
+			intO <= #1 intMF;
+		else if (k1 == 7) 
+			intO <= #1 intMG;
+		else if (k1 == 8) 
+			intO <= #1 intMH;
+		else if (k1 == 9) 
+			intO <= #1 intMAA;
+		else if (k1 == 10) 
+			intO <= #1 intMAB;
+		else if (k1 == 11) 
+			intO <= #1 intMAC;
+		else if (k1 == 12) 
+			intO <= #1 intMAD;
+		else if (k1 == 13) 
+			intO <= #1 intMAE;
+		else if (k1 == 14) 
+			intO <= #1 intMAF;
+		else if (k1 == 15) 
+			intO <= #1 intMAG;
+		else if (k1 == 16) 
+			intO <= #1 intMAH;
+		else if (k1 == 17) 
+			intO <= #1 intMBA;
+		else if (k1 == 18) 
+			intO <= #1 intMBB;
+		else if (k1 == 19) 
+			intO <= #1 intMBC;
+		else if (k1 == 20) 
+			intO <= #1 intMBD;
+		else if (k1 == 21) 
+			intO <= #1 intMBE;
+		else if (k1 == 22) 
+			intO <= #1 intMBF;
+		else if (k1 == 23) 
+			intO <= #1 intMBG;
+		else if (k1 == 24) 
+			intO <= #1 intMBH;
+		else if (k1 == 25) 
+			intO <= #1 intMCA;
+		else if (k1 == 26) 
+			intO <= #1 intMCB;
+		else if (k1 == 27) 
+			intO <= #1 intMCC;
+		else if (k1 == 28) 
+			intO <= #1 intMCD;
+		else if (k1 == 29) 
+			intO <= #1 intMCE;
+		else if (k1 == 30) 
+			intO <= #1 intMCF;
+		else if (k1 == 31) 
+			intO <= #1 intMCG;
+		else if (k1 == 32) 
+			intO <= #1 intMCH;
+		else
+			intO <= #1 `allmyXs;  
+                           
+	end
+	
+// Register output settings       
+always   
+begin
+     //------------------------------
+     //-- REGISTER CLOCKED OUTPUTS --
+     //------------------------------
+        if (C_LATENCY === 1)
+             intQ = STAGE1;
+            else
+             intQ = STAGE2; 
+        @(STAGE1 or STAGE2);       
+end
+     
+		
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_lut_based
+`undef c_buft_based
+
+`undef allmyXs
+`undef allmyZs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V7_0.v

@@ -0,0 +1,444 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Id: C_MUX_BUS_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_MUX_BUS_V7_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BUS_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+`define c_lut_based 0
+`define c_buft_based 1
+
+
+
+`define allmyXs {C_WIDTH{1'bx}}
+`define allmyZs {C_WIDTH{1'bz}}
+
+module C_MUX_BUS_V7_0 (MA, MB, MC, MD, ME, MF, MG, MH, 
+                       MAA, MAB, MAC, MAD, MAE, MAF, MAG, MAH,
+                       MBA, MBB, MBC, MBD, MBE, MBF, MBG, MBH, 
+                       MCA, MCB, MCC, MCD, MCE, MCF, MCG, MCH, 
+                       S, CLK, CE, EN, ACLR, ASET, AINIT, 
+                       SCLR, SSET, SINIT, O, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 		    = 0;
+	parameter C_HAS_EN          = 0;
+	parameter C_HAS_O           = 0;
+	parameter C_HAS_Q           = 1;
+	parameter C_HAS_SCLR 		= 1;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 1;
+	parameter C_HEIGHT          = 0;
+	parameter C_INPUTS 		    = 2;
+    parameter C_LATENCY         = 1; 				
+	parameter C_MUX_TYPE 		= `c_lut_based;
+	parameter C_SEL_WIDTH 		= 1; 				
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 2;
+
+    // Parameters, used to drive additional register, for pipelining.
+    parameter PIPE_HAS_ACLR  = (C_LATENCY == 1 ? C_HAS_ACLR  : 1'b0);
+    parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0);
+    parameter PIPE_HAS_ASET  = (C_LATENCY == 1 ? C_HAS_ASET  : 1'b0);
+    parameter PIPE_HAS_SSET  = (C_LATENCY == 1 ? C_HAS_SSET  : 1'b0);
+    parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0);
+
+
+	input [C_WIDTH-1 : 0] MA;
+	input [C_WIDTH-1 : 0] MB;
+	input [C_WIDTH-1 : 0] MC;
+	input [C_WIDTH-1 : 0] MD;
+	input [C_WIDTH-1 : 0] ME;
+	input [C_WIDTH-1 : 0] MF;
+	input [C_WIDTH-1 : 0] MG;
+	input [C_WIDTH-1 : 0] MH;
+    input [C_WIDTH-1 : 0] MAA;
+	input [C_WIDTH-1 : 0] MAB;
+	input [C_WIDTH-1 : 0] MAC;
+	input [C_WIDTH-1 : 0] MAD;
+	input [C_WIDTH-1 : 0] MAE;
+	input [C_WIDTH-1 : 0] MAF;
+	input [C_WIDTH-1 : 0] MAG;
+	input [C_WIDTH-1 : 0] MAH;
+    input [C_WIDTH-1 : 0] MBA;
+	input [C_WIDTH-1 : 0] MBB;
+	input [C_WIDTH-1 : 0] MBC;
+	input [C_WIDTH-1 : 0] MBD;
+	input [C_WIDTH-1 : 0] MBE;
+	input [C_WIDTH-1 : 0] MBF;
+	input [C_WIDTH-1 : 0] MBG;
+	input [C_WIDTH-1 : 0] MBH;
+    input [C_WIDTH-1 : 0] MCA;
+	input [C_WIDTH-1 : 0] MCB;
+	input [C_WIDTH-1 : 0] MCC;
+	input [C_WIDTH-1 : 0] MCD;
+	input [C_WIDTH-1 : 0] MCE;
+	input [C_WIDTH-1 : 0] MCF;
+	input [C_WIDTH-1 : 0] MCG;
+	input [C_WIDTH-1 : 0] MCH;
+	input [C_SEL_WIDTH-1 : 0] S;
+	input CLK;
+	input CE;
+	input EN;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] O;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	// Internal values to drive signals when input is missing
+	wire [C_WIDTH-1 : 0] intMA = MA;
+	wire [C_WIDTH-1 : 0] intMB = MB;
+	wire [C_WIDTH-1 : 0] intMC = (C_INPUTS > 2 ? MC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMD = (C_INPUTS > 3 ? MD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intME = (C_INPUTS > 4 ? ME : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMF = (C_INPUTS > 5 ? MF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMG = (C_INPUTS > 6 ? MG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMH = (C_INPUTS > 7 ? MH : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAA = (C_INPUTS > 8 ? MAA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAB = (C_INPUTS > 9 ? MAB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAC = (C_INPUTS > 10 ? MAC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAD = (C_INPUTS > 11 ? MAD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAE = (C_INPUTS > 12 ? MAE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAF = (C_INPUTS > 13 ? MAF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAG = (C_INPUTS > 14 ? MAG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMAH = (C_INPUTS > 15 ? MAH : `allmyXs);
+    wire [C_WIDTH-1 : 0] intMBA = (C_INPUTS > 16 ? MBA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBB = (C_INPUTS > 17 ? MBB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBC = (C_INPUTS > 18 ? MBC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBD = (C_INPUTS > 19 ? MBD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBE = (C_INPUTS > 20 ? MBE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBF = (C_INPUTS > 21 ? MBF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBG = (C_INPUTS > 22 ? MBG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMBH = (C_INPUTS > 23 ? MBH : `allmyXs);
+    wire [C_WIDTH-1 : 0] intMCA = (C_INPUTS > 24 ? MCA : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCB = (C_INPUTS > 25 ? MCB : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCC = (C_INPUTS > 26 ? MCC : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCD = (C_INPUTS > 27 ? MCD : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCE = (C_INPUTS > 28 ? MCE : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCF = (C_INPUTS > 29 ? MCF : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCG = (C_INPUTS > 30 ? MCG : `allmyXs);
+	wire [C_WIDTH-1 : 0] intMCH = (C_INPUTS > 31 ? MCH : `allmyXs);
+
+	reg  [C_WIDTH-1 : 0] intO;
+	reg [C_WIDTH-1 : 0] intQ;
+
+        wire [C_WIDTH-1 : 0] STAGE1;
+	wire [C_WIDTH-1 : 0] STAGE2;
+	wire [C_SEL_WIDTH-1 : 0] intS = S;	 
+	wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allmyXs);
+	wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allmyXs);
+	wire intEN;
+	
+
+	assign intEN = defval(EN, C_HAS_EN, 1);
+
+
+	integer j, k, j1, k1;
+	integer m, unknown, m1, unknown1;
+	
+	// Register on output by default
+
+        
+        C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+	      REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), 
+			  .Q(STAGE1)); 
+        
+        /* Just in case someone would want full register options on this register...
+        C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+	      REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), 
+			  .Q(STAGE1)); 
+        */
+
+        C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET,
+			   C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET,
+			   C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH)
+		  REG2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET),
+			  .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT),
+			  .Q(STAGE2)); 
+
+
+	initial 
+	begin
+
+		#1;
+		k = 1;
+		m = 1; 
+		unknown = 0;
+		for(j = 0; j < C_SEL_WIDTH; j = j + 1)
+		begin
+			if(intS[j] === 1)
+				k = k + m;
+			else if(intS[j] === 1'bz || intS[j] === 1'bx)
+				unknown = 1;
+			m = m * 2;
+		end
+
+		if(intEN === 1'b0)
+			intO <= #1 `allmyZs;
+		else if(intEN === 1'bx)
+			intO <= #1 `allmyXs;
+		else if(unknown == 1)
+			intO <= #1 `allmyXs;
+		else if (k == 1) 
+			intO <= #1 intMA;
+		else if (k == 2) 
+			intO <= #1 intMB;
+		else if (k == 3) 
+			intO <= #1 intMC;
+		else if (k == 4) 
+			intO <= #1 intMD;
+		else if (k == 5) 
+			intO <= #1 intME;
+		else if (k == 6) 
+			intO <= #1 intMF;
+		else if (k == 7) 
+			intO <= #1 intMG;
+		else if (k == 8) 
+			intO <= #1 intMH;
+                 else if (k == 9) 
+			intO <= #1 intMAA;
+		else if (k == 10) 
+			intO <= #1 intMAB;
+		else if (k == 11) 
+			intO <= #1 intMAC;
+		else if (k == 12) 
+			intO <= #1 intMAD;
+		else if (k == 13) 
+			intO <= #1 intMAE;
+		else if (k == 14) 
+			intO <= #1 intMAF;
+		else if (k == 15) 
+			intO <= #1 intMAG;
+		else if (k == 16) 
+			intO <= #1 intMAH;
+		else if (k == 17) 
+			intO <= #1 intMBA;
+		else if (k == 18) 
+			intO <= #1 intMBB;
+		else if (k == 19) 
+			intO <= #1 intMBC;
+		else if (k == 20) 
+			intO <= #1 intMBD;
+		else if (k == 21) 
+			intO <= #1 intMBE;
+		else if (k == 22) 
+			intO <= #1 intMBF;
+		else if (k == 23) 
+			intO <= #1 intMBG;
+		else if (k == 24) 
+			intO <= #1 intMBH;
+		else if (k == 25) 
+			intO <= #1 intMCA;
+		else if (k == 26) 
+			intO <= #1 intMCB;
+		else if (k == 27) 
+			intO <= #1 intMCC;
+		else if (k == 28) 
+			intO <= #1 intMCD;
+		else if (k == 29) 
+			intO <= #1 intMCE;
+		else if (k == 30) 
+			intO <= #1 intMCF;
+		else if (k == 31) 
+			intO <= #1 intMCG;
+		else if (k == 32) 
+			intO <= #1 intMCH;
+		else
+			intO <= #1 `allmyXs;
+
+	end
+	
+	always@(intMA or intMB or intMC or intMD or intME or intMF or intMG or intMH or 
+	        intMAA or intMAB or intMAC or intMAD or intMAE or intMAF or intMAG or intMAH or
+                intMBA or intMBB or intMBC or intMBD or intMBE or intMBF or intMBG or intMBH or
+                intMCA or intMCB or intMCC or intMCD or intMCE or intMCF or intMCG or intMCH or
+	        intEN or intS)
+	begin
+		
+		k1 = 1;
+		m1 = 1; 
+		unknown1 = 0;
+		for(j1 = 0; j1 < C_SEL_WIDTH; j1 = j1 + 1)
+		begin
+			if(intS[j1] === 1)
+				k1 = k1 + m1;
+			else if(intS[j1] === 1'bz || intS[j1] === 1'bx)
+				unknown1 = 1;
+			m1 = m1 * 2;
+		end
+
+		
+		if(intEN === 1'b0)
+			intO <= #1 `allmyZs;
+		else if(intEN === 1'bx)
+			intO <= #1 `allmyXs;
+		else if(unknown1 == 1)
+			intO <= #1 `allmyXs;
+		else if (k1 == 1) 
+			intO <= #1 intMA;
+		else if (k1 == 2) 
+			intO <= #1 intMB;
+		else if (k1 == 3) 
+			intO <= #1 intMC;
+		else if (k1 == 4) 
+			intO <= #1 intMD;
+		else if (k1 == 5) 
+			intO <= #1 intME;
+		else if (k1 == 6) 
+			intO <= #1 intMF;
+		else if (k1 == 7) 
+			intO <= #1 intMG;
+		else if (k1 == 8) 
+			intO <= #1 intMH;
+		else if (k1 == 9) 
+			intO <= #1 intMAA;
+		else if (k1 == 10) 
+			intO <= #1 intMAB;
+		else if (k1 == 11) 
+			intO <= #1 intMAC;
+		else if (k1 == 12) 
+			intO <= #1 intMAD;
+		else if (k1 == 13) 
+			intO <= #1 intMAE;
+		else if (k1 == 14) 
+			intO <= #1 intMAF;
+		else if (k1 == 15) 
+			intO <= #1 intMAG;
+		else if (k1 == 16) 
+			intO <= #1 intMAH;
+		else if (k1 == 17) 
+			intO <= #1 intMBA;
+		else if (k1 == 18) 
+			intO <= #1 intMBB;
+		else if (k1 == 19) 
+			intO <= #1 intMBC;
+		else if (k1 == 20) 
+			intO <= #1 intMBD;
+		else if (k1 == 21) 
+			intO <= #1 intMBE;
+		else if (k1 == 22) 
+			intO <= #1 intMBF;
+		else if (k1 == 23) 
+			intO <= #1 intMBG;
+		else if (k1 == 24) 
+			intO <= #1 intMBH;
+		else if (k1 == 25) 
+			intO <= #1 intMCA;
+		else if (k1 == 26) 
+			intO <= #1 intMCB;
+		else if (k1 == 27) 
+			intO <= #1 intMCC;
+		else if (k1 == 28) 
+			intO <= #1 intMCD;
+		else if (k1 == 29) 
+			intO <= #1 intMCE;
+		else if (k1 == 30) 
+			intO <= #1 intMCF;
+		else if (k1 == 31) 
+			intO <= #1 intMCG;
+		else if (k1 == 32) 
+			intO <= #1 intMCH;
+		else
+			intO <= #1 `allmyXs;  
+                           
+	end
+	
+// Register output settings       
+always   
+begin
+     //------------------------------
+     //-- REGISTER CLOCKED OUTPUTS --
+     //------------------------------
+        if (C_LATENCY === 1)
+             intQ = STAGE1;
+            else
+             intQ = STAGE2; 
+        @(STAGE1 or STAGE2);       
+end
+     
+		
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+`undef c_lut_based
+`undef c_buft_based
+
+`undef allmyXs
+`undef allmyZs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V4_0.v

@@ -0,0 +1,51 @@
+/* $Id: C_MUX_SLICE_BUFE_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_MUX_SLICE_BUFE_V4_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFE_V4_0 module
+*/
+
+
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+
+module C_MUX_SLICE_BUFE_V4_0 (I, OE, O);
+
+	parameter C_WIDTH = 16;						/* Width of the single input */	
+
+	input [C_WIDTH-1 : 0] I;
+	input OE;
+	output [C_WIDTH-1 : 0] O;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+
+	wire [C_WIDTH-1 : 0] #1 O = intO;
+	
+	initial 
+	begin
+
+		if (OE == 1) 
+			intO = I;
+		else if (OE == 0) 
+			intO = `allZs;
+		else
+			intO = `allXs;			
+	end
+	
+	always@(I or OE)
+	begin
+		if (OE == 1) 
+			intO <= I;
+		else if (OE == 0) 
+			intO <= `allZs;
+		else
+			intO <= `allXs;			
+	end
+		
+endmodule
+
+`undef allXs
+`undef allZs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V5_0.v

@@ -0,0 +1,51 @@
+/* $Id: C_MUX_SLICE_BUFE_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $
+--
+-- Filename - C_MUX_SLICE_BUFE_V5_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFE_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+
+module C_MUX_SLICE_BUFE_V5_0 (I, OE, O);
+
+	parameter C_WIDTH = 16;						/* Width of the single input */	
+
+	input [C_WIDTH-1 : 0] I;
+	input OE;
+	output [C_WIDTH-1 : 0] O;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+
+	wire [C_WIDTH-1 : 0] #1 O = intO;
+	
+	initial 
+	begin
+
+		if (OE == 1) 
+			intO = I;
+		else if (OE == 0) 
+			intO = `allZs;
+		else
+			intO = `allXs;			
+	end
+	
+	always@(I or OE)
+	begin
+		if (OE == 1) 
+			intO <= I;
+		else if (OE == 0) 
+			intO <= `allZs;
+		else
+			intO <= `allXs;			
+	end
+		
+endmodule
+
+`undef allXs
+`undef allZs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V6_0.v

@@ -0,0 +1,60 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_MUX_SLICE_BUFE_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_MUX_SLICE_BUFE_V6_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFE_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+
+module C_MUX_SLICE_BUFE_V6_0 (I, OE, O);
+
+	parameter C_WIDTH = 16;						/* Width of the single input */	
+
+	input [C_WIDTH-1 : 0] I;
+	input OE;
+	output [C_WIDTH-1 : 0] O;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+
+	wire [C_WIDTH-1 : 0] #1 O = intO;
+	
+	initial 
+	begin
+
+		if (OE == 1) 
+			intO = I;
+		else if (OE == 0) 
+			intO = `allZs;
+		else
+			intO = `allXs;			
+	end
+	
+	always@(I or OE)
+	begin
+		if (OE == 1) 
+			intO <= I;
+		else if (OE == 0) 
+			intO <= `allZs;
+		else
+			intO <= `allXs;			
+	end
+		
+endmodule
+
+`undef allXs
+`undef allZs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V7_0.v

@@ -0,0 +1,89 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Id: C_MUX_SLICE_BUFE_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_MUX_SLICE_BUFE_V7_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFE_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+
+module C_MUX_SLICE_BUFE_V7_0 (I, OE, O);
+
+	parameter C_WIDTH = 16;						/* Width of the single input */	
+
+	input [C_WIDTH-1 : 0] I;
+	input OE;
+	output [C_WIDTH-1 : 0] O;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+
+	wire [C_WIDTH-1 : 0] #1 O = intO;
+	
+	initial 
+	begin
+
+		if (OE == 1) 
+			intO = I;
+		else if (OE == 0) 
+			intO = `allZs;
+		else
+			intO = `allXs;			
+	end
+	
+	always@(I or OE)
+	begin
+		if (OE == 1) 
+			intO <= I;
+		else if (OE == 0) 
+			intO <= `allZs;
+		else
+			intO <= `allXs;			
+	end
+		
+endmodule
+
+`undef allXs
+`undef allZs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V4_0.v

@@ -0,0 +1,51 @@
+/* $Id: C_MUX_SLICE_BUFT_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_MUX_SLICE_BUFT_V4_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFT_V4_0 module
+*/
+
+
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+
+module C_MUX_SLICE_BUFT_V4_0 (I, T, O);
+
+	parameter C_WIDTH = 16;						/* Width of the single input */	
+
+	input [C_WIDTH-1 : 0] I;
+	input T;
+	output [C_WIDTH-1 : 0] O;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+
+	wire [C_WIDTH-1 : 0] #1 O = intO;
+	
+	initial 
+	begin
+
+		if (T == 0) 
+			intO = I;
+		else if (T == 1) 
+			intO = `allZs;
+		else
+			intO = `allXs;			
+	end
+	
+	always@(I or T)
+	begin
+		if (T == 0) 
+			intO <= I;
+		else if (T == 1) 
+			intO <= `allZs;
+		else
+			intO <= `allXs;			
+	end
+		
+endmodule
+
+`undef allXs
+`undef allZs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V5_0.v

@@ -0,0 +1,52 @@
+/* $Id: C_MUX_SLICE_BUFT_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $
+--
+-- Filename - C_MUX_SLICE_BUFT_V5_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFT_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+
+module C_MUX_SLICE_BUFT_V5_0 (I, T, O);
+
+	parameter C_WIDTH = 16;						/* Width of the single input */	
+
+	input [C_WIDTH-1 : 0] I;
+	input T;
+	output [C_WIDTH-1 : 0] O;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+
+	wire [C_WIDTH-1 : 0] #1 O = intO;
+	
+	initial 
+	begin
+
+		if (T == 0) 
+			intO = I;
+		else if (T == 1) 
+			intO = `allZs;
+		else
+			intO = `allXs;			
+	end
+	
+	always@(I or T)
+	begin
+		if (T == 0) 
+			intO <= I;
+		else if (T == 1) 
+			intO <= `allZs;
+		else
+			intO <= `allXs;			
+	end
+		
+endmodule
+
+`undef allXs
+`undef allZs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V6_0.v

@@ -0,0 +1,61 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_MUX_SLICE_BUFT_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_MUX_SLICE_BUFT_V6_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFT_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+
+module C_MUX_SLICE_BUFT_V6_0 (I, T, O);
+
+	parameter C_WIDTH = 16;						/* Width of the single input */	
+
+	input [C_WIDTH-1 : 0] I;
+	input T;
+	output [C_WIDTH-1 : 0] O;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+
+	wire [C_WIDTH-1 : 0] #1 O = intO;
+	
+	initial 
+	begin
+
+		if (T == 0) 
+			intO = I;
+		else if (T == 1) 
+			intO = `allZs;
+		else
+			intO = `allXs;			
+	end
+	
+	always@(I or T)
+	begin
+		if (T == 0) 
+			intO <= I;
+		else if (T == 1) 
+			intO <= `allZs;
+		else
+			intO <= `allXs;			
+	end
+		
+endmodule
+
+`undef allXs
+`undef allZs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V7_0.v

@@ -0,0 +1,90 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Id: C_MUX_SLICE_BUFT_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_MUX_SLICE_BUFT_V7_0.v
+-- Author - Xilinx
+-- Creation - 4 Feb 1999
+--
+-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFT_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define allXs {C_WIDTH{1'bx}}
+`define allZs {C_WIDTH{1'bz}}
+
+module C_MUX_SLICE_BUFT_V7_0 (I, T, O);
+
+	parameter C_WIDTH = 16;						/* Width of the single input */	
+
+	input [C_WIDTH-1 : 0] I;
+	input T;
+	output [C_WIDTH-1 : 0] O;
+	 
+	reg [C_WIDTH-1 : 0] intO;
+
+	wire [C_WIDTH-1 : 0] #1 O = intO;
+	
+	initial 
+	begin
+
+		if (T == 0) 
+			intO = I;
+		else if (T == 1) 
+			intO = `allZs;
+		else
+			intO = `allXs;			
+	end
+	
+	always@(I or T)
+	begin
+		if (T == 0) 
+			intO <= I;
+		else if (T == 1) 
+			intO <= `allZs;
+		else
+			intO <= `allXs;			
+	end
+		
+endmodule
+
+`undef allXs
+`undef allZs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V4_0.v

@@ -0,0 +1,333 @@
+/* $Id: C_REG_FD_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_REG_FD_V4_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V4_0 module
+*/
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define all1s {C_WIDTH{1'b1}}
+`define all0s 'b0
+`define allXs {C_WIDTH{1'bx}}
+
+module C_REG_FD_V4_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 16; 		
+	
+
+	input [C_WIDTH-1 : 0] D;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] data;
+	reg [C_WIDTH-1 : 0] datatmp;
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	wire intCLK;
+	 
+	wire [C_WIDTH-1 : 0] #1 Q = data;
+
+	// Sort out default values for missing ports
+	
+	assign intCLK = CLK;
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intCE = ((((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) &&
+					(C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1)) ||
+					(C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) &&
+					(C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ? 
+						(CE | intSCLR | intSSET | intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1));
+	
+	reg lastCLK;
+	reg lastintACLR;
+	reg lastintASET;
+	
+	reg [C_WIDTH-1 : 0] AIV;
+	reg [C_WIDTH-1 : 0] SIV;
+	
+	
+	integer i;
+	integer ASYNC_CTRL;
+	
+	initial 
+	begin
+		ASYNC_CTRL <= 1;
+		lastCLK = #1 1'b0;
+		lastintACLR <= 1'b0;
+		lastintASET <= 1'b0;
+		AIV = to_bits(C_AINIT_VAL);
+		SIV = to_bits(C_SINIT_VAL);
+		if(C_HAS_ACLR === 1)
+			data <= #1 `all0s;
+		else if(C_HAS_ASET === 1)
+			data <= #1 `all1s;
+		else if(C_HAS_AINIT === 1)
+		    data <= #1 AIV;
+		else if(C_HAS_SCLR === 1)
+			data <= #1 `all0s;
+		else if(C_HAS_SSET === 1)
+			data <= #1 `all1s;
+		else if(C_HAS_SINIT === 1)
+			data <= #1 SIV;
+		else
+			data <= #1 AIV;			
+	end
+
+        // intCE removed from sensitivity list.  
+        // Fix CR 128989
+        //Neil Ritchie 8 Dec 2000
+	
+	always@(posedge intCLK or intACLR or intASET or intAINIT)
+	begin
+		datatmp = data;
+		
+		for(i = 0; i < C_WIDTH; i = i + 1)
+		begin
+			if(intACLR === 1'b1)
+				datatmp[i] = 1'b0;
+			else if(intACLR === 1'b0 && intASET === 1'b1)
+				datatmp[i] = 1'b1;
+			else if(intAINIT === 1'b1)
+				datatmp[i] = AIV[i];
+			else if(intACLR === 1'bx && intASET !== 1'b0)
+				datatmp[i] = 1'bx;
+			else if(intACLR != lastintACLR && lastintASET != intASET 
+						&& lastintACLR === 1'b1 && lastintASET === 1'b1
+						&& intACLR === 1'b0 && intASET === 1'b0)
+				datatmp[i] = 1'bx;
+			else 
+			begin
+				ASYNC_CTRL = 0;
+				if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1)
+				begin
+					if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+						(C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+					if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+					(C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+					if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp[i] = D[i];
+					else if(intCE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp[i] = 1'bx;
+
+					if(intSINIT === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0)
+						datatmp[i] = SIV[i];
+					else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+					else if(intSINIT === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+
+					if(intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0)
+						datatmp[i] = 1'b0;
+					else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp[i] = 1'bx;
+					else if(intSCLR === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp[i] = 1'bx;
+						
+					if(intSSET === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0)
+						datatmp[i] = 1'b1;
+					else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp[i] = 1'bx;
+					else if(intSSET === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp[i] = 1'bx;
+				end
+				else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx)
+							|| (lastCLK === 1'bx && intCLK === 1'b1)))
+				begin
+					if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+						datatmp[i] = 1'bx;
+					else if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+						datatmp[i] = 1'bx;
+					
+					if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i])
+						datatmp[i] = 1'bx;
+					
+					if(intSINIT !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+						
+					if(intSCLR !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0)
+						datatmp[i] = 1'bx;
+						
+					if(intSSET !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1)
+						datatmp[i] = 1'bx;
+				end
+
+				if(intACLR === 1'b0 && intASET === 1'bx)
+				begin
+					if(datatmp[i] !== 1'b1)
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+				else if(intACLR === 1'bx && intASET === 1'b0)
+				begin
+					if(datatmp[i] !== 1'b0)
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+				else if(intAINIT === 1'bx)
+				begin
+					if(datatmp[i] !== AIV[i])
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+			end
+		end
+		
+		data <= datatmp;
+	end	
+							
+	
+	always@(intACLR or intASET)
+	begin
+		lastintACLR <= intACLR;
+		lastintASET <= intASET;
+		if($time != 0)
+			if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE
+				data <= `allXs;
+	end
+	
+	always@(intCLK)
+		lastCLK <= intCLK;
+	
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+				to_bits[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bits[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+				else
+				begin
+					$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef all1s
+`undef all0s
+`undef allXs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V5_0.v

@@ -0,0 +1,334 @@
+/* $Id: C_REG_FD_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $
+--
+-- Filename - C_REG_FD_V5_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define all1s {C_WIDTH{1'b1}}
+`define all0s 'b0
+`define allXs {C_WIDTH{1'bx}}
+
+module C_REG_FD_V5_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 16; 		
+	
+
+	input [C_WIDTH-1 : 0] D;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] data;
+	reg [C_WIDTH-1 : 0] datatmp;
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	wire intCLK;
+	 
+	wire [C_WIDTH-1 : 0] #1 Q = data;
+
+	// Sort out default values for missing ports
+	
+	assign intCLK = CLK;
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intCE = ((((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) &&
+					(C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1)) ||
+					(C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) &&
+					(C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ? 
+						(CE | intSCLR | intSSET | intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1));
+	
+	reg lastCLK;
+	reg lastintACLR;
+	reg lastintASET;
+	
+	reg [C_WIDTH-1 : 0] AIV;
+	reg [C_WIDTH-1 : 0] SIV;
+	
+	
+	integer i;
+	integer ASYNC_CTRL;
+	
+	initial 
+	begin
+		ASYNC_CTRL <= 1;
+		lastCLK = #1 1'b0;
+		lastintACLR <= 1'b0;
+		lastintASET <= 1'b0;
+		AIV = to_bits(C_AINIT_VAL);
+		SIV = to_bits(C_SINIT_VAL);
+		if(C_HAS_ACLR === 1)
+			data <= #1 `all0s;
+		else if(C_HAS_ASET === 1)
+			data <= #1 `all1s;
+		else if(C_HAS_AINIT === 1)
+		    data <= #1 AIV;
+		else if(C_HAS_SCLR === 1)
+			data <= #1 `all0s;
+		else if(C_HAS_SSET === 1)
+			data <= #1 `all1s;
+		else if(C_HAS_SINIT === 1)
+			data <= #1 SIV;
+		else
+			data <= #1 AIV;			
+	end
+
+        // intCE removed from sensitivity list.  
+        // Fix CR 128989
+        //Neil Ritchie 8 Dec 2000
+	
+	always@(posedge intCLK or intACLR or intASET or intAINIT)
+	begin
+		datatmp = data;
+		
+		for(i = 0; i < C_WIDTH; i = i + 1)
+		begin
+			if(intACLR === 1'b1)
+				datatmp[i] = 1'b0;
+			else if(intACLR === 1'b0 && intASET === 1'b1)
+				datatmp[i] = 1'b1;
+			else if(intAINIT === 1'b1)
+				datatmp[i] = AIV[i];
+			else if(intACLR === 1'bx && intASET !== 1'b0)
+				datatmp[i] = 1'bx;
+			else if(intACLR != lastintACLR && lastintASET != intASET 
+						&& lastintACLR === 1'b1 && lastintASET === 1'b1
+						&& intACLR === 1'b0 && intASET === 1'b0)
+				datatmp[i] = 1'bx;
+			else 
+			begin
+				ASYNC_CTRL = 0;
+				if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1)
+				begin
+					if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+						(C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+					if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+					(C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+					if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp[i] = D[i];
+					else if(intCE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp[i] = 1'bx;
+
+					if(intSINIT === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0)
+						datatmp[i] = SIV[i];
+					else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+					else if(intSINIT === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+
+					if(intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0)
+						datatmp[i] = 1'b0;
+					else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp[i] = 1'bx;
+					else if(intSCLR === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp[i] = 1'bx;
+						
+					if(intSSET === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0)
+						datatmp[i] = 1'b1;
+					else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp[i] = 1'bx;
+					else if(intSSET === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp[i] = 1'bx;
+				end
+				else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx)
+							|| (lastCLK === 1'bx && intCLK === 1'b1)))
+				begin
+					if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+						datatmp[i] = 1'bx;
+					else if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+						datatmp[i] = 1'bx;
+					
+					if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i])
+						datatmp[i] = 1'bx;
+					
+					if(intSINIT !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+						
+					if(intSCLR !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0)
+						datatmp[i] = 1'bx;
+						
+					if(intSSET !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1)
+						datatmp[i] = 1'bx;
+				end
+
+				if(intACLR === 1'b0 && intASET === 1'bx)
+				begin
+					if(datatmp[i] !== 1'b1)
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+				else if(intACLR === 1'bx && intASET === 1'b0)
+				begin
+					if(datatmp[i] !== 1'b0)
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+				else if(intAINIT === 1'bx)
+				begin
+					if(datatmp[i] !== AIV[i])
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+			end
+		end
+		
+		data <= datatmp;
+	end	
+							
+	
+	always@(intACLR or intASET)
+	begin
+		lastintACLR <= intACLR;
+		lastintASET <= intASET;
+		if($time != 0)
+			if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE
+				data <= `allXs;
+	end
+	
+	always@(intCLK)
+		lastCLK <= intCLK;
+	
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+				to_bits[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bits[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef all1s
+`undef all0s
+`undef allXs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V6_0.v

@@ -0,0 +1,349 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_REG_FD_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $
+--
+-- Filename - C_REG_FD_V6_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define all1s {C_WIDTH{1'b1}}
+`define all0s 'b0
+`define allXs {C_WIDTH{1'bx}}
+
+module C_REG_FD_V6_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 16; 		
+	
+
+	input [C_WIDTH-1 : 0] D;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] data;
+	reg [C_WIDTH-1 : 0] datatmp;
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	wire intCLK;
+	 
+	wire [C_WIDTH-1 : 0] #1 Q = data;
+
+	// Sort out default values for missing ports
+	
+	assign intCLK = CLK;
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intCE = ((((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) &&
+					(C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1)) ||
+					(C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) &&
+					(C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ? 
+						(CE | intSCLR | intSSET | intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1));
+	
+	reg lastCLK;
+	reg lastintACLR;
+	reg lastintASET;
+	
+	reg [C_WIDTH-1 : 0] AIV;
+	reg [C_WIDTH-1 : 0] SIV;
+	
+	
+	integer i;
+	integer ASYNC_CTRL;
+	
+	initial 
+	begin
+		ASYNC_CTRL <= 1;
+		lastCLK = intCLK;
+		lastintACLR <= 1'b0;
+		lastintASET <= 1'b0;
+		AIV = to_bits(C_AINIT_VAL);
+		SIV = to_bits(C_SINIT_VAL);
+		if(C_HAS_ACLR === 1)
+			data <= #1 `all0s;
+		else if(C_HAS_ASET === 1)
+			data <= #1 `all1s;
+		else if(C_HAS_AINIT === 1)
+		    data <= #1 AIV;
+		else if(C_HAS_SCLR === 1)
+			data <= #1 `all0s;
+		else if(C_HAS_SSET === 1)
+			data <= #1 `all1s;
+		else if(C_HAS_SINIT === 1)
+			data <= #1 SIV;
+		else
+			data <= #1 AIV;			
+	end
+
+        // intCE removed from sensitivity list.  
+        // Fix CR 128989
+        //Neil Ritchie 8 Dec 2000
+	
+	always@(posedge intCLK or intACLR or intASET or intAINIT)
+	begin
+		datatmp = data;
+		
+//		for(i = 0; i < C_WIDTH; i = i + 1)
+//		begin
+			if(intACLR === 1'b1)
+				datatmp = `all0s;
+			else if(intACLR === 1'b0 && intASET === 1'b1)
+				datatmp = `all1s;
+			else if(intAINIT === 1'b1)
+				datatmp = AIV;
+			else if(intACLR === 1'bx && intASET !== 1'b0)
+				datatmp = `allXs;
+			else if(intACLR != lastintACLR && lastintASET != intASET 
+						&& lastintACLR === 1'b1 && lastintASET === 1'b1
+						&& intACLR === 1'b0 && intASET === 1'b0)
+				datatmp = `allXs;
+			else 
+			begin
+				ASYNC_CTRL = 0;
+				if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1)
+				begin
+					if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+						(C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+					begin
+						datatmp = `allXs;
+						ASYNC_CTRL = 1;
+					end
+					if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+					(C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+					begin
+						datatmp = `allXs;
+						ASYNC_CTRL = 1;
+					end
+					if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp = D;
+					else if(intCE === 1'bx && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp);
+
+					if(intSINIT === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0)
+						datatmp = SIV;
+					else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1))
+						datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp);
+					else if(intSINIT === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0))
+						datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp);
+
+					if(intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0)
+						datatmp = `all0s;
+					else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp = ~(~datatmp | `allXs);
+					else if(intSCLR === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp = ~(~datatmp | `allXs);
+						
+					if(intSSET === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0)
+						datatmp = `all1s;
+					else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp = datatmp | `allXs;
+					else if(intSSET === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp = datatmp | `allXs;
+				end
+				else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx)
+							|| (lastCLK === 1'bx && intCLK === 1'b1)))
+				begin
+					if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+						datatmp = `allXs;
+					else if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+						datatmp = `allXs;
+					
+					if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1)
+						datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp);
+					
+					if(intSINIT !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0))
+						datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp);
+						
+					if(intSCLR !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp = ~(~datatmp | `allXs);
+						
+					if(intSSET !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp = datatmp | `allXs;
+				end
+
+				if(intACLR === 1'b0 && intASET === 1'bx)
+				begin
+//					if(datatmp[i] !== 1'b1)
+//					begin
+//						datatmp[i] = 1'bx;
+//						ASYNC_CTRL = 1;
+//					end
+					ASYNC_CTRL = |(~datatmp) ? 1 : 0;
+                                        datatmp = datatmp | `allXs;
+				end
+				else if(intACLR === 1'bx && intASET === 1'b0)
+				begin
+//					if(datatmp[i] !== 1'b0)
+//					begin
+//						datatmp[i] = 1'bx;
+//						ASYNC_CTRL = 1;
+//					end
+                                        ASYNC_CTRL = |datatmp ? 1 : 0;
+					datatmp = datatmp & `allXs;
+				end
+				else if(intAINIT === 1'bx)
+				begin
+//					if(datatmp[i] !== AIV[i])
+//					begin
+//						datatmp[i] = 1'bx;
+//						ASYNC_CTRL = 1;
+//					end
+					ASYNC_CTRL = |(datatmp ^ AIV) ? 1 : 0;
+					datatmp = ~((~(datatmp ^ AIV) | `allXs) ^ datatmp);
+				end
+			end
+//		end
+		
+		data <= datatmp;
+	end	
+							
+	
+	always@(intACLR or intASET)
+	begin
+		lastintACLR <= intACLR;
+		lastintASET <= intASET;
+		if($time != 0)
+			if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE
+				data <= `allXs;
+	end
+	
+	always@(intCLK)
+		lastCLK <= intCLK;
+	
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+				to_bits[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bits[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef all1s
+`undef all0s
+`undef allXs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V7_0.v

@@ -0,0 +1,378 @@
+// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. 
+// This text/file contains proprietary, confidential 
+// information of Xilinx, Inc., is distributed under license 
+// from Xilinx, Inc., and may be used, copied and/or 
+// disclosed only pursuant to the terms of a valid license 
+// agreement with Xilinx, Inc. Xilinx hereby grants you 
+// a license to use this text/file solely for design, simulation, 
+// implementation and creation of design files limited 
+// to Xilinx devices or technologies. Use with non-Xilinx 
+// devices or technologies is expressly prohibited and 
+// immediately terminates your license unless covered by 
+// a separate agreement. 
+// 
+// Xilinx is providing this design, code, or information 
+// "as is" solely for use in developing programs and 
+// solutions for Xilinx devices. By providing this design, 
+// code, or information as one possible implementation of 
+// this feature, application or standard, Xilinx is making no 
+// representation that this implementation is free from any 
+// claims of infringement. You are responsible for 
+// obtaining any rights you may require for your implementation. 
+// Xilinx expressly disclaims any warranty whatsoever with 
+// respect to the adequacy of the implementation, including 
+// but not limited to any warranties or representations that this 
+// implementation is free from claims of infringement, implied 
+// warranties of merchantability or fitness for a particular 
+// purpose. 
+// 
+// Xilinx products are not intended for use in life support 
+// appliances, devices, or systems. Use in such applications are 
+// expressly prohibited. 
+// 
+// This copyright and support notice must be retained as part 
+// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. 
+// All rights reserved.
+
+
+
+/* $Id: C_REG_FD_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $
+--
+-- Filename - C_REG_FD_V7_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V7_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define all1s {C_WIDTH{1'b1}}
+`define all0s 'b0
+`define allXs {C_WIDTH{1'bx}}
+
+module C_REG_FD_V7_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_CE 			= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 16; 		
+	
+
+	input [C_WIDTH-1 : 0] D;
+	input CLK;
+	input CE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] data;
+	reg [C_WIDTH-1 : 0] datatmp;
+	// Internal values to drive signals when input is missing
+	wire intCE;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	wire intCLK;
+	 
+	wire [C_WIDTH-1 : 0] #1 Q = data;
+
+	// Sort out default values for missing ports
+	
+	assign intCLK = CLK;
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intCE = ((((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) &&
+					(C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1)) ||
+					(C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) &&
+					(C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ? 
+						(CE | intSCLR | intSSET | intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1));
+	
+	reg lastCLK;
+	reg lastintACLR;
+	reg lastintASET;
+	
+	reg [C_WIDTH-1 : 0] AIV;
+	reg [C_WIDTH-1 : 0] SIV;
+	
+	
+	integer i;
+	integer ASYNC_CTRL;
+	
+	initial 
+	begin
+		ASYNC_CTRL <= 1;
+		lastCLK = intCLK;
+		lastintACLR <= 1'b0;
+		lastintASET <= 1'b0;
+		AIV = to_bits(C_AINIT_VAL);
+		SIV = to_bits(C_SINIT_VAL);
+		if(C_HAS_ACLR === 1)
+			data <= #1 `all0s;
+		else if(C_HAS_ASET === 1)
+			data <= #1 `all1s;
+		else if(C_HAS_AINIT === 1)
+		    data <= #1 AIV;
+		else if(C_HAS_SCLR === 1)
+			data <= #1 `all0s;
+		else if(C_HAS_SSET === 1)
+			data <= #1 `all1s;
+		else if(C_HAS_SINIT === 1)
+			data <= #1 SIV;
+		else
+			data <= #1 AIV;			
+	end
+
+        // intCE removed from sensitivity list.  
+        // Fix CR 128989
+        //Neil Ritchie 8 Dec 2000
+	
+	always@(posedge intCLK or intACLR or intASET or intAINIT)
+	begin
+		datatmp = data;
+		
+//		for(i = 0; i < C_WIDTH; i = i + 1)
+//		begin
+			if(intACLR === 1'b1)
+				datatmp = `all0s;
+			else if(intACLR === 1'b0 && intASET === 1'b1)
+				datatmp = `all1s;
+			else if(intAINIT === 1'b1)
+				datatmp = AIV;
+			else if(intACLR === 1'bx && intASET !== 1'b0)
+				datatmp = `allXs;
+			else if(intACLR != lastintACLR && lastintASET != intASET 
+						&& lastintACLR === 1'b1 && lastintASET === 1'b1
+						&& intACLR === 1'b0 && intASET === 1'b0)
+				datatmp = `allXs;
+			else 
+			begin
+				ASYNC_CTRL = 0;
+				if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1)
+				begin
+					if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+						(C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+					begin
+						datatmp = `allXs;
+						ASYNC_CTRL = 1;
+					end
+					if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+					(C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+					begin
+						datatmp = `allXs;
+						ASYNC_CTRL = 1;
+					end
+					if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp = D;
+					else if(intCE === 1'bx && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp);
+
+					if(intSINIT === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0)
+						datatmp = SIV;
+					else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1))
+						datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp);
+					else if(intSINIT === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0))
+						datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp);
+
+					if(intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0)
+						datatmp = `all0s;
+					else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp = ~(~datatmp | `allXs);
+					else if(intSCLR === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp = ~(~datatmp | `allXs);
+						
+					if(intSSET === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0)
+						datatmp = `all1s;
+					else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp = datatmp | `allXs;
+					else if(intSSET === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp = datatmp | `allXs;
+				end
+				else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx)
+							|| (lastCLK === 1'bx && intCLK === 1'b1)))
+				begin
+					if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+						datatmp = `allXs;
+					else if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+						datatmp = `allXs;
+					
+					if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1)
+						datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp);
+					
+					if(intSINIT !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0))
+						datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp);
+						
+					if(intSCLR !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp = ~(~datatmp | `allXs);
+						
+					if(intSSET !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp = datatmp | `allXs;
+				end
+
+				if(intACLR === 1'b0 && intASET === 1'bx)
+				begin
+//					if(datatmp[i] !== 1'b1)
+//					begin
+//						datatmp[i] = 1'bx;
+//						ASYNC_CTRL = 1;
+//					end
+					ASYNC_CTRL = |(~datatmp) ? 1 : 0;
+                                        datatmp = datatmp | `allXs;
+				end
+				else if(intACLR === 1'bx && intASET === 1'b0)
+				begin
+//					if(datatmp[i] !== 1'b0)
+//					begin
+//						datatmp[i] = 1'bx;
+//						ASYNC_CTRL = 1;
+//					end
+                                        ASYNC_CTRL = |datatmp ? 1 : 0;
+					datatmp = datatmp & `allXs;
+				end
+				else if(intAINIT === 1'bx)
+				begin
+//					if(datatmp[i] !== AIV[i])
+//					begin
+//						datatmp[i] = 1'bx;
+//						ASYNC_CTRL = 1;
+//					end
+					ASYNC_CTRL = |(datatmp ^ AIV) ? 1 : 0;
+					datatmp = ~((~(datatmp ^ AIV) | `allXs) ^ datatmp);
+				end
+			end
+//		end
+		
+		data <= datatmp;
+	end	
+							
+	
+	always@(intACLR or intASET)
+	begin
+		lastintACLR <= intACLR;
+		lastintASET <= intASET;
+		if($time != 0)
+			if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE
+				data <= `allXs;
+	end
+	
+	always@(intCLK)
+		lastCLK <= intCLK;
+	
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+				to_bits[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bits[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef all1s
+`undef all0s
+`undef allXs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V4_0.v

@@ -0,0 +1,319 @@
+/* $Id: C_REG_LD_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $
+--
+-- Filename - C_REG_LD_V4_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_REG_LD_V4_0 module
+*/
+
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define all1s {C_WIDTH{1'b1}}
+`define all0s 'b0
+`define allXs {C_WIDTH{1'bx}}
+
+module C_REG_LD_V4_0 (D, G, GE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_GE 			= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 16; 		
+	
+
+	input [C_WIDTH-1 : 0] D;
+	input G;
+	input GE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] data;
+	reg [C_WIDTH-1 : 0] datatmp;
+	// Internal values to drive signals when input is missing
+	wire intGE;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	 
+	wire [C_WIDTH-1 : 0] #1 Q = data;
+
+	// Sort out default values for missing ports
+	
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intGE = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1) &&
+					(C_HAS_GE == 1) && (C_SYNC_ENABLE == `c_override) ? 
+						(GE | intSCLR | intSSET | intSINIT) : ((C_HAS_GE == 1) ? GE : 1'b1));
+	
+	reg lastintACLR;
+	reg lastintASET;
+	
+	reg [C_WIDTH-1 : 0] AIV;
+	reg [C_WIDTH-1 : 0] SIV;
+	
+	
+	integer i;
+	integer ASYNC_CTRL;
+	
+	initial 
+	begin
+		ASYNC_CTRL = 1;
+		lastintACLR = 1'b0;
+		lastintASET = 1'b0;
+		AIV = to_bits(C_AINIT_VAL);
+		SIV = to_bits(C_SINIT_VAL);
+		if(C_HAS_ACLR === 1)
+			#1 data = `all0s;
+		else if(C_HAS_ASET === 1)
+			#1 data = `all1s;
+		else if(C_HAS_AINIT === 1)
+		    #1 data = AIV;
+//		else if(C_HAS_SCLR === 1)
+//			#1 data = `all0s;
+//		else if(C_HAS_SSET === 1)
+//			#1 data = `all1s;
+//		else if(C_HAS_SINIT === 1)
+//			#1 data = SIV;
+		else
+			#1 data = AIV;			
+	end
+	
+	always@(G or intGE or intACLR or intASET or intAINIT or intSCLR or intSSET or intSINIT or D)
+	begin
+		datatmp = data;
+		
+		for(i = 0; i < C_WIDTH; i = i + 1)
+		begin
+			if(intACLR === 1'b1)
+				datatmp[i] = 1'b0;
+			else if(intACLR === 1'b0 && intASET === 1'b1)
+				datatmp[i] = 1'b1;
+			else if(intAINIT === 1'b1)
+				datatmp[i] = AIV[i];
+			else if(intACLR === 1'bx && intASET !== 1'b0)
+				datatmp[i] = 1'bx;
+			else if(intACLR != lastintACLR && lastintASET != intASET 
+						&& lastintACLR === 1'b1 && lastintASET === 1'b1
+						&& intACLR === 1'b0 && intASET === 1'b0)
+				datatmp[i] = 1'bx;
+			else 
+			begin
+				ASYNC_CTRL = 0;
+				if(G === 1'b1)
+				begin
+					if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+						(C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+					if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+					(C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+					if(intGE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp[i] = D[i];
+					else if(intGE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp[i] = 1'bx;
+
+					if(intSINIT === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0)
+						datatmp[i] = SIV[i];
+					else if(intSINIT === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+					else if(intSINIT === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+
+					if(intSCLR === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0)
+						datatmp[i] = 1'b0;
+					else if(intSCLR === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp[i] = 1'bx;
+					else if(intSCLR === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp[i] = 1'bx;
+						
+					if(intSSET === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0)
+						datatmp[i] = 1'b1;
+					else if(intSSET === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp[i] = 1'bx;
+					else if(intSSET === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp[i] = 1'bx;
+				end
+				else if(G === 1'bx)							
+				begin
+					if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+						datatmp[i] = 1'bx;
+					else if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+						datatmp[i] = 1'bx;
+					
+					if((intGE !== 1'b0 || (C_SYNC_ENABLE == 0 && (intSCLR !== 1'b0 || intSSET !== 1'b0 || intSINIT !== 1'b0))) && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i])
+						datatmp[i] = 1'bx;
+					
+					if(intSINIT !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+						
+					if(intSCLR !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0)
+						datatmp[i] = 1'bx;
+						
+					if(intSSET !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1)
+						datatmp[i] = 1'bx;
+				end
+
+				if(intACLR === 1'b0 && intASET === 1'bx)
+				begin
+					if(datatmp[i] !== 1'b1)
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+				else if(intACLR === 1'bx && intASET === 1'b0)
+				begin
+					if(datatmp[i] !== 1'b0)
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+				else if(intAINIT === 1'bx)
+				begin
+					if(datatmp[i] !== AIV[i])
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+			end
+		end
+		
+		data <= datatmp;
+	end	
+							
+	
+	always@(intACLR or intASET)
+	begin
+		lastintACLR <= intACLR;
+		lastintASET <= intASET;
+		if($time != 0)
+			if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE
+				data <= `allXs;
+	end
+	
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+				to_bits[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bits[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+				else
+				begin
+					$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef all1s
+`undef all0s
+`undef allXs
+

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V5_0.v

@@ -0,0 +1,319 @@
+/* $Id: C_REG_LD_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $
+--
+-- Filename - C_REG_LD_V5_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_REG_LD_V5_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define all1s {C_WIDTH{1'b1}}
+`define all0s 'b0
+`define allXs {C_WIDTH{1'bx}}
+
+module C_REG_LD_V5_0 (D, G, GE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_GE 			= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 16; 		
+	
+
+	input [C_WIDTH-1 : 0] D;
+	input G;
+	input GE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] data;
+	reg [C_WIDTH-1 : 0] datatmp;
+	// Internal values to drive signals when input is missing
+	wire intGE;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	 
+	wire [C_WIDTH-1 : 0] #1 Q = data;
+
+	// Sort out default values for missing ports
+	
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intGE = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1) &&
+					(C_HAS_GE == 1) && (C_SYNC_ENABLE == `c_override) ? 
+						(GE | intSCLR | intSSET | intSINIT) : ((C_HAS_GE == 1) ? GE : 1'b1));
+	
+	reg lastintACLR;
+	reg lastintASET;
+	
+	reg [C_WIDTH-1 : 0] AIV;
+	reg [C_WIDTH-1 : 0] SIV;
+	
+	
+	integer i;
+	integer ASYNC_CTRL;
+	
+	initial 
+	begin
+		ASYNC_CTRL = 1;
+		lastintACLR = 1'b0;
+		lastintASET = 1'b0;
+		AIV = to_bits(C_AINIT_VAL);
+		SIV = to_bits(C_SINIT_VAL);
+		if(C_HAS_ACLR === 1)
+			#1 data = `all0s;
+		else if(C_HAS_ASET === 1)
+			#1 data = `all1s;
+		else if(C_HAS_AINIT === 1)
+		    #1 data = AIV;
+//		else if(C_HAS_SCLR === 1)
+//			#1 data = `all0s;
+//		else if(C_HAS_SSET === 1)
+//			#1 data = `all1s;
+//		else if(C_HAS_SINIT === 1)
+//			#1 data = SIV;
+		else
+			#1 data = AIV;			
+	end
+	
+	always@(G or intGE or intACLR or intASET or intAINIT or intSCLR or intSSET or intSINIT or D)
+	begin
+		datatmp = data;
+		
+		for(i = 0; i < C_WIDTH; i = i + 1)
+		begin
+			if(intACLR === 1'b1)
+				datatmp[i] = 1'b0;
+			else if(intACLR === 1'b0 && intASET === 1'b1)
+				datatmp[i] = 1'b1;
+			else if(intAINIT === 1'b1)
+				datatmp[i] = AIV[i];
+			else if(intACLR === 1'bx && intASET !== 1'b0)
+				datatmp[i] = 1'bx;
+			else if(intACLR != lastintACLR && lastintASET != intASET 
+						&& lastintACLR === 1'b1 && lastintASET === 1'b1
+						&& intACLR === 1'b0 && intASET === 1'b0)
+				datatmp[i] = 1'bx;
+			else 
+			begin
+				ASYNC_CTRL = 0;
+				if(G === 1'b1)
+				begin
+					if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+						(C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+					if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+					(C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+					if(intGE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp[i] = D[i];
+					else if(intGE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+						datatmp[i] = 1'bx;
+
+					if(intSINIT === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0)
+						datatmp[i] = SIV[i];
+					else if(intSINIT === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+					else if(intSINIT === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+
+					if(intSCLR === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0)
+						datatmp[i] = 1'b0;
+					else if(intSCLR === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp[i] = 1'bx;
+					else if(intSCLR === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+						datatmp[i] = 1'bx;
+						
+					if(intSSET === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0)
+						datatmp[i] = 1'b1;
+					else if(intSSET === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp[i] = 1'bx;
+					else if(intSSET === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+						datatmp[i] = 1'bx;
+				end
+				else if(G === 1'bx)							
+				begin
+					if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+						datatmp[i] = 1'bx;
+					else if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+						datatmp[i] = 1'bx;
+					
+					if((intGE !== 1'b0 || (C_SYNC_ENABLE == 0 && (intSCLR !== 1'b0 || intSSET !== 1'b0 || intSINIT !== 1'b0))) && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i])
+						datatmp[i] = 1'bx;
+					
+					if(intSINIT !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+						datatmp[i] = 1'bx;
+						
+					if(intSCLR !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0)
+						datatmp[i] = 1'bx;
+						
+					if(intSSET !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1)
+						datatmp[i] = 1'bx;
+				end
+
+				if(intACLR === 1'b0 && intASET === 1'bx)
+				begin
+					if(datatmp[i] !== 1'b1)
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+				else if(intACLR === 1'bx && intASET === 1'b0)
+				begin
+					if(datatmp[i] !== 1'b0)
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+				else if(intAINIT === 1'bx)
+				begin
+					if(datatmp[i] !== AIV[i])
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end
+				end
+			end
+		end
+		
+		data <= datatmp;
+	end	
+							
+	
+	always@(intACLR or intASET)
+	begin
+		lastintACLR <= intACLR;
+		lastintASET <= intASET;
+		if($time != 0)
+			if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE
+				data <= `allXs;
+	end
+	
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+				to_bits[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bits[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef all1s
+`undef all0s
+`undef allXs

verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V6_0.v

@@ -0,0 +1,369 @@
+// Copyright(C) 2002 by Xilinx, Inc. All rights reserved.
+// This text contains proprietary, confidential
+// information of Xilinx, Inc., is distributed
+// under license from Xilinx, Inc., and may be used,
+// copied and/or disclosed only pursuant to the terms
+// of a valid license agreement with Xilinx, Inc. This copyright
+// notice must be retained as part of this text at all times.
+
+
+/* $Id: C_REG_LD_V6_0.v,v 1.16 2008/09/08 20:06:05 akennedy Exp $
+--
+-- Filename - C_REG_LD_V6_0.v
+-- Author - Xilinx
+-- Creation - 21 Oct 1998
+--
+-- Description - This file contains the Verilog behavior for the baseblocks C_REG_LD_V6_0 module
+*/
+
+`timescale 1ns/10ps
+
+`define c_set 0
+`define c_clear 1
+`define c_override 0
+`define c_no_override 1
+
+`define all1s {C_WIDTH{1'b1}}
+`define all0s 'b0
+`define allXs {C_WIDTH{1'bx}}
+
+module C_REG_LD_V6_0 (D, G, GE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q);
+
+	parameter C_AINIT_VAL 		= "";
+	parameter C_ENABLE_RLOCS	= 1;
+	parameter C_HAS_ACLR 		= 0;
+	parameter C_HAS_AINIT 		= 0;
+	parameter C_HAS_ASET 		= 0;
+	parameter C_HAS_GE 			= 0;
+	parameter C_HAS_SCLR 		= 0;
+	parameter C_HAS_SINIT 		= 0;
+	parameter C_HAS_SSET 		= 0;
+	parameter C_SINIT_VAL 		= "";
+	parameter C_SYNC_ENABLE 	= `c_override;	
+	parameter C_SYNC_PRIORITY 	= `c_clear;	
+	parameter C_WIDTH 			= 16; 		
+	
+
+	input [C_WIDTH-1 : 0] D;
+	input G;
+	input GE;
+	input ACLR;
+	input ASET;
+	input AINIT;
+	input SCLR;
+	input SSET;
+	input SINIT;
+	output [C_WIDTH-1 : 0] Q;
+	 
+	reg [C_WIDTH-1 : 0] data;
+	reg [C_WIDTH-1 : 0] datatmp;
+	// Internal values to drive signals when input is missing
+	wire intGE;
+	wire intACLR;
+	wire intASET;
+	wire intAINIT;
+	wire intSCLR;
+	wire intSSET;
+	wire intSINIT;
+	 
+	wire [C_WIDTH-1 : 0] #1 Q = data;
+
+	// Sort out default values for missing ports
+	
+	assign intACLR = defval(ACLR, C_HAS_ACLR, 0);
+	assign intASET = defval(ASET, C_HAS_ASET, 0);
+	assign intAINIT = defval(AINIT, C_HAS_AINIT, 0);
+	assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
+	assign intSSET = defval(SSET, C_HAS_SSET, 0);
+	assign intSINIT = defval(SINIT, C_HAS_SINIT, 0);
+	assign intGE = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1) &&
+					(C_HAS_GE == 1) && (C_SYNC_ENABLE == `c_override) ? 
+						(GE | intSCLR | intSSET | intSINIT) : ((C_HAS_GE == 1) ? GE : 1'b1));
+	
+	reg lastintACLR;
+	reg lastintASET;
+	
+	reg [C_WIDTH-1 : 0] AIV;
+	reg [C_WIDTH-1 : 0] SIV;
+	
+	
+	integer i;
+	integer ASYNC_CTRL;
+	
+	initial 
+	begin
+		ASYNC_CTRL = 1;
+		lastintACLR = 1'b0;
+		lastintASET = 1'b0;
+		AIV = to_bits(C_AINIT_VAL);
+		SIV = to_bits(C_SINIT_VAL);
+		if(C_HAS_ACLR === 1)
+			#1 data = `all0s;
+		else if(C_HAS_ASET === 1)
+			#1 data = `all1s;
+		else if(C_HAS_AINIT === 1)
+		    #1 data = AIV;
+//		else if(C_HAS_SCLR === 1)
+//			#1 data = `all0s;
+//		else if(C_HAS_SSET === 1)
+//			#1 data = `all1s;
+//		else if(C_HAS_SINIT === 1)
+//			#1 data = SIV;
+		else
+			#1 data = AIV;			
+	end
+	
+	always@(G or intGE or intACLR or intASET or intAINIT or intSCLR or intSSET or intSINIT or D)
+	begin
+		datatmp = data;
+		
+//		for(i = 0; i < C_WIDTH; i = i + 1)
+//		begin
+			if(intACLR === 1'b1)
+//				datatmp[i] = 1'b0;
+				datatmp = `all0s;
+			else if(intACLR === 1'b0 && intASET === 1'b1)
+//				datatmp[i] = 1'b1;
+				datatmp = `all1s;
+			else if(intAINIT === 1'b1)
+//				datatmp[i] = AIV[i];
+				datatmp = AIV;
+			else if(intACLR === 1'bx && intASET !== 1'b0)
+//				datatmp[i] = 1'bx;
+				datatmp = `allXs;
+			else if(intACLR != lastintACLR && lastintASET != intASET 
+						&& lastintACLR === 1'b1 && lastintASET === 1'b1
+						&& intACLR === 1'b0 && intASET === 1'b0)
+//				datatmp[i] = 1'bx;
+				datatmp = `allXs;
+			else 
+			begin
+				ASYNC_CTRL = 0;
+				if(G === 1'b1)
+				begin
+					if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+						(C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+					begin
+//						datatmp[i] = 1'bx;
+						datatmp = `allXs;
+						ASYNC_CTRL = 1;
+					end
+					if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) &&
+					(C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+					begin
+//						datatmp[i] = 1'bx;
+						datatmp = `allXs;
+						ASYNC_CTRL = 1;
+					end
+					if(intGE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+//						datatmp[i] = D[i];
+						datatmp = D;
+//					else if(intGE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+					else if(intGE === 1'bx && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0)
+//						datatmp[i] = 1'bx;
+						datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp);
+
+					if(intSINIT === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0)
+//						datatmp[i] = SIV[i];
+						datatmp = SIV;
+//					else if(intSINIT === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i])
+					else if(intSINIT === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1))
+//						datatmp[i] = 1'bx;
+						datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp);
+//					else if(intSINIT === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+					else if(intSINIT === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0))
+//						datatmp[i] = 1'bx;
+						datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp);
+
+					if(intSCLR === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0)
+//						datatmp[i] = 1'b0;
+						datatmp = `all0s;
+//					else if(intSCLR === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+					else if(intSCLR === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+//						datatmp[i] = 1'bx;
+						datatmp = ~(~datatmp | `allXs);
+//					else if(intSCLR === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+					else if(intSCLR === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+//						datatmp[i] = 1'bx;
+						datatmp = ~(~datatmp | `allXs);
+						
+					if(intSSET === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0)
+//						datatmp[i] = 1'b1;
+						datatmp = `all1s;
+//					else if(intSSET === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+					else if(intSSET === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+//						datatmp[i] = 1'bx;
+						datatmp = datatmp | `allXs;
+//					else if(intSSET === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+					else if(intSSET === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+//						datatmp[i] = 1'bx;
+						datatmp = datatmp | `allXs;
+				end
+				else if(G === 1'bx)							
+				begin
+					if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0))
+//						datatmp[i] = 1'bx;
+						datatmp = `allXs;
+					else if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx))
+//						datatmp[i] = 1'bx;
+						datatmp = `allXs;
+					
+//					if((intGE !== 1'b0 || (C_SYNC_ENABLE == 0 && (intSCLR !== 1'b0 || intSSET !== 1'b0 || intSINIT !== 1'b0))) && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i])
+					if((intGE !== 1'b0 || (C_SYNC_ENABLE == 0 && (intSCLR !== 1'b0 || intSSET !== 1'b0 || intSINIT !== 1'b0))) && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1)
+//						datatmp[i] = 1'bx;
+						datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp);
+						
+//					if(intSINIT !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i])
+					if(intSINIT !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0))
+//						datatmp[i] = 1'bx;
+						datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp);
+						
+//					if(intSCLR !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0)
+					if(intSCLR !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0))
+//						datatmp[i] = 1'bx;
+						datatmp = ~(~datatmp | `allXs);
+						
+//					if(intSSET !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1)
+					if(intSSET !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0))
+//						datatmp[i] = 1'bx;
+						datatmp = datatmp | `allXs;
+				end
+
+				if(intACLR === 1'b0 && intASET === 1'bx)
+				begin
+/*					if(datatmp[i] !== 1'b1)
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end*/
+					ASYNC_CTRL = |(~datatmp) ? 1 : 0;
+                                        datatmp = datatmp | `allXs;
+				end
+				else if(intACLR === 1'bx && intASET === 1'b0)
+				begin
+/*					if(datatmp[i] !== 1'b0)
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end*/
+                                        ASYNC_CTRL = |datatmp ? 1 : 0;
+					datatmp = datatmp & `allXs;
+				end
+				else if(intAINIT === 1'bx)
+				begin
+/*					if(datatmp[i] !== AIV[i])
+					begin
+						datatmp[i] = 1'bx;
+						ASYNC_CTRL = 1;
+					end*/
+					ASYNC_CTRL = |(datatmp ^ AIV) ? 1 : 0;
+					datatmp = ~((~(datatmp ^ AIV) | `allXs) ^ datatmp);
+				end
+			end
+//		end
+		
+		data <= datatmp;
+	end	
+							
+	
+	always@(intACLR or intASET)
+	begin
+		lastintACLR <= intACLR;
+		lastintASET <= intASET;
+		if($time != 0)
+			if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE
+				data <= `allXs;
+	end
+	
+	
+	function defval;
+	input i;
+	input hassig;
+	input val;
+		begin
+			if(hassig == 1)
+				defval = i;
+			else
+				defval = val;
+		end
+	endfunction
+	
+	function [C_WIDTH - 1 : 0] to_bits;
+	input [C_WIDTH*8 : 1] instring;
+	integer i;
+	integer non_null_string;
+	begin
+		non_null_string = 0;
+		for(i = C_WIDTH; i > 0; i = i - 1)
+		begin // Is the string empty?
+			if(instring[(i*8)] == 0 && 
+				instring[(i*8)-1] == 0 && 
+				instring[(i*8)-2] == 0 && 
+				instring[(i*8)-3] == 0 && 
+				instring[(i*8)-4] == 0 && 
+				instring[(i*8)-5] == 0 && 
+				instring[(i*8)-6] == 0 && 
+				instring[(i*8)-7] == 0 &&
+				non_null_string == 0)
+					non_null_string = 0; // Use the return value to flag a non-empty string
+			else
+					non_null_string = 1; // Non-null character!
+		end
+		if(non_null_string == 0) // String IS empty! Just return the value to be all '0's
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+				to_bits[i-1] = 0;
+		end
+		else
+		begin
+			for(i = C_WIDTH; i > 0; i = i - 1)
+			begin // Is this character a '0'? (ASCII = 48 = 00110000)
+				if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)
+						to_bits[i-1] = 0;
+				  // Or is it a '1'? 
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 1 && 
+					instring[(i*8)-3] == 1 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 1)		
+						to_bits[i-1] = 1;
+				  // Or is it a ' '? (a null char - in which case insert a '0')
+				else if(instring[(i*8)] == 0 && 
+					instring[(i*8)-1] == 0 && 
+					instring[(i*8)-2] == 0 && 
+					instring[(i*8)-3] == 0 && 
+					instring[(i*8)-4] == 0 && 
+					instring[(i*8)-5] == 0 && 
+					instring[(i*8)-6] == 0 && 
+					instring[(i*8)-7] == 0)		
+						to_bits[i-1] = 0;
+				else
+				begin
+					$display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring);
+					$finish;
+				end
+			end
+		end 
+	end
+	endfunction
+	
+endmodule
+
+`undef c_set
+`undef c_clear
+`undef c_override
+`undef c_no_override
+
+`undef all1s
+`undef all0s
+`undef allXs