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bug fix: increase phase calculation delay by 1 CLK

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mmehari 2022-01-04 22:22:00 +01:00
parent e257d3373b
commit 85b1adbec7
1 changed files with 1 additions and 1 deletions
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2
verilog/phase.v
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@ -78,7 +78,7 @@ divider div_inst (
.output_strobe(div_out_stb)
);
delayT #(.DATA_WIDTH(3), .DELAY(36)) quadrant_inst (
delayT #(.DATA_WIDTH(3), .DELAY(37)) quadrant_inst (
.clock(clock),
.reset(reset),