add sim_out dir

This commit is contained in:
Jinghao Shi 2017-04-03 15:25:48 -04:00
parent 23e1c270e0
commit 506472dec3

4
verilog/sim_out/.gitignore vendored Normal file
View File

@ -0,0 +1,4 @@
# Ignore everything in this directory
*
# # Except this file
!.gitignore