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fix long preamble sample beginning index

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This commit is contained in:
Jinghao Shi 2017-04-07 16:49:41 -04:00
parent 652c8c1bb7
commit 20279b42a4
1 changed files with 2 additions and 2 deletions
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4
verilog/sync_long.v
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@ -265,8 +265,8 @@ always @(posedge clock) begin
num_sample <= 0;
mult_strobe <= 0;
sum_stb <= 0;
in_raddr <= addr1 - 15;
num_input_consumed <= addr1 - 15;
in_raddr <= addr1 - 16;
num_input_consumed <= addr1 - 16;
in_offset <= 0;
num_ofdm_symbol <= 0;
phase_correction <= 0;