From 20279b42a43bb5bb0d7b01ecc061ed6bd6b68c69 Mon Sep 17 00:00:00 2001 From: Jinghao Shi Date: Fri, 7 Apr 2017 16:49:41 -0400 Subject: [PATCH] fix long preamble sample beginning index --- verilog/sync_long.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/sync_long.v b/verilog/sync_long.v index 93c5f7f..82bf3ea 100644 --- a/verilog/sync_long.v +++ b/verilog/sync_long.v @@ -265,8 +265,8 @@ always @(posedge clock) begin num_sample <= 0; mult_strobe <= 0; sum_stb <= 0; - in_raddr <= addr1 - 15; - num_input_consumed <= addr1 - 15; + in_raddr <= addr1 - 16; + num_input_consumed <= addr1 - 16; in_offset <= 0; num_ofdm_symbol <= 0; phase_correction <= 0;