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61 lines
3.3 KiB
Plaintext
61 lines
3.3 KiB
Plaintext
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-- This file is owned and controlled by Xilinx and must be used --
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-- solely for design, simulation, implementation and creation of --
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-- design files limited to Xilinx devices or technologies. Use --
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-- with non-Xilinx devices or technologies is expressly prohibited --
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-- and immediately terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
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-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
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-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
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-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
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-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
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-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
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-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
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-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
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-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support --
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-- appliances, devices, or systems. Use in such applications are --
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-- expressly prohibited. --
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-- --
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-- (c) Copyright 1995-2009 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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-- The following code must appear in the VHDL architecture header:
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------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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component atan_lut
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port (
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clka: IN std_logic;
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addra: IN std_logic_VECTOR(7 downto 0);
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douta: OUT std_logic_VECTOR(8 downto 0));
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end component;
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-- Synplicity black box declaration
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attribute syn_black_box : boolean;
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attribute syn_black_box of atan_lut: component is true;
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-- COMP_TAG_END ------ End COMPONENT Declaration ------------
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-- The following code must appear in the VHDL architecture
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-- body. Substitute your own instance name and net names.
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------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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your_instance_name : atan_lut
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port map (
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clka => clka,
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addra => addra,
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douta => douta);
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-- INST_TAG_END ------ End INSTANTIATION Template ------------
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-- You must compile the wrapper file atan_lut.vhd when simulating
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-- the core, atan_lut. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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