mirror of
https://github.com/jhshi/openofdm.git
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86 lines
2.2 KiB
Plaintext
86 lines
2.2 KiB
Plaintext
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##############################################################
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#
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# Xilinx Core Generator version 12.2
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# Date: Sat Oct 29 21:54:23 2016
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc3sd3400a
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SET devicefamily = spartan3adsp
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SET flowvendor = Foundation_ISE
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = fg676
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SET removerpms = false
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SET simulationfiles = Structural
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SET speedgrade = -5
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SET verilogsim = true
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT Viterbi_Decoder family Xilinx,_Inc. 7.0
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# END Select
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# BEGIN Parameters
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CSET architecture=Parallel
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CSET ber_symbol_count=false
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CSET ber_thresh=600
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CSET best_state=true
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CSET best_state_width=3
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CSET block_valid=false
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CSET ce=true
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CSET channels=1
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CSET coding=Soft_Coding
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CSET component_name=viterbi_v7_0
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CSET constraint_length=7
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CSET convolution0_code0=133
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CSET convolution0_code1=171
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CSET convolution0_code2=0
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CSET convolution0_code3=0
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CSET convolution0_code4=0
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CSET convolution0_code5=0
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CSET convolution0_code6=0
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CSET convolution1_code0=1111001
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CSET convolution1_code1=1011011
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CSET convolution1_code2=0
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CSET convolution1_code3=0
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CSET convolution1_code4=0
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CSET convolution1_code5=0
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CSET convolution1_code6=0
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CSET convolution_code_0_radix=Octal
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CSET convolution_code_1_radix=Binary
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CSET data_format=Signed_Magnitude
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CSET direct_traceback=None
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CSET dynamic_thresholds=false
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CSET maximum_direct=24
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CSET norm=false
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CSET norm_thresh=250
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CSET number_of_ber_symbols=300
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CSET output_rate0=2
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CSET output_rate1=2
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CSET puncturing=External
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CSET rdy=true
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CSET reduced_latency=true
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CSET soft_width=3
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CSET synchronization=false
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CSET synchronous_clear=true
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CSET traceback_length=24
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CSET trellis_initialization=None
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CSET viterbi_type=Standard
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# END Parameters
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GENERATE
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# CRC: a323316c
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