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85d7e29d18
* modules/coreboot: add option to use coreboot 4.11 Port patches from coreboot 4.8.1 to 4.11: * 0000-measure-boot -> 0001 * 0010-cross-compiler-support All other patches for coreboot 4.8.1 have either already been integrated, or are for platforms which do not need to be migrated to coreboot 4.11 (they will move to 4.12 or newer). Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> * patches/coreboot-4.11: Add Broadwell-DE platform patch Add a patch for FSP Broadwell-DE to make use of Heads' measured boot. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> * patches/coreboot-4.11: Add patch to read serial # from CBFS Will be used by multiple Librem boards. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> * patches/coreboot-4.11: add board support for Librem Server L1UM Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> * Librem Server L1UM: add new board Add board config, coreboot config, kernel config files. Add conditional purism-blobs dependency to coreboot-4.11 module. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> * flash.sh: add special handling for librem_l1um board Add support for persisting PCIe config via PCHSTRP9 in flash descriptor. This is needed to support multiple variants of the L1UM server which use the same firmware but differ in PCIe lane configuration via the PCH straps configuration in the flash descriptor. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> * patches/coreboot-4.11: Add 'Use PRIxPTR to print uintptr_t' patch Cherry-picked from upstream coreboot (post-4.11), fixes compilation issue. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> * CircleCI: add target to build board librem_l1um Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
48 lines
1.5 KiB
Diff
48 lines
1.5 KiB
Diff
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
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index 8438b1035c..ff7a29271f 100644
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--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
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+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
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@@ -28,6 +28,8 @@
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#include <version.h>
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <pc80/mc146818rtc.h>
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+#include <security/tpm/tss.h>
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+#include <security/tpm/tspi.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/memory.h>
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@@ -156,6 +158,20 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
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early_iio_hide();
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timestamp_add_now(TS_BEFORE_INITRAM);
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post_code(0x48);
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+
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+ if (CONFIG(MEASURED_BOOT) && CONFIG(LPC_TPM)) {
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+ // we don't know if we are coming out of a resume
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+ // at this point, but want to setup the tpm ASAP
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+ tpm_setup(0);
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+ tlcl_lib_init();
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+ const void *const bootblock = (const void *) 0xFFFFF800;
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+ const unsigned int bootblock_size = 0x800;
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+ tlcl_measure(2, bootblock, bootblock_size);
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+
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+ extern char _romstage, _eromstage;
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+ tlcl_measure(2, &_romstage, &_eromstage - &_romstage);
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+ }
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+
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/*
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* Call early init to initialize memory and chipset. This function returns
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* to the romstage_main_continue function with a pointer to the HOB
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@@ -214,3 +230,9 @@ uint64_t get_initial_timestamp(void)
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{
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return 0;
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}
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+
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+void platform_segment_loaded(uintptr_t start, size_t size, int flags)
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+{
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+ if (CONFIG(MEASURED_BOOT) && !(flags & SEG_NO_MEASURE))
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+ tlcl_measure(2, (const void *) start, size);
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+}
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--
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2.20.1
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