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Add new board: Purism Librem Server L1UM (#858)

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* modules/coreboot: add option to use coreboot 4.11

Port patches from coreboot 4.8.1 to 4.11:
* 0000-measure-boot -> 0001
* 0010-cross-compiler-support

All other patches for coreboot 4.8.1 have either already been
integrated, or are for platforms which do not need to be migrated
to coreboot 4.11 (they will move to 4.12 or newer).

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

* patches/coreboot-4.11: Add Broadwell-DE platform patch

Add a patch for FSP Broadwell-DE to make use of Heads' measured boot.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

* patches/coreboot-4.11: Add patch to read serial # from CBFS

Will be used by multiple Librem boards.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

* patches/coreboot-4.11: add board support for Librem Server L1UM

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

* Librem Server L1UM: add new board

Add board config, coreboot config, kernel config files.
Add conditional purism-blobs dependency to coreboot-4.11 module.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

* flash.sh: add special handling for librem_l1um board

Add support for persisting PCIe config via PCHSTRP9 in flash descriptor.
This is needed to support multiple variants of the L1UM server which
use the same firmware but differ in PCIe lane configuration via the
PCH straps configuration in the flash descriptor.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

* patches/coreboot-4.11: Add 'Use PRIxPTR to print uintptr_t' patch

Cherry-picked from upstream coreboot (post-4.11), fixes compilation issue.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>

* CircleCI: add target to build board librem_l1um

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
This commit is contained in:
MrChromebox 2020-10-18 13:48:25 -05:00 committed by GitHub
parent 636e40456e
commit 85d7e29d18
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
12 changed files with 3114 additions and 0 deletions
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18
.circleci/config.yml
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@ -59,6 +59,24 @@ jobs:
# - store-artifacts:
# path: build/qemu-linuxboot/hashes.txt
- run:
name: librem_l1um
command: |
rm -rf build/librem_l1um/* build/log/* && make CPUS=4 \
V=1 \
BOARD=librem_l1um || (find ./build/ -name "*.log" -type f -mmin -1|while read log; do echo ""; echo '==>' "$log" '<=='; echo ""; cat $log;done; exit 1) \
no_output_timeout: 3h
- run:
name: Ouput librem_l1um hashes
command: |
cat build/librem_l1um/hashes.txt \
- run:
name: Archiving build logs for librem_l1um
command: |
tar zcvf build/librem_l1um/logs.tar.gz build/log/*
- store-artifacts:
path: build/librem_l1um
- run:
name: librem_mini
command: |

43
boards/librem_l1um/librem_l1um.config Normal file
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@ -0,0 +1,43 @@
# Configuration for a librem_l1um
CONFIG_LINUX_CONFIG=config/linux-librem_l1um.config
CONFIG_COREBOOT_CONFIG=config/coreboot-librem_l1um.config
export CONFIG_COREBOOT=y
export CONFIG_COREBOOT_VERSION=4.11
export CONFIG_LINUX_VERSION=4.19.139
export CONFIG_PURISM_BLOBS=y
CONFIG_CRYPTSETUP=y
CONFIG_FLASHROM=y
CONFIG_FLASHTOOLS=y
CONFIG_GPG2=y
CONFIG_KEXEC=y
CONFIG_UTIL_LINUX=y
CONFIG_LVM2=y
CONFIG_MBEDTLS=y
CONFIG_PCIUTILS=y
CONFIG_POPT=y
CONFIG_QRENCODE=y
CONFIG_TPMTOTP=y
CONFIG_CAIRO=y
CONFIG_FBWHIPTAIL=y
CONFIG_HOTPKEY=y
CONFIG_LINUX_USB=y
export CONFIG_TPM=y
export CONFIG_TPM_NO_LUKS_DISK_UNLOCK=y
export CONFIG_BOOTSCRIPT=/bin/gui-init
export CONFIG_BOOT_REQ_HASH=n
export CONFIG_BOOT_REQ_ROLLBACK=n
export CONFIG_BOOT_KERNEL_ADD="intel_iommu=on"
export CONFIG_BOOT_KERNEL_REMOVE="plymouth.ignore-serial-consoles"
export CONFIG_BOOT_DEV="/dev/nvme0n1p1"
export CONFIG_BOOT_GUI_MENU_NAME="Purism Librem Server L1UM Heads Boot Menu"
export CONFIG_WARNING_BG_COLOR="--background-gradient 0 0 0 150 125 0"
export CONFIG_ERROR_BG_COLOR="--background-gradient 0 0 0 150 0 0"
export CONFIG_AUTO_BOOT_TIMEOUT=5
export CONFIG_FLASHROM_OPTIONS="-p internal"
export CONFIG_USB_KEYBOARD=y

28
config/coreboot-librem_l1um.config Normal file
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@ -0,0 +1,28 @@
CONFIG_LOCALVERSION="heads"
CONFIG_ANY_TOOLCHAIN=y
CONFIG_USE_BLOBS=y
CONFIG_MEASURED_BOOT=y
CONFIG_VENDOR_PURISM=y
CONFIG_CBFS_SIZE=0xC00000
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Purism"
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Librem Server L1UM"
CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_l1um/flashdescriptor.bin"
CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_l1um/me.bin"
CONFIG_HAVE_IFD_BIN=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_BOARD_PURISM_LIBREM_L1UM=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_FSP_EHCI1_ENABLE=y
CONFIG_FSP_EHCI2_ENABLE=y
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_l1um/cpu_microcode_blob.bin"
CONFIG_HAVE_ME_BIN=y
CONFIG_NO_GFX_INIT=y
CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y
CONFIG_SMBIOS_ENCLOSURE_TYPE=0x17
CONFIG_USER_TPM1=y
CONFIG_NO_POST=y
CONFIG_PAYLOAD_LINUX=y
CONFIG_PAYLOAD_FILE="../../build/librem_l1um/bzImage"
CONFIG_LINUX_INITRD="../../build/librem_l1um/initrd.cpio.xz"
CONFIG_LINUX_COMMAND_LINE="quiet loglevel=3"

309
config/linux-librem_l1um.config Normal file
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@ -0,0 +1,309 @@
CONFIG_LOCALVERSION="-heads"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_KERNEL_XZ=y
# CONFIG_SWAP is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_LOG_BUF_SHIFT=18
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../../../blobs/dev.cpio"
# CONFIG_RD_GZIP is not set
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_SGETMASK_SYSCALL is not set
# CONFIG_SYSFS_SYSCALL is not set
# CONFIG_FHANDLE is not set
# CONFIG_BASE_FULL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
# CONFIG_ADVISE_SYSCALLS is not set
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SMP=y
# CONFIG_RETPOLINE is not set
# CONFIG_X86_EXTENDED_PLATFORM is not set
CONFIG_PROCESSOR_SELECT=y
# CONFIG_CPU_SUP_CENTAUR is not set
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
# CONFIG_X86_MCE_AMD is not set
# CONFIG_PERF_EVENTS_INTEL_RAPL is not set
# CONFIG_MICROCODE is not set
CONFIG_X86_PMEM_LEGACY=y
# CONFIG_X86_SMAP is not set
# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set
# CONFIG_SECCOMP is not set
CONFIG_KEXEC=y
CONFIG_KEXEC_FILE=y
# CONFIG_RELOCATABLE is not set
CONFIG_PHYSICAL_ALIGN=0x1000000
# CONFIG_MODIFY_LDT_SYSCALL is not set
# CONFIG_SUSPEND is not set
CONFIG_PCI_MSI=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
# CONFIG_FIRMWARE_MEMMAP is not set
# CONFIG_DMIID is not set
# CONFIG_VIRTUALIZATION is not set
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_COREDUMP is not set
# CONFIG_SPARSEMEM_VMEMMAP is not set
# CONFIG_COMPACTION is not set
# CONFIG_BOUNCE is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_BLK_DEV_NVME=y
CONFIG_EEPROM_93CX6=m
CONFIG_INTEL_MEI_ME=m
CONFIG_INTEL_MEI_TXE=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_ISCSI_TCP=y
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
# CONFIG_ATA_SFF is not set
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_BROCADE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HP is not set
# CONFIG_NET_VENDOR_I825XX is not set
CONFIG_E1000=m
CONFIG_E1000E=m
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RDC is not set
# CONFIG_NET_VENDOR_REALTEK is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO_SERPORT is not set
# CONFIG_UNIX98_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_LPSS is not set
# CONFIG_SERIAL_8250_MID is not set
CONFIG_TTY_PRINTK=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_TIMERIOMEM=m
CONFIG_HW_RANDOM_INTEL=m
CONFIG_HW_RANDOM_AMD=m
CONFIG_HW_RANDOM_VIA=m
CONFIG_TCG_TPM=y
CONFIG_TCG_TIS=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_MUX=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_REG=m
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_SLAVE=y
CONFIG_PTP_1588_CLOCK=y
# CONFIG_HWMON is not set
# CONFIG_X86_PKG_TEMP_THERMAL is not set
CONFIG_MFD_SYSCON=y
CONFIG_DRM=y
CONFIG_DRM_AST=y
CONFIG_FB_VESA=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=m
CONFIG_USB_XHCI_PLATFORM=m
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_EHCI_HCD_PLATFORM=m
CONFIG_USB_STORAGE=m
CONFIG_RTC_CLASS=y
# CONFIG_X86_PLATFORM_DEVICES is not set
CONFIG_INTEL_IOMMU=y
CONFIG_INTEL_IOMMU_SVM=y
CONFIG_GENERIC_PHY=y
# CONFIG_BLK_DEV_PMEM is not set
# CONFIG_ND_BLK is not set
# CONFIG_BTT is not set
CONFIG_EXT4_FS=y
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
# CONFIG_PROC_SYSCTL is not set
# CONFIG_PROC_PAGE_MONITOR is not set
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_CRYPTO_RSA=m
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_MCRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_CHACHA20POLY1305=m
CONFIG_CRYPTO_CTS=m
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=m
CONFIG_CRYPTO_CMAC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_CRC32C_INTEL=y
CONFIG_CRYPTO_CRC32=m
CONFIG_CRYPTO_CRC32_PCLMUL=m
CONFIG_CRYPTO_CRCT10DIF_PCLMUL=m
CONFIG_CRYPTO_POLY1305_X86_64=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_RMD128=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_RMD256=m
CONFIG_CRYPTO_RMD320=m
CONFIG_CRYPTO_SHA1_SSSE3=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=m
CONFIG_CRYPTO_AES_NI_INTEL=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_BLOWFISH_X86_64=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=m
CONFIG_CRYPTO_CAST5_AVX_X86_64=m
CONFIG_CRYPTO_CAST6_AVX_X86_64=m
CONFIG_CRYPTO_DES3_EDE_X86_64=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_CHACHA20_X86_64=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT_SSE2_X86_64=m
CONFIG_CRYPTO_SERPENT_AVX2_X86_64=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=m
CONFIG_CRYPTO_LZ4=m
CONFIG_CRYPTO_LZ4HC=m
CONFIG_CRYPTO_ANSI_CPRNG=m
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_AEAD=y
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=m
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=m
CONFIG_CRC7=m
CONFIG_LIBCRC32C=m
CONFIG_CRC8=m
CONFIG_XZ_DEC_TEST=m
CONFIG_CORDIC=m
CONFIG_IRQ_POLL=y
CONFIG_PRINTK_TIME=y
CONFIG_BOOT_PRINTK_DELAY=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_INFO_DWARF4=y
CONFIG_GDB_SCRIPTS=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_HARDLOCKUP_DETECTOR=y
CONFIG_WQ_WATCHDOG=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_RCU_TRACE is not set
# CONFIG_FTRACE is not set
# CONFIG_STRICT_DEVMEM is not set
# CONFIG_X86_VERBOSE_BOOTUP is not set
# CONFIG_DOUBLEFAULT is not set
CONFIG_IO_DELAY_0XED=y
CONFIG_OPTIMIZE_INLINING=y
# CONFIG_X86_DEBUG_FPU is not set

8
initrd/bin/flash.sh
View File

@ -43,6 +43,14 @@ flash_rom() {
cbfs -o /tmp/${CONFIG_BOARD}.rom -d serial_number 2>/dev/null || true
cbfs -o /tmp/${CONFIG_BOARD}.rom -a serial_number -f /tmp/serial
fi
# persist PCHSTRP9 from flash descriptor
if [ "$CONFIG_BOARD" = "librem_l1um" ]; then
echo "Persisting PCHSTRP9"
flashrom $CONFIG_FLASHROM_OPTIONS -r /tmp/ifd.bin --ifd -i fd >/dev/null 2>&1 \
|| die "Failed to read flash descriptor"
dd if=/tmp/ifd.bin bs=1 count=4 skip=292 of=/tmp/pchstrp9.bin >/dev/null 2>&1
dd if=/tmp/pchstrp9.bin bs=1 count=4 seek=292 of=/tmp/${CONFIG_BOARD}.rom conv=notrunc >/dev/null 2>&1
fi
flashrom $CONFIG_FLASHROM_OPTIONS -w /tmp/${CONFIG_BOARD}.rom \
|| die "$ROM: Flash failed"

5
modules/coreboot
View File

@ -4,6 +4,11 @@ ifeq "$(CONFIG_COREBOOT_VERSION)" "4.8.1"
coreboot_version := 4.8.1
coreboot_hash := f0ddf4db0628c1fe1e8348c40084d9cbeb5771400c963fd419cda3995b69ad23
coreboot-blobs_hash := 18aa509ae3af005a05d7b1e0b0246dc640249c14fc828f5144b6fd20bb10e295
else ifeq "$(CONFIG_COREBOOT_VERSION)" "4.11"
coreboot_version := 4.11
coreboot_hash := 97fd859b4c39a25534fe33c30eb86e54a233952e08a024c55858d11598a8ad87
coreboot-blobs_hash := aa7855c5bd385b3360dadc043ea6bc93f564e6e4840d9b3ee5b9e696bbd055db
coreboot_depends := $(if $(CONFIG_PURISM_BLOBS), purism-blobs)
else ifeq "$(CONFIG_COREBOOT_VERSION)" "4.12"
coreboot_version := 4.12
coreboot_hash := edcad000ee9b73183c396ea76155629b3d27c693e0f1ae83e3424c4d936e2be2

47
patches/coreboot-4.11/0000-cpu-x86-smm-Use-PRIxPTR-to-print-uintptr_t.patch Normal file
View File

@ -0,0 +1,47 @@
From 06f2fcc0ffc1a903f304d8a3382f3a57163989a1 Mon Sep 17 00:00:00 2001
From: Jacob Garber <jgarber1@ualberta.ca>
Date: Mon, 4 Nov 2019 09:35:15 -0700
Subject: [PATCH] cpu/x86/smm: Use PRIxPTR to print uintptr_t
Since 'base' is a uintptr_t, it needs the PRIxPTR format specifier. This
fixes a compilation error when targeting x86_64 or using Clang 9.0.0.
Change-Id: Ib806e2b3cbb255ef208b361744ac4547b8ba262f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
---
src/cpu/x86/smm/tseg_region.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c
index a8b8bb7b9a..5b5c5729d5 100644
--- a/src/cpu/x86/smm/tseg_region.c
+++ b/src/cpu/x86/smm/tseg_region.c
@@ -17,6 +17,7 @@
#include <cpu/x86/smm.h>
#include <stage_cache.h>
#include <types.h>
+#include <inttypes.h>
/*
* Subregions within SMM
@@ -88,11 +89,11 @@ void smm_list_regions(void)
return;
printk(BIOS_DEBUG, "SMM Memory Map\n");
- printk(BIOS_DEBUG, "SMRAM : 0x%zx 0x%zx\n", base, size);
+ printk(BIOS_DEBUG, "SMRAM : 0x%" PRIxPTR " 0x%zx\n", base, size);
for (i = 0; i < SMM_SUBREGION_NUM; i++) {
if (smm_subregion(i, &base, &size))
continue;
- printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
+ printk(BIOS_DEBUG, " Subregion %d: 0x%" PRIxPTR " 0x%zx\n", i, base, size);
}
}
--
2.21.1

1890
patches/coreboot-4.11/0001-Add-Heads-TPM-measured-boot-support.patch Normal file
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File diff suppressed because it is too large Load Diff

47
patches/coreboot-4.11/0002-soc-intel-broadwell_de-Add-measured-boot-support.patch Normal file
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@ -0,0 +1,47 @@
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 8438b1035c..ff7a29271f 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -28,6 +28,8 @@
#include <version.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <pc80/mc146818rtc.h>
+#include <security/tpm/tss.h>
+#include <security/tpm/tspi.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/memory.h>
@@ -156,6 +158,20 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
early_iio_hide();
timestamp_add_now(TS_BEFORE_INITRAM);
post_code(0x48);
+
+ if (CONFIG(MEASURED_BOOT) && CONFIG(LPC_TPM)) {
+ // we don't know if we are coming out of a resume
+ // at this point, but want to setup the tpm ASAP
+ tpm_setup(0);
+ tlcl_lib_init();
+ const void *const bootblock = (const void *) 0xFFFFF800;
+ const unsigned int bootblock_size = 0x800;
+ tlcl_measure(2, bootblock, bootblock_size);
+
+ extern char _romstage, _eromstage;
+ tlcl_measure(2, &_romstage, &_eromstage - &_romstage);
+ }
+
/*
* Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB
@@ -214,3 +230,9 @@ uint64_t get_initial_timestamp(void)
{
return 0;
}
+
+void platform_segment_loaded(uintptr_t start, size_t size, int flags)
+{
+ if (CONFIG(MEASURED_BOOT) && !(flags & SEG_NO_MEASURE))
+ tlcl_measure(2, (const void *) start, size);
+}
--
2.20.1

78
patches/coreboot-4.11/0003-drivers-generic-cbfs-serial-Add-driver-to-read-seria.patch Normal file
View File

@ -0,0 +1,78 @@
diff --git a/src/drivers/generic/cbfs-serial/Kconfig b/src/drivers/generic/cbfs-serial/Kconfig
new file mode 100644
index 0000000000..209c242dba
--- /dev/null
+++ b/src/drivers/generic/cbfs-serial/Kconfig
@@ -0,0 +1,6 @@
+config DRIVERS_GENERIC_CBFS_SERIAL
+ bool "Serial number in CBFS"
+ default n
+ help
+ Enable this option to read the board serial number from a
+ text file located in CBFS.
diff --git a/src/drivers/generic/cbfs-serial/Makefile.inc b/src/drivers/generic/cbfs-serial/Makefile.inc
new file mode 100644
index 0000000000..163d439ba9
--- /dev/null
+++ b/src/drivers/generic/cbfs-serial/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_GENERIC_CBFS_SERIAL) += cbfs-serial.c
diff --git a/src/drivers/generic/cbfs-serial/cbfs-serial.c b/src/drivers/generic/cbfs-serial/cbfs-serial.c
new file mode 100644
index 0000000000..ee3e36620c
--- /dev/null
+++ b/src/drivers/generic/cbfs-serial/cbfs-serial.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <device/device.h>
+#include <smbios.h>
+#include <string.h>
+
+
+#define MAX_SERIAL_LENGTH 0x100
+
+const char *smbios_mainboard_serial_number(void)
+{
+ static char serial_number[MAX_SERIAL_LENGTH + 1] = {0};
+ struct cbfsf file;
+
+ if (serial_number[0] != 0)
+ return serial_number;
+
+ if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) {
+ struct region_device cbfs_region;
+ size_t serial_len;
+
+ cbfs_file_data(&cbfs_region, &file);
+
+ serial_len = region_device_sz(&cbfs_region);
+ if (serial_len <= MAX_SERIAL_LENGTH) {
+ if (rdev_readat(&cbfs_region, serial_number, 0,
+ serial_len) == serial_len) {
+ serial_number[serial_len] = 0;
+ return serial_number;
+ }
+ }
+ }
+
+ strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER,
+ MAX_SERIAL_LENGTH);
+
+ return serial_number;
+}
--
2.20.1

609
patches/coreboot-4.11/0004-mb-purism-librem_l1um-Add-new-board.patch Normal file
View File

@ -0,0 +1,609 @@
diff --git a/src/mainboard/purism/librem_l1um/Kconfig b/src/mainboard/purism/librem_l1um/Kconfig
new file mode 100644
index 0000000000..ba504faa75
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/Kconfig
@@ -0,0 +1,41 @@
+if BOARD_PURISM_LIBREM_L1UM
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_16384
+ select DRIVERS_UART_8250IO
+ select ENABLE_FSP_FAST_BOOT
+ select GENERATE_SMBIOS_TABLES
+ select HAVE_ACPI_TABLES
+ select IPMI_KCS
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select MRC_CACHE_FMAP
+ select SERIRQ_CONTINUOUS_MODE
+ select SOC_INTEL_FSP_BROADWELL_DE
+ select SUPERIO_ASPEED_AST2400
+
+config MAINBOARD_DIR
+ string
+ default "purism/librem_l1um"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "LIBREM_L1UM"
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config CBFS_SIZE
+ hex
+ default 0x00C00000
+
+config VIRTUAL_ROM_SIZE
+ hex
+ default 0x1000000
+
+config INTEGRATED_UART
+ def_bool n
+
+endif # BOARD_PURISM_LIBREM_L1UM
diff --git a/src/mainboard/purism/librem_l1um/Kconfig.name b/src/mainboard/purism/librem_l1um/Kconfig.name
new file mode 100644
index 0000000000..3e3441931c
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_PURISM_LIBREM_L1UM
+ bool "Purism LIBREM_L1UM"
diff --git a/src/mainboard/purism/librem_l1um/Makefile.inc b/src/mainboard/purism/librem_l1um/Makefile.inc
new file mode 100644
index 0000000000..991f44ed3c
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/Makefile.inc
@@ -0,0 +1,14 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-y += irqroute.c
diff --git a/src/mainboard/purism/librem_l1um/acpi/mainboard.asl b/src/mainboard/purism/librem_l1um/acpi/mainboard.asl
new file mode 100644
index 0000000000..78858cc652
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/acpi/mainboard.asl
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+}
diff --git a/src/mainboard/purism/librem_l1um/acpi/platform.asl b/src/mainboard/purism/librem_l1um/acpi/platform.asl
new file mode 100644
index 0000000000..4cab1777c4
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/acpi/platform.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+Name(\APC1, Zero) // IIO IOAPIC
+
+Name(\PICM, Zero) // IOAPIC/8259
+
+Method(_PIC, 1)
+{
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/purism/librem_l1um/acpi_tables.c b/src/mainboard/purism/librem_l1um/acpi_tables.c
new file mode 100644
index 0000000000..7507f24fc7
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/acpi_tables.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/ioapic.h>
+#include <soc/acpi.h>
+#include <soc/iomap.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ u32 i;
+
+ current = acpi_create_madt_lapics(current);
+
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8,
+ IOXAPIC1_BASE_ADDRESS, 0);
+ set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8);
+
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9,
+ IOXAPIC2_BASE_ADDRESS, 24);
+ set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9);
+
+ current = acpi_madt_irq_overrides(current);
+
+ for (i = 0; i < 16; i++)
+ current += acpi_create_madt_lapic_nmi(
+ (acpi_madt_lapic_nmi_t *)current, i, 0xD, 1);
+
+ return current;
+}
diff --git a/src/mainboard/purism/librem_l1um/board_info.txt b/src/mainboard/purism/librem_l1um/board_info.txt
new file mode 100644
index 0000000000..fc8da9d5f5
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/board_info.txt
@@ -0,0 +1,8 @@
+Board name: Purism Librem Server L1UM
+Category: server
+Board URL: https://puri.sm/products/librem-server/
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: no
+Flashrom support: y
+Release year: 2020
diff --git a/src/mainboard/purism/librem_l1um/devicetree.cb b/src/mainboard/purism/librem_l1um/devicetree.cb
new file mode 100644
index 0000000000..5869b23e58
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/devicetree.cb
@@ -0,0 +1,96 @@
+chip soc/intel/fsp_broadwell_de
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # SoC router (6f00)
+ device pci 01.0 on end # CPU PCIe RP1 (6f02)
+ device pci 01.1 on end # CPU PCIe RP1 (6f03)
+ device pci 02.0 on end # CPU PCIe RP2 (6f04)
+ device pci 02.2 on end # CPU PCIe RP2 (6f06)
+ device pci 03.0 on end # CPU PCIe RP3 (6f08)
+ device pci 05.0 on end # Sys Mgmt (6f28)
+ device pci 05.1 on end # IIO HP (6f29)
+ device pci 05.2 on end # IIO RAS (6f2a)
+ device pci 05.4 on end # I/O APIC (6f2c)
+ device pci 05.6 off end # I/O Performance Monitoring (6f39)
+ device pci 06.0 off end # IIO Debug
+ device pci 06.1 off end # IIO Debug
+ device pci 06.2 off end # IIO Debug
+ device pci 06.3 off end # IIO Debug
+ device pci 06.4 off end # IIO Debug
+ device pci 06.5 off end # IIO Debug
+ device pci 06.6 off end # IIO Debug
+ device pci 06.7 off end # IIO Debug
+ device pci 07.0 off end # IIO Debug
+ device pci 07.1 off end # IIO Debug
+ device pci 07.2 off end # IIO Debug
+ device pci 07.3 off end # IIO Debug
+ device pci 07.4 off end # IIO Debug
+ device pci 14.0 on end # xHCI Controller (8c31)
+ device pci 16.0 off end # MEI Controller #1 (8c3a)
+ device pci 16.1 off end # MEI Controller #2 (8c3b)
+ device pci 16.2 off end # IDE-r Controller (8c3c)
+ device pci 16.3 off end # KT Controller (8c3d)
+ device pci 19.0 off end # Gigabit LAN Controller
+ device pci 1a.0 on end # EHCI Controller #2 (8c2d)
+ device pci 1c.0 on end # PCH PCIe RP1 (8c10)
+ device pci 1c.1 on end # PCH PCIe RP2 (8c12)
+ device pci 1c.3 on end # PCH PCIe RP4 (8c16)
+ device pci 1c.4 on end # PCH PCIe RP5 (8c18)
+ device pci 1d.0 on end # EHCI Controller #1 (8c26)
+ device pci 1f.0 on
+ chip drivers/ipmi
+ register "bmc_i2c_address" = "0x20"
+ device pnp ca2.0 on # IPMI KCS
+ irq 0x70 = 0x05
+ end
+ end
+ chip superio/common
+ device pnp 2e.0 on
+ chip superio/aspeed/ast2400
+ device pnp 2e.2 on # SUART1
+ io 0x60 = 0x3f8
+ irq 0x70 = 0x04
+ end
+ device pnp 2e.3 on # SUART2
+ io 0x60 = 0x2f8
+ irq 0x70 = 0x03
+ end
+ device pnp 2e.4 on # SWC
+ io 0x60 = 0x8e6
+ io 0x62 = 0x8e0
+ io 0x64 = 0x8e4
+ io 0x66 = 0x8e8
+ irq 0x70 = 0x09
+ end
+ device pnp 2e.5 off end # KBC
+ device pnp 2e.7 on end # GPIO
+ device pnp 2e.b on # SUART3
+ io 0x60 = 0x3e8
+ irq 0x70 = 0x06
+ end
+ device pnp 2e.c on # SUART4
+ io 0x60 = 0x2e8
+ irq 0x70 = 0x05
+ end
+ device pnp 2e.d on # iLPC2AHB
+ irq 0x70 = 0x09
+ end
+ device pnp 2e.e on # Mailbox
+ io 0x60 = 0x8c0
+ irq 0x70 = 0x09
+ end
+ end
+ end
+ end
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # LPC Bridge (8c54)
+ device pci 1f.2 on end # SATA Controller (8c02)
+ device pci 1f.3 on end # SMBus Controller (8c22)
+ device pci 1f.5 on end # SATA Controller
+ device pci 1f.6 on end # Thermal Mgmt Controller (8c24)
+ end
+end
diff --git a/src/mainboard/purism/librem_l1um/dsdt.asl b/src/mainboard/purism/librem_l1um/dsdt.asl
new file mode 100644
index 0000000000..c9dd6f5506
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/dsdt.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include "acpi/platform.asl"
+
+ Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
+ Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
+
+ Scope (\_SB)
+ {
+ Device (PCI0)
+ {
+ #include <acpi/southcluster.asl>
+ #include <acpi/pcie1.asl>
+ }
+
+ #include <acpi/uncore.asl>
+ }
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/purism/librem_l1um/fadt.c b/src/mainboard/purism/librem_l1um/fadt.c
new file mode 100644
index 0000000000..cba3b078fb
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/fadt.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ acpi_fill_in_fadt(fadt, facs, dsdt);
+
+ /* Platform specific customizations go here */
+
+ header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+}
diff --git a/src/mainboard/purism/librem_l1um/irqroute.c b/src/mainboard/purism/librem_l1um/irqroute.c
new file mode 100644
index 0000000000..fb2f90d0f4
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/irqroute.c
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/purism/librem_l1um/irqroute.h b/src/mainboard/purism/librem_l1um/irqroute.h
new file mode 100644
index 0000000000..82b9448f64
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/irqroute.h
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef IRQROUTE_H
+#define IRQROUTE_H
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D)
+
+/*
+ * Route each PIRQ[A-H] to a PIC IRQ[0-15]
+ * Reserved: 0, 1, 2, 8, 13
+ * ACPI/SCI: 9
+ */
+#define PIRQ_PIC_ROUTES \
+ PIRQ_PIC(A, 5), \
+ PIRQ_PIC(B, 6), \
+ PIRQ_PIC(C, 7), \
+ PIRQ_PIC(D, 10), \
+ PIRQ_PIC(E, 11), \
+ PIRQ_PIC(F, 12), \
+ PIRQ_PIC(G, 14), \
+ PIRQ_PIC(H, 15)
+
+#endif /* IRQROUTE_H */
diff --git a/src/mainboard/purism/librem_l1um/mainboard.c b/src/mainboard/purism/librem_l1um/mainboard.c
new file mode 100644
index 0000000000..7a017bdcaf
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/mainboard.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+
+/*
+ * mainboard_enable is executed as first thing after enumerate_buses().
+ * This is the earliest point to add customization.
+ */
+static void mainboard_enable(struct device *dev)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/purism/librem_l1um/romstage.c b/src/mainboard/purism/librem_l1um/romstage.c
new file mode 100644
index 0000000000..112eb264fc
--- /dev/null
+++ b/src/mainboard/purism/librem_l1um/romstage.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stddef.h>
+#include <soc/romstage.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
+#include <cpu/x86/msr.h>
+#include <cf9_reset.h>
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <soc/lpc.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, AST2400_SUART1)
+
+/**
+ * brief mainboard call for setup that needs to be done before fsp init
+ */
+void early_mainboard_romstage_entry(void)
+{
+ /*
+ * Sometimes the system boots in an invalid state, where random values
+ * have been written to MSRs and then the MSRs are locked.
+ * Seems to always happen on warm reset.
+ *
+ * Power cycling or a board_reset() isn't sufficient in this case, so
+ * issue a full_reset() to "fix" this issue.
+ */
+ msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
+ if (msr.lo & 1) {
+ console_init();
+ printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
+ full_reset();
+ }
+
+ /* enable early serial output */
+ aspeed_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+/*
+ * brief mainboard call for setup that needs to be done after fsp init
+ */
+void late_mainboard_romstage_entry(void)
+{
+ // IPMI through BIC
+ pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC,
+ 0x0c0ca1);
+}
+
+/*
+ * brief customize fsp parameters here if needed
+ */
+void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
+{
+ UPD_DATA_REGION *fsp_upd_data = FspRtBuffer->Common.UpdDataRgnPtr;
+
+ /* The internal UART operates on 0x3f8/0x2f8.
+ * As it's not wired up and conflicts with SuperIO decoding
+ * the same range, make sure to disable it.
+ */
+ fsp_upd_data->SerialPortConfigure = 0;
+ fsp_upd_data->SerialPortControllerInit0 = 0;
+ fsp_upd_data->SerialPortControllerInit1 = 0;
+
+ /* coreboot will initialize UART.
+ * No need for FSP to do it again.
+ */
+ fsp_upd_data->SerialPortConfigure = 0;
+ fsp_upd_data->SerialPortBaudRate = 0;
+
+ /* Make FSP use serial IO */
+ fsp_upd_data->SerialPortType = 1;
+
+ /* Set the bifurcation for IOU1 / port 0
+ * default xxxxxx8, set to xxxx8x8 to
+ * enable PCIe slot 0
+ */
+ fsp_upd_data->ConfigIOU1_PciPort3 = 3;
+
+ /* Set the bifurcation for IOU2 / port 1
+ * default xxxxxx8, set to xxxxx4x4 to
+ * enable SAS controller and NVMe to coexist
+ */
+ fsp_upd_data->ConfigIOU2_PciPort1 = 0;
+
+}
--
2.20.1

32
patches/coreboot-4.11/0010-cross-compiler-support.patch Normal file
View File

@ -0,0 +1,32 @@
diff --git a/Makefile b/Makefile
index f3f9592649..cb37557c81 100644
--- a/Makefile
+++ b/Makefile
@@ -164,6 +164,24 @@ $(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell util/xcompile/xcompile $(
-include .xcompile
+ifneq "$(CROSS)" ""
+ $(info coreboot: Using $(CROSS)gcc)
+ CROSS_COMPILE_x86_32 := $(CROSS)
+ CC_x86_32 := $(CROSS_COMPILE_x86_32)gcc
+ CPP_x86_32 := $(CROSS_COMPILE_x86_32)cpp
+ AS_x86_32 := $(CROSS_COMPILE_x86_32)as --32
+ LD_x86_32 := $(CROSS_COMPILE_x86_32)ld.bfd -b elf32-i386 -melf_i386
+ NM_x86_32 := $(CROSS_COMPILE_x86_32)nm
+ OBJCOPY_x86_32 := $(CROSS_COMPILE_x86_32)objcopy
+ OBJDUMP_x86_32 := $(CROSS_COMPILE_x86_32)objdump
+ READELF_x86_32 := $(CROSS_COMPILE_x86_32)readelf
+ STRIP_x86_32 := $(CROSS_COMPILE_x86_32)strip
+ AR_x86_32 := $(CROSS_COMPILE_x86_32)ar
+ GNATBIND_x86_32 := $(CROSS_COMPILE_x86_32)gnatbind
+ COMPILER_RT_x86_32 := $(shell $(CC_x86_32) --print-libgcc-file-name)
+endif
+
+
ifneq ($(XCOMPILE_COMPLETE),1)
$(shell rm -f .xcompile)
$(error .xcompile deleted because it's invalid. \
--
2.20.1