ExternalVendorCode/heads
1
0
Fork 0
mirror of https://github.com/linuxboot/heads.git synced 2024-12-18 20:47:55 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Librem13v2: Update to 4.7-Purism-4

Browse Source 
Fixes access to the EC through the Index I/O interface
Fixes AC and DC LoadLine values to avoid overheating problems
Fix Turbo mode value from EC
Change version name to have '-heads' suffix
This commit is contained in:
Youness Alaoui 2018-04-03 18:06:22 -04:00
parent 1fc114ba42
commit 16d9c405ac
No known key found for this signature in database
GPG Key ID: AAFC4B34BBEBB31C
4 changed files with 332 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
config/coreboot-librem13v2.config
View File

@ -7,7 +7,7 @@
# General setup # General setup
# #
CONFIG_COREBOOT_BUILD=y CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION="4.7-Purism-3" CONFIG_LOCALVERSION="4.7-Purism-4-heads"
CONFIG_CBFS_PREFIX="fallback" CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_COMPILER_LLVM_CLANG is not set

74
patches/coreboot-4.7/0016-purism-librem13v1-librem13v2-liberm15v3-Fix-EC-LPC-I.patch Normal file
View File

@ -0,0 +1,74 @@
From c6dd40b67a21bda1d8ec6043f19e4606a3695a05 Mon Sep 17 00:00:00 2001
From: Youness Alaoui <youness.alaoui@puri.sm>
Date: Tue, 13 Mar 2018 16:53:30 -0400
Subject: [PATCH 1/3] purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O
port
The LPC I/O ports for communicating with the EC were not set
properly causing ectool to fail to read the Index I/O from the EC.
The EC Index I/O is on port 0x380 and the LPC I/O port needs to be
decoded by the PCI device for it to be accessible.
This fixes it for the Librem 13v1, 13v2 and 15v3.
Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
---
src/mainboard/purism/librem13v1/devicetree.cb | 4 ++++
src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb | 6 +++---
src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb | 6 +++---
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/src/mainboard/purism/librem13v1/devicetree.cb b/src/mainboard/purism/librem13v1/devicetree.cb
index ba38070a55..c916e9a9a4 100644
--- a/src/mainboard/purism/librem13v1/devicetree.cb
+++ b/src/mainboard/purism/librem13v1/devicetree.cb
@@ -18,6 +18,10 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
+ # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
+ register "gen1_dec" = "0x00000381"
+ register "gen2_dec" = "0x000c0081"
+
# Port 0 is HDD
# Port 3 is M.2 NGFF
register "sata_port_map" = "0x9"
diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
index 159d921046..da97fb9ea7 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
@@ -24,9 +24,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
+ # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
+ register "gen1_dec" = "0x00000381"
+ register "gen2_dec" = "0x000c0081"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
index 035db18eff..deaf3a6deb 100644
--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
@@ -24,9 +24,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
+ # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
+ register "gen1_dec" = "0x00000381"
+ register "gen2_dec" = "0x000c0081"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
--
2.14.3

63
patches/coreboot-4.7/0017-ec-purism-Fix-the-CPU-s-PPCM-value-for-Turbo-when-se.patch Normal file
View File

@ -0,0 +1,63 @@
From 7cb5f11eac45c17bfdd096eb10db3115fc782b5b Mon Sep 17 00:00:00 2001
From: Youness Alaoui <youness.alaoui@puri.sm>
Date: Tue, 13 Mar 2018 16:58:52 -0400
Subject: [PATCH 2/3] ec/purism: Fix the CPU's PPCM value for Turbo when set by
the EC
The EC needs to set the PPCM value to 0, 1 or 2 depending on whether
the Turbo is enabled or not and the value differs from Broadwell and
Skylake machines.
Change-Id: I662dce54415e685c054ffc00b6afde0f1f7765e2
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
---
src/ec/purism/librem/acpi/ec.asl | 4 ++--
src/mainboard/purism/librem13v1/acpi/ec.asl | 2 ++
src/mainboard/purism/librem_skl/acpi/ec.asl | 2 ++
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl
index e95f126c63..ff325aa9a3 100644
--- a/src/ec/purism/librem/acpi/ec.asl
+++ b/src/ec/purism/librem/acpi/ec.asl
@@ -218,11 +218,11 @@ Device (EC)
* when the system is charging.
*/
If (TURB) {
- Store (Zero, PPCM)
+ Store (PPCM_TURBO, PPCM)
PPCN ()
Store (One, EDTB)
} Else {
- Store (One, PPCM)
+ Store (PPCM_NOTURBO, PPCM)
PPCN ()
Store (Zero, EDTB)
}
diff --git a/src/mainboard/purism/librem13v1/acpi/ec.asl b/src/mainboard/purism/librem13v1/acpi/ec.asl
index cf8b9a91d9..b2fa5b9924 100644
--- a/src/mainboard/purism/librem13v1/acpi/ec.asl
+++ b/src/mainboard/purism/librem13v1/acpi/ec.asl
@@ -14,5 +14,7 @@
*/
#define EC_SCI_GPI 10
+#define PPCM_TURBO Zero
+#define PPCM_NOTURBO One
#include <ec/purism/librem/acpi/ec.asl>
diff --git a/src/mainboard/purism/librem_skl/acpi/ec.asl b/src/mainboard/purism/librem_skl/acpi/ec.asl
index 4215213737..c667b6c41b 100644
--- a/src/mainboard/purism/librem_skl/acpi/ec.asl
+++ b/src/mainboard/purism/librem_skl/acpi/ec.asl
@@ -14,5 +14,7 @@
*/
#define EC_SCI_GPI 0x50
+#define PPCM_TURBO One
+#define PPCM_NOTURBO 0x02
#include <ec/purism/librem/acpi/ec.asl>
--
2.14.3

194
patches/coreboot-4.7/0018-purism-librem_skl-Add-AC-DC-LoadLine-to-VR-Config.patch Normal file
View File

@ -0,0 +1,194 @@
From 7ac4919b8af16b62fb63592dbdd43ca9215c0cf7 Mon Sep 17 00:00:00 2001
From: Youness Alaoui <youness.alaoui@puri.sm>
Date: Tue, 20 Mar 2018 18:32:23 -0400
Subject: [PATCH 3/3] purism/librem_skl: Add AC/DC LoadLine to VR Config
The FSP 2.0 needs to set the ac_loadline and dc_loadline for
each VR config. Without it, the Loadline is considered to be
0 mOhm and this causes CPU temp to jump all over the place
whenever the CPU is used.
These values were copied from the Google Poppy devicetree.
Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
---
.../librem_skl/variants/librem13v2/devicetree.cb | 40 ++++++++++++++--------
.../librem_skl/variants/librem15v3/devicetree.cb | 40 ++++++++++++++--------
2 files changed, 50 insertions(+), 30 deletions(-)
diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
index da97fb9ea7..a08a3df5f4 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
@@ -31,8 +31,8 @@ chip soc/intel/skylake
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
- # Enable DPTF
- register "dptf_enable" = "1"
+ # Disable DPTF
+ register "dptf_enable" = "0"
# FSP Configuration
register "ProbelessTrace" = "0"
@@ -82,19 +82,21 @@ chip soc/intel/skylake
register "pirqh_routing" = "PCH_IRQ11"
# VR Settings Configuration for 4 Domains
- #+----------------+-------+-------+-------------+-------+
- #| Domain/Setting | SA | IA | GT Unsliced | GT |
- #+----------------+-------+-------+-------------+-------+
- #| Psi1Threshold | 20A | 20A | 20A | 20A |
- #| Psi2Threshold | 4A | 5A | 5A | 5A |
- #| Psi3Threshold | 1A | 1A | 1A | 1A |
- #| Psi3Enable | 1 | 1 | 1 | 1 |
- #| Psi4Enable | 1 | 1 | 1 | 1 |
- #| ImonSlope | 0 | 0 | 0 | 0 |
- #| ImonOffset | 0 | 0 | 0 | 0 |
- #| IccMax | 7A | 34A | 35A | 35A |
- #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
- #+----------------+-------+-------+-------------+-------+
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
+ #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
+ #+----------------+-----------+-----------+-------------+----------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
@@ -106,6 +108,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(7),
.voltage_limit = 1520,
+ .ac_loadline = 1500,
+ .dc_loadline = 1430,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
@@ -119,6 +123,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(34),
.voltage_limit = 1520,
+ .ac_loadline = 570,
+ .dc_loadline = 483,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
@@ -132,6 +138,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520,
+ .ac_loadline = 520,
+ .dc_loadline = 420,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
@@ -145,6 +153,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520,
+ .ac_loadline = 520,
+ .dc_loadline = 420,
}"
# Enable Root Ports 5 and 9
diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
index deaf3a6deb..7dff719096 100644
--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
@@ -31,8 +31,8 @@ chip soc/intel/skylake
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
- # Enable DPTF
- register "dptf_enable" = "1"
+ # Disable DPTF
+ register "dptf_enable" = "0"
# FSP Configuration
register "ProbelessTrace" = "0"
@@ -82,19 +82,21 @@ chip soc/intel/skylake
register "pirqh_routing" = "PCH_IRQ11"
# VR Settings Configuration for 4 Domains
- #+----------------+-------+-------+-------------+-------+
- #| Domain/Setting | SA | IA | GT Unsliced | GT |
- #+----------------+-------+-------+-------------+-------+
- #| Psi1Threshold | 20A | 20A | 20A | 20A |
- #| Psi2Threshold | 4A | 5A | 5A | 5A |
- #| Psi3Threshold | 1A | 1A | 1A | 1A |
- #| Psi3Enable | 1 | 1 | 1 | 1 |
- #| Psi4Enable | 1 | 1 | 1 | 1 |
- #| ImonSlope | 0 | 0 | 0 | 0 |
- #| ImonOffset | 0 | 0 | 0 | 0 |
- #| IccMax | 7A | 34A | 35A | 35A |
- #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
- #+----------------+-------+-------+-------------+-------+
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Domain/Setting | SA | IA | GT Unsliced | GT |
+ #+----------------+-----------+-----------+-------------+----------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
+ #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
+ #+----------------+-----------+-----------+-------------+----------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
@@ -106,6 +108,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(7),
.voltage_limit = 1520,
+ .ac_loadline = 1500,
+ .dc_loadline = 1430,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
@@ -119,6 +123,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(34),
.voltage_limit = 1520,
+ .ac_loadline = 570,
+ .dc_loadline = 483,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
@@ -132,6 +138,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520,
+ .ac_loadline = 520,
+ .dc_loadline = 420,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
@@ -145,6 +153,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520,
+ .ac_loadline = 520,
+ .dc_loadline = 420,
}"
# Enable Root Ports 5 and 9
--
2.14.3