mirror of
https://github.com/linuxboot/heads.git
synced 2024-12-21 05:53:14 +00:00
59 lines
1.8 KiB
Diff
59 lines
1.8 KiB
Diff
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diff --git ./src/northbridge/intel/sandybridge/romstage.c ./src/northbridge/intel/sandybridge/romstage.c
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index 8608d5a..dac90ee 100644
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--- ./src/northbridge/intel/sandybridge/romstage.c
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+++ ./src/northbridge/intel/sandybridge/romstage.c
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@@ -29,6 +29,8 @@
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#include <device/device.h>
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#include <halt.h>
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#include <tpm.h>
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+#include <tpm_lite/tlcl.h>
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+#include <program_loading.h>
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#include <northbridge/intel/sandybridge/chip.h>
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#include "southbridge/intel/bd82x6x/pch.h"
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#include <southbridge/intel/common/gpio.h>
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@@ -72,6 +74,19 @@ void mainboard_romstage_entry(unsigned long bist)
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/* Initialize superio */
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mainboard_config_superio();
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+ if (IS_ENABLED(CONFIG_MEASURED_BOOT) && IS_ENABLED(CONFIG_LPC_TPM)) {
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+ // we don't know if we are coming out of a resume
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+ // at this point, but want to setup the tpm ASAP
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+ init_tpm(0);
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+ tlcl_lib_init();
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+ const void * const bootblock = (const void*) 0xFFFFF800;
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+ const unsigned bootblock_size = 0x800;
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+ tlcl_measure(0, bootblock, bootblock_size);
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+
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+ extern char _romstage, _eromstage;
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+ tlcl_measure(1, &_romstage, &_eromstage - &_romstage);
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+ }
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+
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/* USB is initialized in MRC if MRC is used. */
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if (CONFIG_USE_NATIVE_RAMINIT) {
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early_usb_init(mainboard_usb_ports);
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@@ -116,9 +131,23 @@ void mainboard_romstage_entry(unsigned long bist)
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northbridge_romstage_finalize(s3resume);
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- if (IS_ENABLED(CONFIG_LPC_TPM)) {
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+ // the normal TPM init happens here, if we haven't already
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+ // set it up as part of the measured boot.
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+ if (!IS_ENABLED(CONFIG_MEASURED_BOOT) && IS_ENABLED(CONFIG_LPC_TPM)) {
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init_tpm(s3resume);
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}
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+ printk(BIOS_DEBUG, "%s: romstage complete\n", __FILE__);
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+
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post_code(0x3f);
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}
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+
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+
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+void platform_segment_loaded(uintptr_t start, size_t size, int flags)
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+{
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+ if (IS_ENABLED(CONFIG_MEASURED_BOOT) && !(flags & SEG_NO_MEASURE))
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+ {
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+ tlcl_measure(2, (const void*) start, size);
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+ }
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+}
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+
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