mirror of
https://github.com/linuxboot/heads.git
synced 2025-04-06 19:06:49 +00:00
split coreboot patch into measured boot, kgpe-16 and sandybridge patches (#358)
This commit is contained in:
Trammell hudson
parent
18a7d5e16d
commit
3cbff7ed1e
@ -473,213 +473,3 @@ index 49854cb..32eb128 100644
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+ return tlcl_extend(pcr_num, hash, NULL);
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+}
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+
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diff --git ./src/mainboard/asus/kgpe-d16/Kconfig ./src/mainboard/asus/kgpe-d16/Kconfig
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index 531ba4f..5227d28 100644
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--- ./src/mainboard/asus/kgpe-d16/Kconfig
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+++ ./src/mainboard/asus/kgpe-d16/Kconfig
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@@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select BOARD_ROMSIZE_KB_2048
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select ENABLE_APIC_EXT_ID
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select SPI_FLASH
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+ select TPM2
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select MAINBOARD_HAS_LPC_TPM
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select HAVE_ACPI_RESUME
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select DRIVERS_I2C_W83795
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diff --git ./src/mainboard/asus/kgpe-d16/devicetree.cb ./src/mainboard/asus/kgpe-d16/devicetree.cb
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index 9039f6d..0ea4216 100644
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--- ./src/mainboard/asus/kgpe-d16/devicetree.cb
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+++ ./src/mainboard/asus/kgpe-d16/devicetree.cb
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@@ -217,6 +217,9 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
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chip drivers/pc80/tpm
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device pnp 4e.0 on end # TPM module
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end
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+ chip drivers/generic/generic # BMC KCS
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+ device pnp ca2.0 on end
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+ end
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end
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device pci 14.4 on # Bridge
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device pci 1.0 on end # VGA
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diff --git ./src/mainboard/asus/kgpe-d16/dsdt.asl ./src/mainboard/asus/kgpe-d16/dsdt.asl
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index 6a25b4d..cfcbc98 100644
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--- ./src/mainboard/asus/kgpe-d16/dsdt.asl
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+++ ./src/mainboard/asus/kgpe-d16/dsdt.asl
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@@ -50,6 +50,9 @@ DefinitionBlock (
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/* HPET enable */
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Name (HPTE, 0x1)
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+ /* IPMI KCS enable */
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+ Name (KCSE, 0x1)
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+
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#include <southbridge/amd/common/acpi/sleepstates.asl>
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/* The _PIC method is called by the OS to choose between interrupt
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@@ -485,6 +488,13 @@ DefinitionBlock (
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Name (_HID, EisaId ("PNP0A05"))
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Name (_ADR, 0x00140003)
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+ OperationRegion(BMRG, SystemIO, 0xca2, 0x02) /* BMC KCS registers */
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+ Field(BMRG, AnyAcc, NoLock, Preserve)
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+ {
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+ BMRI, 8, /* Index */
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+ BMRD, 8, /* Data */
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+ }
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+
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/* Real Time Clock Device */
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Device(RTC0) {
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Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
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@@ -606,6 +616,27 @@ DefinitionBlock (
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})
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}
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}
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+
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+ Device(KCS1) { /* IPMI KCS */
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+ Name(_HID,EISAID("IPI0001")) /* ASpeed BMC */
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+ Method (_STA, 0, NotSerialized) {
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+ If(KCSE) { /* Detection enabled */
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+ If(LNotEqual(BMRD, 0xff)) {
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+ Return(0x0f) /* Device present */
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+ }
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+ Return(Zero)
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+ }
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+ Return(Zero)
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+ }
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+ Method(_CRS, 0) {
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+ Return(ResourceTemplate() {
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+ IO(Decode16, 0x0ca2, 0x0ca2, 0x01, 0x02)
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+ })
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+ }
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+ Method (_IFT, 0, NotSerialized) { /* Interface type */
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+ Return(One) /* KCS interface */
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+ }
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+ }
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}
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/* High Precision Event Timer */
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diff --git ./src/mainboard/asus/kgpe-d16/mainboard.c ./src/mainboard/asus/kgpe-d16/mainboard.c
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index 65029d4..8ee3a5e 100644
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--- ./src/mainboard/asus/kgpe-d16/mainboard.c
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+++ ./src/mainboard/asus/kgpe-d16/mainboard.c
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@@ -70,6 +70,13 @@ static void mainboard_enable(device_t dev)
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set_pcie_dereset();
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/* get_ide_dma66(); */
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+
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+ /* Enable access to the BMC IPMI via KCS */
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+ device_t lpc_sio_dev = dev_find_slot_pnp(0xca2, 0);
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+ struct resource *res = new_resource(lpc_sio_dev, 0xca2);
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+ res->base = 0xca2;
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+ res->size = 1;
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+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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/* override the default SATA PHY setup */
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diff --git ./src/mainboard/asus/kgpe-d16/romstage.c ./src/mainboard/asus/kgpe-d16/romstage.c
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index 63b93c1..bb4f181 100644
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--- ./src/mainboard/asus/kgpe-d16/romstage.c
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+++ ./src/mainboard/asus/kgpe-d16/romstage.c
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@@ -88,6 +88,47 @@ static void switch_spd_mux(uint8_t channel)
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byte &= ~0xc0; /* Enable SPD mux GPIO output drivers */
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byte |= (channel << 2) & 0xc; /* Set SPD mux GPIOs */
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pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte);
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+
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+ /* Temporary AST PCI mapping */
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+ uint32_t base_memory = 0xfc000000;
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+ uint32_t memory_limit = 0xfc800000;
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+
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+ /* Temporarily enable the SP5100 PCI bridge */
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+ uint16_t prev_sec_cfg = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x04);
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+ uint8_t prev_sec_bus = pci_read_config8(PCI_DEV(0, 0x14, 4), 0x19);
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+ uint8_t prev_sec_sub_bus = pci_read_config8(PCI_DEV(0, 0x14, 4), 0x1a);
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+ uint16_t prev_sec_mem_base = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x20);
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+ uint16_t prev_sec_mem_limit = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x22);
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+ pci_write_config8(PCI_DEV(0, 0x14, 4), 0x19, 0x01);
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+ pci_write_config8(PCI_DEV(0, 0x14, 4), 0x1a, 0xff);
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+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x20, (base_memory >> 20));
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+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x22, (memory_limit >> 20));
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+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x04, 0x2);
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+
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+ /* Temporarily enable AST BAR1 */
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+ uint32_t prev_ast_cfg = pci_read_config32(PCI_DEV(1, 0x1, 0), 0x04);
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+ uint32_t prev_ast_bar1 = pci_read_config32(PCI_DEV(1, 0x1, 0), 0x14);
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+ pci_write_config32(PCI_DEV(1, 0x1, 0), 0x14, base_memory);
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+ pci_write_config32(PCI_DEV(1, 0x1, 0), 0x04, 0x02100002);
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+
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+ /* Use the P2A bridge to set ASpeed SPD mux GPIOs to the same values as the SP5100 */
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+ void* ast_bar1 = (void*)base_memory;
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+ write32(ast_bar1 + 0xf004, 0x1e780000); /* Enable access to GPIO controller */
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+ write32(ast_bar1 + 0xf000, 0x1);
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+ write32(ast_bar1 + 0x10024, read32(ast_bar1 + 0x10024) | 0x3000); /* Enable SPD mux GPIO output drivers */
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+ write32(ast_bar1 + 0x10020, (read32(ast_bar1 + 0x10020) & ~0x3000) | ((channel & 0x3) << 12)); /* Set SPD mux GPIOs */
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+ write32(ast_bar1 + 0xf000, 0x0);
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+
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+ /* Deconfigure AST BAR1 */
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+ pci_write_config32(PCI_DEV(1, 0x1, 0), 0x04, prev_ast_cfg);
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+ pci_write_config32(PCI_DEV(1, 0x1, 0), 0x14, prev_ast_bar1);
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+
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+ /* Deconfigure SP5100 PCI bridge */
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+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x04, prev_sec_cfg);
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+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x22, prev_sec_mem_limit);
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+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x20, prev_sec_mem_base);
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+ pci_write_config8(PCI_DEV(0, 0x14, 4), 0x1a, prev_sec_sub_bus);
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+ pci_write_config8(PCI_DEV(0, 0x14, 4), 0x19, prev_sec_bus);
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}
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static const uint8_t spd_addr_fam15[] = {
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diff --git ./src/northbridge/intel/sandybridge/romstage.c ./src/northbridge/intel/sandybridge/romstage.c
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index 8608d5a..dac90ee 100644
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--- ./src/northbridge/intel/sandybridge/romstage.c
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+++ ./src/northbridge/intel/sandybridge/romstage.c
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@@ -29,6 +29,8 @@
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#include <device/device.h>
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#include <halt.h>
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#include <tpm.h>
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+#include <tpm_lite/tlcl.h>
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+#include <program_loading.h>
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#include <northbridge/intel/sandybridge/chip.h>
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#include "southbridge/intel/bd82x6x/pch.h"
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#include <southbridge/intel/common/gpio.h>
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@@ -72,6 +74,19 @@ void mainboard_romstage_entry(unsigned long bist)
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/* Initialize superio */
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mainboard_config_superio();
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+ if (IS_ENABLED(CONFIG_MEASURED_BOOT) && IS_ENABLED(CONFIG_LPC_TPM)) {
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+ // we don't know if we are coming out of a resume
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+ // at this point, but want to setup the tpm ASAP
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+ init_tpm(0);
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+ tlcl_lib_init();
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+ const void * const bootblock = (const void*) 0xFFFFF800;
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+ const unsigned bootblock_size = 0x800;
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+ tlcl_measure(0, bootblock, bootblock_size);
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+
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+ extern char _romstage, _eromstage;
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+ tlcl_measure(1, &_romstage, &_eromstage - &_romstage);
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+ }
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+
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/* USB is initialized in MRC if MRC is used. */
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if (CONFIG_USE_NATIVE_RAMINIT) {
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early_usb_init(mainboard_usb_ports);
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@@ -116,9 +131,23 @@ void mainboard_romstage_entry(unsigned long bist)
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northbridge_romstage_finalize(s3resume);
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- if (IS_ENABLED(CONFIG_LPC_TPM)) {
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+ // the normal TPM init happens here, if we haven't already
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+ // set it up as part of the measured boot.
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+ if (!IS_ENABLED(CONFIG_MEASURED_BOOT) && IS_ENABLED(CONFIG_LPC_TPM)) {
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init_tpm(s3resume);
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}
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+ printk(BIOS_DEBUG, "%s: romstage complete\n", __FILE__);
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+
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post_code(0x3f);
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}
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+
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+
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+void platform_segment_loaded(uintptr_t start, size_t size, int flags)
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+{
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+ if (IS_ENABLED(CONFIG_MEASURED_BOOT) && !(flags & SEG_NO_MEASURE))
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+ {
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+ tlcl_measure(2, (const void*) start, size);
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+ }
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+}
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+
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152
patches/coreboot-4.7/0020-kgpe-d16.patch
Normal file
152
patches/coreboot-4.7/0020-kgpe-d16.patch
Normal file
@ -0,0 +1,152 @@
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diff --git ./src/mainboard/asus/kgpe-d16/Kconfig ./src/mainboard/asus/kgpe-d16/Kconfig
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index 531ba4f..5227d28 100644
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--- ./src/mainboard/asus/kgpe-d16/Kconfig
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+++ ./src/mainboard/asus/kgpe-d16/Kconfig
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@@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select BOARD_ROMSIZE_KB_2048
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select ENABLE_APIC_EXT_ID
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select SPI_FLASH
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+ select TPM2
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select MAINBOARD_HAS_LPC_TPM
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select HAVE_ACPI_RESUME
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select DRIVERS_I2C_W83795
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diff --git ./src/mainboard/asus/kgpe-d16/devicetree.cb ./src/mainboard/asus/kgpe-d16/devicetree.cb
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index 9039f6d..0ea4216 100644
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--- ./src/mainboard/asus/kgpe-d16/devicetree.cb
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+++ ./src/mainboard/asus/kgpe-d16/devicetree.cb
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@@ -217,6 +217,9 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
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chip drivers/pc80/tpm
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device pnp 4e.0 on end # TPM module
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end
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+ chip drivers/generic/generic # BMC KCS
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+ device pnp ca2.0 on end
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+ end
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end
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device pci 14.4 on # Bridge
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device pci 1.0 on end # VGA
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diff --git ./src/mainboard/asus/kgpe-d16/dsdt.asl ./src/mainboard/asus/kgpe-d16/dsdt.asl
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index 6a25b4d..cfcbc98 100644
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--- ./src/mainboard/asus/kgpe-d16/dsdt.asl
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+++ ./src/mainboard/asus/kgpe-d16/dsdt.asl
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@@ -50,6 +50,9 @@ DefinitionBlock (
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/* HPET enable */
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Name (HPTE, 0x1)
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+ /* IPMI KCS enable */
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+ Name (KCSE, 0x1)
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+
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#include <southbridge/amd/common/acpi/sleepstates.asl>
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/* The _PIC method is called by the OS to choose between interrupt
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@@ -485,6 +488,13 @@ DefinitionBlock (
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Name (_HID, EisaId ("PNP0A05"))
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Name (_ADR, 0x00140003)
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+ OperationRegion(BMRG, SystemIO, 0xca2, 0x02) /* BMC KCS registers */
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+ Field(BMRG, AnyAcc, NoLock, Preserve)
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+ {
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+ BMRI, 8, /* Index */
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+ BMRD, 8, /* Data */
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+ }
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+
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/* Real Time Clock Device */
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Device(RTC0) {
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Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
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@@ -606,6 +616,27 @@ DefinitionBlock (
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})
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}
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}
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+
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+ Device(KCS1) { /* IPMI KCS */
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+ Name(_HID,EISAID("IPI0001")) /* ASpeed BMC */
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+ Method (_STA, 0, NotSerialized) {
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+ If(KCSE) { /* Detection enabled */
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+ If(LNotEqual(BMRD, 0xff)) {
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+ Return(0x0f) /* Device present */
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+ }
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+ Return(Zero)
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+ }
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+ Return(Zero)
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+ }
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+ Method(_CRS, 0) {
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+ Return(ResourceTemplate() {
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+ IO(Decode16, 0x0ca2, 0x0ca2, 0x01, 0x02)
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+ })
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+ }
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+ Method (_IFT, 0, NotSerialized) { /* Interface type */
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+ Return(One) /* KCS interface */
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+ }
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+ }
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}
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/* High Precision Event Timer */
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diff --git ./src/mainboard/asus/kgpe-d16/mainboard.c ./src/mainboard/asus/kgpe-d16/mainboard.c
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index 65029d4..8ee3a5e 100644
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--- ./src/mainboard/asus/kgpe-d16/mainboard.c
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+++ ./src/mainboard/asus/kgpe-d16/mainboard.c
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@@ -70,6 +70,13 @@ static void mainboard_enable(device_t dev)
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set_pcie_dereset();
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/* get_ide_dma66(); */
|
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+
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+ /* Enable access to the BMC IPMI via KCS */
|
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+ device_t lpc_sio_dev = dev_find_slot_pnp(0xca2, 0);
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+ struct resource *res = new_resource(lpc_sio_dev, 0xca2);
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+ res->base = 0xca2;
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+ res->size = 1;
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+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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/* override the default SATA PHY setup */
|
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diff --git ./src/mainboard/asus/kgpe-d16/romstage.c ./src/mainboard/asus/kgpe-d16/romstage.c
|
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index 63b93c1..bb4f181 100644
|
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--- ./src/mainboard/asus/kgpe-d16/romstage.c
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+++ ./src/mainboard/asus/kgpe-d16/romstage.c
|
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@@ -88,6 +88,47 @@ static void switch_spd_mux(uint8_t channel)
|
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byte &= ~0xc0; /* Enable SPD mux GPIO output drivers */
|
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byte |= (channel << 2) & 0xc; /* Set SPD mux GPIOs */
|
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pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte);
|
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+
|
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+ /* Temporary AST PCI mapping */
|
||||
+ uint32_t base_memory = 0xfc000000;
|
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+ uint32_t memory_limit = 0xfc800000;
|
||||
+
|
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+ /* Temporarily enable the SP5100 PCI bridge */
|
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+ uint16_t prev_sec_cfg = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x04);
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+ uint8_t prev_sec_bus = pci_read_config8(PCI_DEV(0, 0x14, 4), 0x19);
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+ uint8_t prev_sec_sub_bus = pci_read_config8(PCI_DEV(0, 0x14, 4), 0x1a);
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+ uint16_t prev_sec_mem_base = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x20);
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+ uint16_t prev_sec_mem_limit = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x22);
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+ pci_write_config8(PCI_DEV(0, 0x14, 4), 0x19, 0x01);
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+ pci_write_config8(PCI_DEV(0, 0x14, 4), 0x1a, 0xff);
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+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x20, (base_memory >> 20));
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+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x22, (memory_limit >> 20));
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+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x04, 0x2);
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+
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+ /* Temporarily enable AST BAR1 */
|
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+ uint32_t prev_ast_cfg = pci_read_config32(PCI_DEV(1, 0x1, 0), 0x04);
|
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+ uint32_t prev_ast_bar1 = pci_read_config32(PCI_DEV(1, 0x1, 0), 0x14);
|
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+ pci_write_config32(PCI_DEV(1, 0x1, 0), 0x14, base_memory);
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+ pci_write_config32(PCI_DEV(1, 0x1, 0), 0x04, 0x02100002);
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+
|
||||
+ /* Use the P2A bridge to set ASpeed SPD mux GPIOs to the same values as the SP5100 */
|
||||
+ void* ast_bar1 = (void*)base_memory;
|
||||
+ write32(ast_bar1 + 0xf004, 0x1e780000); /* Enable access to GPIO controller */
|
||||
+ write32(ast_bar1 + 0xf000, 0x1);
|
||||
+ write32(ast_bar1 + 0x10024, read32(ast_bar1 + 0x10024) | 0x3000); /* Enable SPD mux GPIO output drivers */
|
||||
+ write32(ast_bar1 + 0x10020, (read32(ast_bar1 + 0x10020) & ~0x3000) | ((channel & 0x3) << 12)); /* Set SPD mux GPIOs */
|
||||
+ write32(ast_bar1 + 0xf000, 0x0);
|
||||
+
|
||||
+ /* Deconfigure AST BAR1 */
|
||||
+ pci_write_config32(PCI_DEV(1, 0x1, 0), 0x04, prev_ast_cfg);
|
||||
+ pci_write_config32(PCI_DEV(1, 0x1, 0), 0x14, prev_ast_bar1);
|
||||
+
|
||||
+ /* Deconfigure SP5100 PCI bridge */
|
||||
+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x04, prev_sec_cfg);
|
||||
+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x22, prev_sec_mem_limit);
|
||||
+ pci_write_config16(PCI_DEV(0, 0x14, 4), 0x20, prev_sec_mem_base);
|
||||
+ pci_write_config8(PCI_DEV(0, 0x14, 4), 0x1a, prev_sec_sub_bus);
|
||||
+ pci_write_config8(PCI_DEV(0, 0x14, 4), 0x19, prev_sec_bus);
|
||||
}
|
||||
|
||||
static const uint8_t spd_addr_fam15[] = {
|
||||
58
patches/coreboot-4.7/0030-sandybridge.patch
Normal file
58
patches/coreboot-4.7/0030-sandybridge.patch
Normal file
@ -0,0 +1,58 @@
|
||||
diff --git ./src/northbridge/intel/sandybridge/romstage.c ./src/northbridge/intel/sandybridge/romstage.c
|
||||
index 8608d5a..dac90ee 100644
|
||||
--- ./src/northbridge/intel/sandybridge/romstage.c
|
||||
+++ ./src/northbridge/intel/sandybridge/romstage.c
|
||||
@@ -29,6 +29,8 @@
|
||||
#include <device/device.h>
|
||||
#include <halt.h>
|
||||
#include <tpm.h>
|
||||
+#include <tpm_lite/tlcl.h>
|
||||
+#include <program_loading.h>
|
||||
#include <northbridge/intel/sandybridge/chip.h>
|
||||
#include "southbridge/intel/bd82x6x/pch.h"
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
@@ -72,6 +74,19 @@ void mainboard_romstage_entry(unsigned long bist)
|
||||
/* Initialize superio */
|
||||
mainboard_config_superio();
|
||||
|
||||
+ if (IS_ENABLED(CONFIG_MEASURED_BOOT) && IS_ENABLED(CONFIG_LPC_TPM)) {
|
||||
+ // we don't know if we are coming out of a resume
|
||||
+ // at this point, but want to setup the tpm ASAP
|
||||
+ init_tpm(0);
|
||||
+ tlcl_lib_init();
|
||||
+ const void * const bootblock = (const void*) 0xFFFFF800;
|
||||
+ const unsigned bootblock_size = 0x800;
|
||||
+ tlcl_measure(0, bootblock, bootblock_size);
|
||||
+
|
||||
+ extern char _romstage, _eromstage;
|
||||
+ tlcl_measure(1, &_romstage, &_eromstage - &_romstage);
|
||||
+ }
|
||||
+
|
||||
/* USB is initialized in MRC if MRC is used. */
|
||||
if (CONFIG_USE_NATIVE_RAMINIT) {
|
||||
early_usb_init(mainboard_usb_ports);
|
||||
@@ -116,9 +131,23 @@ void mainboard_romstage_entry(unsigned long bist)
|
||||
|
||||
northbridge_romstage_finalize(s3resume);
|
||||
|
||||
- if (IS_ENABLED(CONFIG_LPC_TPM)) {
|
||||
+ // the normal TPM init happens here, if we haven't already
|
||||
+ // set it up as part of the measured boot.
|
||||
+ if (!IS_ENABLED(CONFIG_MEASURED_BOOT) && IS_ENABLED(CONFIG_LPC_TPM)) {
|
||||
init_tpm(s3resume);
|
||||
}
|
||||
|
||||
+ printk(BIOS_DEBUG, "%s: romstage complete\n", __FILE__);
|
||||
+
|
||||
post_code(0x3f);
|
||||
}
|
||||
+
|
||||
+
|
||||
+void platform_segment_loaded(uintptr_t start, size_t size, int flags)
|
||||
+{
|
||||
+ if (IS_ENABLED(CONFIG_MEASURED_BOOT) && !(flags & SEG_NO_MEASURE))
|
||||
+ {
|
||||
+ tlcl_measure(2, (const void*) start, size);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
Loading…
x
Reference in New Issue
Block a user