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99 lines
2.4 KiB
C++
99 lines
2.4 KiB
C++
/*
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* \brief MMIO and IRQ definitions common to i.MX6 SoC
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* \author Nikolay Golikov <nik@ksyslabs.org>
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* \author Josef Soentgen
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* \author Martin Stein
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* \date 2017-06-20
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__DRIVERS__DEFS__IMX6_H_
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#define _INCLUDE__DRIVERS__DEFS__IMX6_H_
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namespace Imx6 {
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enum {
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/* device IO memory */
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MMIO_BASE = 0x00000000,
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MMIO_SIZE = 0x10000000,
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UART_1_IRQ = 58,
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UART_1_MMIO_BASE = 0x02020000,
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UART_1_MMIO_SIZE = 0x00004000,
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UART_2_IRQ = 59,
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UART_2_MMIO_BASE = 0x021e8000,
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UART_2_MMIO_SIZE = 0x00004000,
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/* timer */
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EPIT_2_IRQ = 89,
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EPIT_2_MMIO_BASE = 0x020d4000,
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EPIT_2_MMIO_SIZE = 0x00004000,
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/* ARM IP Bus control */
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AIPS_1_MMIO_BASE = 0x0207c000,
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AIPS_1_MMIO_SIZE = 0x00004000,
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AIPS_2_MMIO_BASE = 0x0217c000,
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AIPS_2_MMIO_SIZE = 0x00004000,
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x00a00000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
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CORTEX_A9_PRIVATE_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
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CORTEX_A9_PRIVATE_TIMER_DIV = 100,
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/* L2 cache controller */
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PL310_MMIO_BASE = 0x00a02000,
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PL310_MMIO_SIZE = 0x00001000,
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/* System reset controller */
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SRC_MMIO_BASE = 0x20d8000,
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/* CPU cache */
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CACHE_LINE_SIZE_LOG2 = 5,
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/* SD host controller */
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SDHC_IRQ = 54,
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SDHC_MMIO_BASE = 0x02190000,
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SDHC_MMIO_SIZE = 0x00004000,
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/* GPIO */
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GPIO1_MMIO_BASE = 0x0209c000,
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GPIO1_MMIO_SIZE = 0x4000,
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GPIO2_MMIO_BASE = 0x020a0000,
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GPIO2_MMIO_SIZE = 0x4000,
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GPIO3_MMIO_BASE = 0x020a4000,
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GPIO3_MMIO_SIZE = 0x4000,
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GPIO4_MMIO_BASE = 0x020a8000,
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GPIO4_MMIO_SIZE = 0x4000,
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GPIO5_MMIO_BASE = 0x020ac000,
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GPIO5_MMIO_SIZE = 0x4000,
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GPIO6_MMIO_BASE = 0x020b0000,
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GPIO6_MMIO_SIZE = 0x4000,
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GPIO7_MMIO_BASE = 0x020b4000,
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GPIO7_MMIO_SIZE = 0x4000,
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GPIO1_IRQL = 98,
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GPIO1_IRQH = 99,
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GPIO2_IRQL = 100,
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GPIO2_IRQH = 101,
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GPIO3_IRQL = 102,
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GPIO3_IRQH = 103,
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GPIO4_IRQL = 104,
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GPIO4_IRQH = 105,
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GPIO5_IRQL = 106,
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GPIO5_IRQH = 107,
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GPIO6_IRQL = 108,
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GPIO6_IRQH = 109,
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GPIO7_IRQL = 110,
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GPIO7_IRQH = 111,
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};
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};
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#endif /* _INCLUDE__DRIVERS__DEFS__IMX6_H_ */
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