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6106e64aac
This commit moves the headers residing in `repos/base/include/spec/*/drivers` to `repos/base/include/drivers/defs` or repos/base/include/drivers/uart` respectively. The first one contains definitions about board-specific MMIO iand RAM addresses, or IRQ lines. While the latter contains device driver code for UART devices. Those definitions are used by driver implementations in `repos/base-hw`, `repos/os`, and `repos/dde-linux`, which now need to include them more explicitely. This work is a step in the direction of reducing 'SPEC' identifiers overall. Ref #2403
76 lines
1.7 KiB
C++
76 lines
1.7 KiB
C++
/*
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* \brief MMIO and IRQ definitions for the Raspberry Pi
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* \author Norman Feske
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* \date 2013-04-05
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__DRIVERS__DEFS__RPI_H_
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#define _INCLUDE__DRIVERS__DEFS__RPI_H_
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/* Genode includes */
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#include <util/mmio.h>
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namespace Rpi {
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enum {
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RAM_0_BASE = 0x00000000,
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RAM_0_SIZE = 0x10000000, /* XXX ? */
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MMIO_0_BASE = 0x20000000,
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MMIO_0_SIZE = 0x02000000,
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/*
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* IRQ numbers 0..7 refer to the basic IRQs.
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* IRQ numbers 8..39 refer to GPU IRQs 0..31.
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* IRQ numbers 40..71 refer to GPU IRQs 32..63.
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*/
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GPU_IRQ_BASE = 8,
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SYSTEM_TIMER_IRQ = GPU_IRQ_BASE + 1,
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SYSTEM_TIMER_MMIO_BASE = 0x20003000,
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SYSTEM_TIMER_MMIO_SIZE = 0x1000,
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SYSTEM_TIMER_CLOCK = 1000000,
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PL011_0_IRQ = 57,
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PL011_0_MMIO_BASE = 0x20201000,
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PL011_0_MMIO_SIZE = 0x1000,
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PL011_0_CLOCK = 3000000,
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IRQ_CONTROLLER_BASE = 0x2000b200,
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IRQ_CONTROLLER_SIZE = 0x100,
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GPIO_CONTROLLER_BASE = 0x20200000,
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GPIO_CONTROLLER_SIZE = 0x1000,
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USB_DWC_OTG_BASE = 0x20980000,
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USB_DWC_OTG_SIZE = 0x20000,
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/* timer */
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TIMER_IRQ = 0,
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/* USB host controller */
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DWC_IRQ = 17,
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/* CPU cache */
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CACHE_LINE_SIZE_LOG2 = 5,
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/* SD card */
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SDHCI_BASE = MMIO_0_BASE + 0x300000,
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SDHCI_SIZE = 0x100,
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SDHCI_IRQ = 62,
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};
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enum Videocore_cache_policy { NON_COHERENT = 0,
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COHERENT = 1,
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L2_ONLY = 2,
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UNCACHED = 3 };
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};
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#endif /* _INCLUDE__DRIVERS__DEFS__RPI_H_ */
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