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base: remove include/spec/* other than ISA

Browse Source 
This commit moves the headers residing in `repos/base/include/spec/*/drivers`
to `repos/base/include/drivers/defs` or repos/base/include/drivers/uart`
respectively. The first one contains definitions about board-specific MMIO
iand RAM addresses, or IRQ lines. While the latter contains device driver
code for UART devices. Those definitions are used by driver implementations
in `repos/base-hw`, `repos/os`, and `repos/dde-linux`, which now need to
include them more explicitely.

This work is a step in the direction of reducing 'SPEC' identifiers overall.

Ref #2403
This commit is contained in:
Stefan Kalkowski 2017-04-28 15:27:26 +02:00 committed by Christian Helmuth
parent 80eddd8731
commit 6106e64aac
180 changed files with 1018 additions and 1251 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
repos/base-hw/etc/specs.conf
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@ -4,7 +4,7 @@ ifeq ($(filter-out $(SPECS),x86_64),)
SPECS += pci ps2 vesa framebuffer
ifneq ($(filter-out $(SPECS),muen),)
SPECS += acpi
SPECS += acpi x86_pc
endif
endif

6
repos/base-hw/include/spec/imx53/drivers/trustzone.h
View File

@ -15,7 +15,7 @@
#define _INCLUDE__SPEC__IMX53__DRIVERS__TRUSTZONE_H_
/* Genode includes */
#include <drivers/board_base.h>
#include <drivers/defs/imx53.h>
namespace Trustzone
{
@ -26,9 +26,9 @@ namespace Trustzone
* on this platform allows to protect a max. region of
* 256MB per RAM bank only.
*/
SECURE_RAM_BASE = Genode::Board_base::RAM0_BASE,
SECURE_RAM_BASE = Imx53::RAM_BANK_0_BASE,
SECURE_RAM_SIZE = 256 * 1024 * 1024,
NONSECURE_RAM_BASE = Genode::Board_base::RAM0_BASE + SECURE_RAM_SIZE,
NONSECURE_RAM_BASE = Imx53::RAM_BANK_0_BASE + SECURE_RAM_SIZE,
NONSECURE_RAM_SIZE = 256 * 1024 * 1024,
};
}

10
repos/base-hw/lib/mk/core-hw-muen.mk
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@ -1,10 +0,0 @@
#
# \brief Build config for parts of core that depend on Muen status
# \author Stefan Kalkowski
# \date 2015-06-02
#
REQUIRES = x86_64
# add library dependencies
LIBS += core-hw-muen_off

11
repos/base-hw/lib/mk/core-hw-trustzone.mk
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@ -1,11 +0,0 @@
#
# \brief Build config for parts of core that depend on Trustzone status
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
#
REQUIRES = imx53
# add library dependencies
LIBS += core-hw-trustzone_off

1
repos/base-hw/lib/mk/spec/arndale/core-hw.mk
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@ -5,6 +5,7 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/arndale
INC_DIR += $(REP_DIR)/src/core/spec/arm_v7/virtualization
# add C++ sources

1
repos/base-hw/lib/mk/spec/exynos5/core-hw.inc
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@ -9,6 +9,7 @@ INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/exynos5
# add C++ sources
SRC_CC += spec/exynos5/cpu.cc
SRC_CC += spec/exynos5/timer.cc
# include less specific configuration
include $(BASE_DIR)/../base-hw/lib/mk/spec/cortex_a15/core-hw.inc

13
repos/base-hw/lib/mk/spec/imx53/core-hw-trustzone_off.mk
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@ -1,13 +0,0 @@
#
# \brief Build config for parts of core that depend on Trustzone status
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
#
# add C++ sources
SRC_CC += kernel/vm_thread_off.cc
SRC_CC += platform_services.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/imx53/core-hw.inc

16
repos/base-hw/lib/mk/spec/imx53/core-hw.inc
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@ -1,16 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/imx53
INC_DIR += $(REP_DIR)/src/core/spec/imx
SRC_CC += spec/imx53/pic.cc
SRC_CC += spec/arm/cpu_context_trustzone.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/cortex_a8/core-hw.inc

1
repos/base-hw/lib/mk/spec/imx53/core-hw.mk
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@ -1 +0,0 @@
LIBS += core-hw-trustzone

11
repos/base-hw/lib/mk/spec/imx53_qsb/core-hw-trustzone_on.mk
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@ -1,11 +0,0 @@
#
# \brief Build config for parts of core that depend on Trustzone status
# \author Martin Stein
# \date 2015-10-30
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/imx53_qsb/trustzone
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/imx53/core-hw-trustzone_on.inc

34
repos/base-hw/lib/mk/spec/imx53_qsb/core-hw.mk Normal file
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@ -0,0 +1,34 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/imx53_qsb
INC_DIR += $(REP_DIR)/src/core/spec/imx53
INC_DIR += $(REP_DIR)/src/core/spec/imx
SRC_CC += spec/imx53/pic.cc
SRC_CC += spec/imx53/timer.cc
SRC_CC += spec/arm/cpu_context_trustzone.cc
ifneq ($(filter-out $(SPECS),trustzone),)
SRC_CC += kernel/vm_thread_off.cc
SRC_CC += platform_services.cc
else
INC_DIR += $(REP_DIR)/src/core/spec/arm_v7/trustzone
INC_DIR += $(REP_DIR)/src/core/spec/imx53/trustzone
SRC_CC += spec/imx53/trustzone/platform_services.cc
SRC_CC += kernel/vm_thread_on.cc
SRC_CC += spec/arm_v7/trustzone/kernel/vm.cc
SRC_CC += spec/arm_v7/vm_session_component.cc
SRC_CC += spec/arm_v7/trustzone/vm_session_component.cc
SRC_S += spec/arm_v7/trustzone/mode_transition.s
endif
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/cortex_a8/core-hw.inc

2
repos/base-hw/lib/mk/spec/imx6/core-hw.mk
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@ -7,7 +7,7 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/imx6
INC_DIR += $(REP_DIR)/src/core/spec/wand_quad
INC_DIR += $(REP_DIR)/src/core/spec/imx
# add C++ sources

11
repos/base-hw/lib/mk/spec/x86_64/bootstrap-hw.mk → repos/base-hw/lib/mk/spec/muen/bootstrap-hw.mk
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@ -1,14 +1,9 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/x86_64
SRC_S += bootstrap/spec/x86_64/crt0.s
ifneq ($(filter-out $(SPECS),muen),)
SRC_CC += bootstrap/spec/x86_64/platform.cc
SRC_S += bootstrap/spec/x86_64/crt0_translation_table.s
else
SRC_CC += lib/muen/sinfo.cc
SRC_CC += bootstrap/spec/x86_64/platform_muen.cc
SRC_CC += lib/muen/sinfo.cc
SRC_S += bootstrap/spec/x86_64/crt0.s
SRC_S += bootstrap/spec/x86_64/crt0_translation_table_muen.s
endif
include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc

1
repos/base-hw/lib/mk/spec/muen/core-hw-muen.mk
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@ -1 +0,0 @@
LIBS += core-hw-muen_on

44
repos/base-hw/lib/mk/spec/muen/core-hw.mk Normal file
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@ -0,0 +1,44 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-04
#
REQUIRES = muen
LIBS += sinfo-muen
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/x86_64/muen
INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/x86_64
# add assembly sources
SRC_S += spec/x86_64/mode_transition.s
SRC_S += spec/x86_64/crt0.s
# add C++ sources
SRC_CC += spec/x86_64/muen/kernel/cpu_exception.cc
SRC_CC += spec/x86_64/muen/kernel/thread_exception.cc
SRC_CC += spec/x86_64/muen/platform_support.cc
SRC_CC += spec/x86_64/muen/kernel/vm.cc
SRC_CC += spec/x86_64/muen/platform_services.cc
SRC_CC += spec/x86_64/muen/sinfo_instance.cc
SRC_CC += spec/x86_64/muen/timer.cc
SRC_CC += kernel/vm_thread_on.cc
SRC_CC += kernel/kernel.cc
SRC_CC += spec/x86/io_port_session_component.cc
SRC_CC += spec/x86/io_port_session_support.cc
SRC_CC += spec/x86_64/bios_data_area.cc
SRC_CC += spec/x86_64/cpu.cc
SRC_CC += spec/x86_64/fpu.cc
SRC_CC += spec/x86_64/kernel/cpu.cc
SRC_CC += spec/x86_64/kernel/cpu_context.cc
SRC_CC += spec/x86_64/kernel/pd.cc
SRC_CC += spec/x86_64/kernel/thread.cc
SRC_CC += spec/x86_64/kernel/thread.cc
SRC_CC += spec/x86_64/platform_support_common.cc
# include less specific configuration
include $(BASE_DIR)/../base-hw/lib/mk/core-hw.inc

3
repos/base-hw/lib/mk/spec/odroid_xu/core-hw.mk
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@ -4,6 +4,9 @@
# \date 2015-02-09
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/odroid_xu
# add C++ sources
SRC_CC += spec/arm/kernel/cpu_context.cc
SRC_CC += spec/arm_gic/pic.cc

1
repos/base-hw/lib/mk/spec/pbxa9/core-hw.mk
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@ -11,7 +11,6 @@ INC_DIR += $(REP_DIR)/src/core/spec/pl011
# add C++ sources
SRC_CC += platform_services.cc
SRC_CC += spec/pbxa9/board.cc
NR_OF_CPUS = 1

1
repos/base-hw/lib/mk/spec/trustzone/core-hw-trustzone.mk
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@ -1 +0,0 @@
LIBS += core-hw-trustzone_on

11
repos/base-hw/lib/mk/spec/usb_armory/core-hw-trustzone_on.mk
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@ -1,11 +0,0 @@
#
# \brief Build config for parts of core that depend on Trustzone status
# \author Martin Stein
# \date 2015-10-30
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/usb_armory
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/imx53/core-hw-trustzone_on.inc

11
repos/base-hw/lib/mk/spec/imx53/core-hw-trustzone_on.inc → repos/base-hw/lib/mk/spec/usb_armory/core-hw.mk
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@ -1,11 +1,13 @@
#
# \brief Build config for parts of core that depend on Trustzone status
# \author Stefan Kalkowski
# \author Martin Stein
# \date 2012-10-24
# \date 2015-10-30
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/usb_armory
INC_DIR += $(REP_DIR)/src/core/spec/imx53
INC_DIR += $(REP_DIR)/src/core/spec/imx
INC_DIR += $(REP_DIR)/src/core/spec/arm_v7/trustzone
INC_DIR += $(REP_DIR)/src/core/spec/imx53/trustzone
@ -15,9 +17,12 @@ SRC_CC += kernel/vm_thread_on.cc
SRC_CC += spec/arm_v7/trustzone/kernel/vm.cc
SRC_CC += spec/arm_v7/vm_session_component.cc
SRC_CC += spec/arm_v7/trustzone/vm_session_component.cc
SRC_CC += spec/imx53/pic.cc
SRC_CC += spec/imx53/timer.cc
SRC_CC += spec/arm/cpu_context_trustzone.cc
# add assembly sources
SRC_S += spec/arm_v7/trustzone/mode_transition.s
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/imx53/core-hw.inc
include $(REP_DIR)/lib/mk/spec/cortex_a8/core-hw.inc

17
repos/base-hw/lib/mk/spec/x86_64/core-hw-muen_off.mk
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@ -1,17 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \date 2015-06-02
#
# add C++ sources
SRC_CC += kernel/vm_thread_off.cc
SRC_CC += spec/x86_64/pic.cc
SRC_CC += spec/x86_64/timer.cc
SRC_CC += spec/x86_64/kernel/cpu_exception.cc
SRC_CC += spec/x86_64/kernel/thread_exception.cc
SRC_CC += spec/x86_64/platform_support.cc
SRC_CC += spec/x86/platform_services.cc
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/x86_64/core-hw.inc

23
repos/base-hw/lib/mk/spec/x86_64/core-hw-muen_on.mk
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@ -1,23 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \date 2015-06-02
#
REQUIRES = muen
# add include paths
INC_DIR += $(REP_DIR)/src/core/spec/x86_64/muen
# add C++ sources
SRC_CC += spec/x86_64/muen/kernel/cpu_exception.cc
SRC_CC += spec/x86_64/muen/kernel/thread_exception.cc
SRC_CC += spec/x86_64/muen/platform_support.cc
SRC_CC += spec/x86_64/muen/kernel/vm.cc
SRC_CC += spec/x86_64/muen/platform_services.cc
SRC_CC += kernel/vm_thread_on.cc
LIBS += sinfo-muen
# include less specific configuration
include $(REP_DIR)/lib/mk/spec/x86_64/core-hw.inc

7
repos/base-hw/lib/mk/spec/x86_64/core-hw.mk
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@ -1,7 +0,0 @@
#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \date 2015-06-02
#
LIBS += core-hw-muen

7
repos/base-hw/lib/mk/spec/x86_pc/bootstrap-hw.mk Normal file
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@ -0,0 +1,7 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/x86_64
SRC_S += bootstrap/spec/x86_64/crt0.s
SRC_CC += bootstrap/spec/x86_64/platform.cc
SRC_S += bootstrap/spec/x86_64/crt0_translation_table.s
include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc

8
repos/base-hw/lib/mk/spec/x86_64/core-hw.inc → repos/base-hw/lib/mk/spec/x86_pc/core-hw.mk
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@ -13,6 +13,14 @@ SRC_S += spec/x86_64/mode_transition.s
SRC_S += spec/x86_64/crt0.s
# add C++ sources
SRC_CC += kernel/vm_thread_off.cc
SRC_CC += spec/x86_64/pic.cc
SRC_CC += spec/x86_64/timer.cc
SRC_CC += spec/x86_64/kernel/cpu_exception.cc
SRC_CC += spec/x86_64/kernel/thread_exception.cc
SRC_CC += spec/x86_64/platform_support.cc
SRC_CC += spec/x86/platform_services.cc
SRC_CC += kernel/kernel.cc
SRC_CC += spec/x86/io_port_session_component.cc
SRC_CC += spec/x86/io_port_session_support.cc

2
repos/base-hw/src/bootstrap/log.cc
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@ -22,7 +22,7 @@
#include <board.h>
using namespace Bootstrap;
using namespace Board;
using namespace Genode;
struct Buffer

2
repos/base-hw/src/bootstrap/platform.h
View File

@ -40,7 +40,7 @@ class Bootstrap::Platform
{
private:
struct Board : Genode::Board_base
struct Board
{
Memory_region_array early_ram_regions;
Memory_region_array late_ram_regions;

8
repos/base-hw/src/bootstrap/spec/arm/cortex_a9_mmu.cc
View File

@ -66,9 +66,7 @@ struct Scu : Genode::Mmio
struct Cpu3_way : Bitfield<12, 4> { };
};
using Memory_map = Hw::Cpu_memory_map<Bootstrap::CPU_MMIO_BASE>;
Scu() : Genode::Mmio(Memory_map::SCU_MMIO_BASE) { }
Scu() : Genode::Mmio(Board::Cpu_mmio::SCU_MMIO_BASE) { }
void invalidate()
{
@ -128,7 +126,7 @@ void Bootstrap::Platform::enable_mmu()
if (primary) {
Scu scu;
scu.invalidate();
Bootstrap::L2_cache l2_cache(Board::PL310_MMIO_BASE);
::Board::L2_cache l2_cache(::Board::PL310_MMIO_BASE);
l2_cache.disable();
l2_cache.invalidate();
scu.enable(Cpu::errata(Cpu::ARM_764369));
@ -146,7 +144,7 @@ void Bootstrap::Platform::enable_mmu()
data_cache_enabled.wait_for(NR_OF_CPUS);
if (primary) {
Bootstrap::L2_cache l2_cache(board.core_mmio.virt_addr(Board::PL310_MMIO_BASE));
::Board::L2_cache l2_cache(board.core_mmio.virt_addr(::Board::PL310_MMIO_BASE));
l2_cache.enable();
}

6
repos/base-hw/src/bootstrap/spec/arm/imx_tzic.cc
View File

@ -13,11 +13,11 @@
#include <board.h>
Hw::Pic::Pic() : Genode::Mmio(Genode::Board_base::IRQ_CONTROLLER_BASE)
Hw::Pic::Pic() : Genode::Mmio(Board::IRQ_CONTROLLER_BASE)
{
for (unsigned i = 0; i < NR_OF_IRQ; i++) {
write<Intsec::Nonsecure>(!Bootstrap::secure_irq(i), i);
if (!Bootstrap::secure_irq(i)) write<Priority>(0x80, i);
write<Intsec::Nonsecure>(!Board::secure_irq(i), i);
if (!Board::secure_irq(i)) write<Priority>(0x80, i);
write<Enclear::Clear_enable>(1, i);
}
write<Priomask::Mask>(0xff);

5
repos/base-hw/src/bootstrap/spec/arm/pic.cc
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@ -14,7 +14,6 @@
#include <spec/arm/pic.h>
#include <platform.h>
using Memory_map = Hw::Cpu_memory_map<Bootstrap::CPU_MMIO_BASE>;
using Bootstrap::Platform;
void Bootstrap::Pic::init_cpu_local()
@ -31,8 +30,8 @@ void Bootstrap::Pic::init_cpu_local()
Hw::Pic::Pic()
: _distr(Memory_map::IRQ_CONTROLLER_DISTR_BASE),
_cpui (Memory_map::IRQ_CONTROLLER_CPU_BASE),
: _distr(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE),
_cpui (Board::Cpu_mmio::IRQ_CONTROLLER_CPU_BASE),
_last_iar(Cpu_interface::Iar::Irq_id::bits(spurious_id)),
_max_irq(_distr.max_irq())
{

16
repos/base-hw/src/bootstrap/spec/arndale/board.h
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@ -14,23 +14,23 @@
#ifndef _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_
#include <drivers/board_base.h>
#include <drivers/uart_base.h>
#include <drivers/defs/arndale.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/cortex_a15.h>
#include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Bootstrap {
class L2_cache;
namespace Board {
using Serial = Genode::Exynos_uart_base;
using namespace Arndale;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = Genode::Board_base::UART_2_MMIO_BASE,
UART_CLOCK = Genode::Board_base::UART_2_CLOCK,
CPU_MMIO_BASE = Genode::Board_base::IRQ_CONTROLLER_BASE,
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
}

5
repos/base-hw/src/bootstrap/spec/arndale/pic.cc
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@ -15,7 +15,6 @@
#include <spec/arm/pic.h>
#include <platform.h>
using Memory_map = Hw::Cpu_memory_map<Bootstrap::CPU_MMIO_BASE>;
using Bootstrap::Platform;
void Bootstrap::Pic::init_cpu_local()
@ -42,8 +41,8 @@ void Bootstrap::Pic::init_cpu_local()
Hw::Pic::Pic()
: _distr(Memory_map::IRQ_CONTROLLER_DISTR_BASE),
_cpui(Memory_map::IRQ_CONTROLLER_CPU_BASE),
: _distr(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE),
_cpui (Board::Cpu_mmio::IRQ_CONTROLLER_CPU_BASE),
_last_iar(Cpu_interface::Iar::Irq_id::bits(spurious_id)),
_max_irq(_distr.max_irq())
{

4
repos/base-hw/src/bootstrap/spec/arndale/platform.cc
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@ -16,6 +16,8 @@
extern "C" void * _start_setup_stack; /* entrypoint for non-boot CPUs */
static unsigned char hyp_mode_stack[1024]; /* hypervisor mode's kernel stack */
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
@ -176,6 +178,6 @@ void Bootstrap::Platform::enable_mmu()
void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
{
*(void * volatile *)Genode::Board_base::IRAM_BASE = ip;
*(void * volatile *)Board::IRAM_BASE = ip;
asm volatile("dsb; sev;");
}

14
repos/base-hw/src/bootstrap/spec/imx53_qsb/board.h
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@ -14,23 +14,25 @@
#ifndef _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_
#include <drivers/board_base.h>
#include <drivers/uart_base.h>
#include <drivers/defs/imx53_qsb.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/imx_tzic.h>
#include <spec/arm/cortex_a8_page_table.h>
#include <spec/arm/cpu.h>
namespace Bootstrap {
using Hw::Pic;
using Serial = Genode::Imx_uart_base;
namespace Board {
using namespace Imx53_qsb;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = Genode::Board_base::UART_1_MMIO_BASE,
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* ignored value */
};
bool secure_irq(unsigned irq);
}
namespace Bootstrap { using Hw::Pic; }
#endif /* _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_ */

4
repos/base-hw/src/bootstrap/spec/imx53_qsb/platform.cc
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@ -14,7 +14,9 @@
#include <platform.h>
#include <spec/arm/imx_aipstz.h>
bool Bootstrap::secure_irq(unsigned i) { return true; }
using namespace Board;
bool Board::secure_irq(unsigned i) { return true; }
Bootstrap::Platform::Board::Board()

20
repos/base-hw/src/bootstrap/spec/imx53_qsb/platform_trustzone.cc
View File

@ -16,16 +16,16 @@
#include <spec/arm/imx_aipstz.h>
#include <spec/arm/imx_csu.h>
bool Bootstrap::secure_irq(unsigned i)
{
using Board = Genode::Board_base;
using namespace Board;
if (i == Board::EPIT_1_IRQ) return true;
if (i == Board::EPIT_2_IRQ) return true;
if (i == Board::I2C_2_IRQ) return true;
if (i == Board::I2C_3_IRQ) return true;
if (i >= Board::GPIO1_IRQL && i <= Board::GPIO4_IRQH) return true;
if (i >= Board::GPIO5_IRQL && i <= Board::GPIO7_IRQH) return true;
bool Board::secure_irq(unsigned i)
{
if (i == EPIT_1_IRQ) return true;
if (i == EPIT_2_IRQ) return true;
if (i == I2C_2_IRQ) return true;
if (i == I2C_3_IRQ) return true;
if (i >= GPIO1_IRQL && i <= GPIO4_IRQH) return true;
if (i >= GPIO5_IRQL && i <= GPIO7_IRQH) return true;
return false;
}
@ -51,5 +51,5 @@ Bootstrap::Platform::Board::Board()
Cpu::Nsacr::write(v);
/* configure central security unit */
Csu csu(Genode::Board_base::CSU_BASE, false, true, false, true);
Csu csu(CSU_BASE, false, true, false, true);
}

16
repos/base-hw/src/bootstrap/spec/odroid_xu/board.h
View File

@ -14,23 +14,23 @@
#ifndef _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_
#include <drivers/board_base.h>
#include <drivers/uart_base.h>
#include <drivers/defs/odroid_xu.h>
#include <drivers/uart/exynos.h>
#include <hw/spec/arm/cortex_a15.h>
#include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Bootstrap {
class L2_cache;
namespace Board {
using Serial = Genode::Exynos_uart_base;
using namespace Odroid_xu;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
using Serial = Genode::Exynos_uart;
enum {
UART_BASE = Genode::Board_base::UART_2_MMIO_BASE,
UART_CLOCK = Genode::Board_base::UART_2_CLOCK,
CPU_MMIO_BASE = Genode::Board_base::IRQ_CONTROLLER_BASE,
UART_BASE = UART_2_MMIO_BASE,
UART_CLOCK = UART_2_CLOCK,
};
}

2
repos/base-hw/src/bootstrap/spec/odroid_xu/platform.cc
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@ -13,6 +13,8 @@
#include <platform.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
core_mmio(Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },

21
repos/base-hw/src/bootstrap/spec/panda/board.h
View File

@ -14,8 +14,8 @@
#ifndef _SRC__BOOTSTRAP__SPEC__PANDA__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__PANDA__BOARD_H_
#include <drivers/board_base.h>
#include <drivers/uart_base.h>
#include <drivers/defs/panda.h>
#include <drivers/uart/tl16c750.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/panda_trustzone_firmware.h>
@ -24,20 +24,21 @@
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Bootstrap {
namespace Board {
class L2_cache;
using Serial = Genode::Tl16c750_base;
using namespace Panda;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Tl16c750_uart;
enum {
UART_BASE = Genode::Board_base::TL16C750_3_MMIO_BASE,
UART_CLOCK = Genode::Board_base::TL16C750_CLOCK,
CPU_MMIO_BASE = Genode::Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
UART_BASE = TL16C750_3_MMIO_BASE,
UART_CLOCK = TL16C750_CLOCK,
};
struct Actlr;
}
namespace Bootstrap { struct Actlr; }
struct Bootstrap::Actlr
{
@ -46,7 +47,7 @@ struct Bootstrap::Actlr
};
class Bootstrap::L2_cache : Hw::Pl310
class Board::L2_cache : Hw::Pl310
{
private:

5
repos/base-hw/src/bootstrap/spec/panda/platform.cc
View File

@ -13,6 +13,8 @@
#include <platform.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE }),
core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
@ -36,8 +38,7 @@ void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
struct Aux_core_boot_1 : Register<0x804, 32> { };
Wakeup_generator(void * const ip)
: Mmio(Genode::Board_base::CORTEX_A9_WUGEN_MMIO_BASE)
Wakeup_generator(void * const ip) : Mmio(CORTEX_A9_WUGEN_MMIO_BASE)
{
write<Aux_core_boot_1>((addr_t)ip);
write<Aux_core_boot_0::Cpu1_status>(1);

17
repos/base-hw/src/bootstrap/spec/pbxa9/board.h
View File

@ -14,8 +14,8 @@
#ifndef _SRC__BOOTSTRAP__SPEC__PBXA9__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__PBXA9__BOARD_H_
#include <drivers/board_base.h>
#include <drivers/uart_base.h>
#include <drivers/defs/pbxa9.h>
#include <drivers/uart/pl011.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
@ -24,14 +24,17 @@
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Bootstrap {
namespace Board {
using namespace Pbxa9;
using L2_cache = Hw::Pl310;
using Serial = Genode::Pl011_base;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Pl011_uart;
enum {
UART_BASE = Genode::Board_base::PL011_0_MMIO_BASE,
UART_CLOCK = Genode::Board_base::PL011_0_CLOCK,
CPU_MMIO_BASE = Genode::Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
UART_BASE = PL011_0_MMIO_BASE,
UART_CLOCK = PL011_0_CLOCK,
};
}

17
repos/base-hw/src/bootstrap/spec/pbxa9/platform.cc
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@ -14,15 +14,17 @@
/* bootstrap includes */
#include <platform.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE, RAM_0_SIZE },
Memory_region { RAM_1_BASE, RAM_1_SIZE }),
core_mmio(Memory_region { Board::CORTEX_A9_PRIVATE_MEM_BASE,
Board::CORTEX_A9_PRIVATE_MEM_SIZE },
Memory_region { Board::PL011_0_MMIO_BASE,
Board::PL011_0_MMIO_SIZE },
Memory_region { Board::PL310_MMIO_BASE,
Board::PL310_MMIO_SIZE }) { }
core_mmio(Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
CORTEX_A9_PRIVATE_MEM_SIZE },
Memory_region { PL011_0_MMIO_BASE,
PL011_0_MMIO_SIZE },
Memory_region { PL310_MMIO_BASE,
PL310_MMIO_SIZE }) { }
bool Bootstrap::Cpu::errata(Bootstrap::Cpu::Errata err) {
@ -42,8 +44,7 @@ void Bootstrap::Cpu::wake_up_all_cpus(void * const ip)
struct Flagsset : Register<0x30, 32> { };
struct Flagsclr : Register<0x34, 32> { };
System_control(void * const ip)
: Mmio(Genode::Board_base::SYSTEM_CONTROL_MMIO_BASE)
System_control(void * const ip) : Mmio(SYSTEM_CONTROL_MMIO_BASE)
{
write<Flagsclr>(~0UL);
write<Flagsset>(reinterpret_cast<Flagsset::access_t>(ip));

4
repos/base-hw/src/bootstrap/spec/riscv/board.h
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@ -17,12 +17,12 @@
#include <hw/spec/riscv/page_table.h>
#include <hw/spec/riscv/uart.h>
namespace Genode { struct Board_base {}; }
namespace Bootstrap {
struct Cpu {};
struct Pic {};
}
namespace Board {
enum { UART_BASE, UART_CLOCK };
struct Serial : Hw::Riscv_uart {
Serial(unsigned, unsigned, unsigned) {} };

16
repos/base-hw/src/bootstrap/spec/rpi/board.h
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@ -14,23 +14,23 @@
#ifndef _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__RPI__BOARD_H_
#include <drivers/board_base.h>
#include <drivers/uart_base.h>
#include <drivers/defs/rpi.h>
#include <drivers/uart/pl011.h>
#include <hw/spec/arm/page_table.h>
#include <spec/arm/cpu.h>
namespace Bootstrap {
using Serial = Genode::Pl011_base;
namespace Board {
using Serial = Genode::Pl011_uart;
enum {
UART_BASE = Genode::Board_base::PL011_0_MMIO_BASE,
UART_CLOCK = Genode::Board_base::PL011_0_CLOCK,
UART_BASE = Rpi::PL011_0_MMIO_BASE,
UART_CLOCK = Rpi::PL011_0_CLOCK,
};
struct Pic {};
}
namespace Bootstrap { struct Pic {}; }
constexpr unsigned Hw::Page_table::Descriptor_base::_device_tex() {
return 0; }

2
repos/base-hw/src/bootstrap/spec/rpi/platform.cc
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@ -15,6 +15,8 @@
#include <hw/assert.h>
#include <platform.h>
using namespace Rpi;
/**
* Leave out the first page (being 0x0) from bootstraps RAM allocator,
* some code does not feel happy with addresses being zero

14
repos/base-hw/src/bootstrap/spec/usb_armory/board.h
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@ -14,19 +14,21 @@
#ifndef _SRC__BOOTSTRAP__SPEC__USB_ARMORY__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__USB_ARMORY__BOARD_H_
#include <drivers/board_base.h>
#include <drivers/uart_base.h>
#include <drivers/defs/usb_armory.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/imx_tzic.h>
#include <spec/arm/cortex_a8_page_table.h>
#include <spec/arm/cpu.h>
namespace Bootstrap {
using Hw::Pic;
using Serial = Genode::Imx_uart_base;
namespace Bootstrap { using Hw::Pic; }
namespace Board {
using namespace Usb_armory;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = Genode::Board_base::UART_1_MMIO_BASE,
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* ignored value */
};

14
repos/base-hw/src/bootstrap/spec/usb_armory/platform.cc
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@ -16,13 +16,13 @@
#include <spec/arm/imx_aipstz.h>
#include <spec/arm/imx_csu.h>
bool Bootstrap::secure_irq(unsigned i)
{
using Board = Genode::Board_base;
using namespace Board;
if (i == Board::EPIT_1_IRQ) return true;
if (i == Board::EPIT_2_IRQ) return true;
if (i == Board::SDHC_IRQ) return true;
bool Board::secure_irq(unsigned i)
{
if (i == EPIT_1_IRQ) return true;
if (i == EPIT_2_IRQ) return true;
if (i == SDHC_IRQ) return true;
return false;
}
@ -48,5 +48,5 @@ Bootstrap::Platform::Board::Board()
Cpu::Nsacr::write(v);
/* configure central security unit */
Csu csu(Genode::Board_base::CSU_BASE, true, false, true, false);
Csu csu(CSU_BASE, true, false, true, false);
}

15
repos/base-hw/src/bootstrap/spec/wand_quad/board.h
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@ -14,8 +14,8 @@
#ifndef _SRC__BOOTSTRAP__SPEC__WAND_QUAD__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__WAND_QUAD__BOARD_H_
#include <drivers/board_base.h>
#include <drivers/uart_base.h>
#include <drivers/defs/wand_quad.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
@ -24,14 +24,17 @@
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Bootstrap {
namespace Board {
using namespace Wand_quad;
using L2_cache = Hw::Pl310;
using Serial = Genode::Imx_uart_base;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = Genode::Board_base::UART_1_MMIO_BASE,
UART_BASE = UART_1_MMIO_BASE,
UART_CLOCK = 0, /* dummy value, not used */
CPU_MMIO_BASE = Genode::Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
};
}

5
repos/base-hw/src/bootstrap/spec/wand_quad/platform.cc
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@ -16,6 +16,8 @@
#include <platform.h>
#include <spec/arm/imx_aipstz.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM0_BASE, RAM0_SIZE }),
core_mmio(Memory_region { UART_1_MMIO_BASE,
@ -52,8 +54,7 @@ void Bootstrap::Cpu::wake_up_all_cpus(void * const entry)
struct Gpr5 : Register<0x30, 32> {}; /* ep core 2 */
struct Gpr7 : Register<0x38, 32> {}; /* ep core 3 */
Src(void * const entry)
: Genode::Mmio(Genode::Board_base::SRC_MMIO_BASE)
Src(void * const entry) : Genode::Mmio(SRC_MMIO_BASE)
{
write<Gpr3>((Gpr3::access_t)entry);
write<Gpr5>((Gpr5::access_t)entry);

12
repos/base-hw/src/bootstrap/spec/x86_64/board.h
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@ -14,26 +14,24 @@
#ifndef _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_
#include <drivers/uart_base.h>
#include <drivers/uart/x86_pc.h>
#include <hw/spec/x86_64/page_table.h>
#include <hw/spec/x86_64/cpu.h>
#include <hw/spec/x86_64/x86_64.h>
namespace Genode { struct Board_base {}; }
namespace Bootstrap {
struct Serial;
struct Pic {};
using Cpu = Hw::X86_64_cpu;
}
namespace Board {
struct Serial;
enum Dummies { UART_BASE, UART_CLOCK };
}
struct Bootstrap::Serial : Genode::X86_uart_base
struct Board::Serial : Genode::X86_uart
{
Serial(Genode::addr_t, Genode::size_t, unsigned);
};

4
repos/base-hw/src/bootstrap/spec/x86_64/platform.cc
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@ -74,5 +74,5 @@ void Bootstrap::Platform::enable_mmu() {
addr_t Bios_data_area::_mmio_base_virt() { return 0x1ff000; }
Bootstrap::Serial::Serial(addr_t, size_t, unsigned baudrate)
:X86_uart_base(Bios_data_area::singleton()->serial_port(), 0, baudrate) {}
Board::Serial::Serial(addr_t, size_t, unsigned baudrate)
:X86_uart(Bios_data_area::singleton()->serial_port(), 0, baudrate) {}

4
repos/base-hw/src/bootstrap/spec/x86_64/platform_muen.cc
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@ -46,5 +46,5 @@ void Bootstrap::Platform::enable_mmu() {
Cpu::Cr3::write(Cpu::Cr3::Pdb::masked((addr_t)core_pd->table_base)); }
Bootstrap::Serial::Serial(addr_t, size_t, unsigned baudrate)
:X86_uart_base(COM1_PORT, 0, baudrate) {}
Board::Serial::Serial(Genode::addr_t, Genode::size_t, unsigned baudrate)
:X86_uart(COM1_PORT, 0, baudrate) {}

14
repos/base-hw/src/bootstrap/spec/zynq/board.h
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@ -14,8 +14,8 @@
#ifndef _SRC__BOOTSTRAP__SPEC__ZYNQ__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__ZYNQ__BOARD_H_
#include <drivers/board_base.h>
#include <drivers/uart_base.h>
#include <drivers/defs/zynq_qemu.h>
#include <drivers/uart/xilinx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
@ -24,14 +24,14 @@
#include <spec/arm/cpu.h>
#include <spec/arm/pic.h>
namespace Bootstrap {
namespace Board {
using namespace Zynq_qemu;
using L2_cache = Hw::Pl310;
using Serial = Genode::Xilinx_uartps_base;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Xilinx_uart;
enum {
UART_BASE = Genode::Board_base::UART_0_MMIO_BASE,
UART_CLOCK = Genode::Board_base::UART_CLOCK,
CPU_MMIO_BASE = Genode::Board_base::CORTEX_A9_PRIVATE_MEM_BASE,
UART_BASE = UART_0_MMIO_BASE,
};
}

2
repos/base-hw/src/bootstrap/spec/zynq/platform.cc
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@ -15,6 +15,8 @@
/* core includes */
#include <platform.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
RAM_0_SIZE - 0x1000 }),

4
repos/base-hw/src/core/kernel/init.cc
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@ -34,10 +34,6 @@ Pd * Kernel::core_pd() {
Pic * Kernel::pic() { return unmanaged_singleton<Pic>(); }
Genode::Board & Kernel::board() {
return *unmanaged_singleton<Genode::Board>(); }
extern "C" void _start() __attribute__((section(".text.crt0")));
/**

6
repos/base-hw/src/core/kernel/kernel.h
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@ -16,7 +16,6 @@
#define _CORE__KERNEL__KERNEL_H_
#include <pic.h>
#include <board.h>
/**
* Main routine of every kernel pass
@ -28,9 +27,8 @@ namespace Kernel {
class Pd;
Pd * core_pd();
Pic * pic();
Genode::Board & board();
Pd * core_pd();
Pic * pic();
}
#endif /* _CORE__KERNEL__KERNEL_H_ */

6
repos/base-hw/src/core/spec/arm/cpu_support.h
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@ -12,8 +12,8 @@
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__ARM__CPU_H_
#define _CORE__SPEC__ARM__CPU_H_
#ifndef _CORE__SPEC__ARM__CPU_SUPPORT_H_
#define _CORE__SPEC__ARM__CPU_SUPPORT_H_
/* Genode includes */
#include <util/register.h>
@ -256,4 +256,4 @@ struct Genode::Arm_cpu : public Hw::Arm_cpu
static unsigned primary_id() { return 0; }
};
#endif /* _CORE__SPEC__ARM__CPU_H_ */
#endif /* _CORE__SPEC__ARM__CPU_SUPPORT_H_ */

4
repos/base-hw/src/core/spec/arm_gic/pic.cc
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@ -19,7 +19,7 @@
using namespace Genode;
Hw::Pic::Pic()
: _distr(Platform::mmio_to_virt(Board::IRQ_CONTROLLER_DISTR_BASE)),
_cpui (Platform::mmio_to_virt(Board::IRQ_CONTROLLER_CPU_BASE)),
: _distr(Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE)),
_cpui (Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_CPU_BASE)),
_last_iar(Cpu_interface::Iar::Irq_id::bits(spurious_id)),
_max_irq(_distr.max_irq()) { }

8
repos/base-hw/src/core/spec/arm_v7/virtualization/kernel/vm.cc
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@ -73,10 +73,10 @@ struct Kernel::Virtual_pic : Genode::Mmio
template <unsigned SLOT>
struct Gich_lr : Register<0x100 + SLOT*4, 32> { };
Vm_irq irq = Genode::Board::VT_MAINTAINANCE_IRQ;
Vm_irq irq = Board::VT_MAINTAINANCE_IRQ;
Virtual_pic()
: Genode::Mmio(Genode::Platform::mmio_to_virt(Genode::Board::IRQ_CONTROLLER_VT_CTRL_BASE)) { }
: Genode::Mmio(Genode::Platform::mmio_to_virt(Board::IRQ_CONTROLLER_VT_CTRL_BASE)) { }
static Virtual_pic& pic()
{
@ -124,7 +124,7 @@ struct Kernel::Virtual_pic : Genode::Mmio
struct Kernel::Virtual_timer
{
Vm_irq irq = Genode::Board::VT_TIMER_IRQ;
Vm_irq irq = Board::VT_TIMER_IRQ;
/**
* Return virtual timer object of currently executing cpu
@ -213,7 +213,7 @@ void Kernel::Vm::exception(unsigned const cpu_id)
switch(_state->cpu_exception) {
case Genode::Cpu_state::INTERRUPT_REQUEST:
case Genode::Cpu_state::FAST_INTERRUPT_REQUEST:
_state->gic_irq = Genode::Board_base::VT_MAINTAINANCE_IRQ;
_state->gic_irq = Board::VT_MAINTAINANCE_IRQ;
_interrupt(cpu_id);
break;
default:

29
repos/base-hw/src/core/spec/arndale/board.h Normal file
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@ -0,0 +1,29 @@
/*
* \brief Board driver for core
* \author Stefan Kalkowski
* \date 2017-04-27
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__ARNDALE__BOARD_H_
#define _CORE__SPEC__ARNDALE__BOARD_H_
/* base includes */
#include <drivers/defs/arndale.h>
#include <hw/spec/arm/cortex_a15.h>
namespace Board {
using namespace Arndale;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
static constexpr bool SMP = true;
}
#endif /* _CORE__SPEC__ARNDALE__BOARD_H_ */

1
repos/base-hw/src/core/spec/arndale/platform_services.cc
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@ -16,6 +16,7 @@
#include <base/heap.h>
/* core includes */
#include <platform.h>
#include <platform_services.h>
#include <core_parent.h> /* for 'Core_service' type */
#include <map_local.h>

41
repos/base-hw/src/core/spec/cortex_a15/board_support.h
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@ -1,41 +0,0 @@
/*
* \brief Board driver definitions common to Cortex A15 SoCs
* \author Stefan Kalkowski
* \date 2015-02-09
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__CORTEX_A15__BOARD_SUPPORT_H_
#define _CORE__SPEC__CORTEX_A15__BOARD_SUPPORT_H_
/* core includes */
#include <drivers/board_base.h>
namespace Cortex_a15
{
class Board_base : public Genode::Board_base
{
private:
using Base = Genode::Board_base;
public:
enum
{
/* interrupt controller */
IRQ_CONTROLLER_DISTR_BASE = Base::IRQ_CONTROLLER_BASE + 0x1000,
IRQ_CONTROLLER_DISTR_SIZE = 0x1000,
IRQ_CONTROLLER_CPU_BASE = Base::IRQ_CONTROLLER_BASE + 0x2000,
IRQ_CONTROLLER_CPU_SIZE = 0x2000,
};
};
}
#endif /* _CORE__SPEC__CORTEX_A15__BOARD_SUPPORT_H_ */

9
repos/base-hw/src/core/spec/cortex_a9/board.cc
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@ -14,7 +14,10 @@
#include <board.h>
#include <platform.h>
using namespace Genode;
Board::L2_cache & Board::l2_cache()
{
using namespace Genode;
Cortex_a9::Board::Board()
: _l2_cache(Platform::mmio_to_virt(Board_base::PL310_MMIO_BASE)) {}
static L2_cache cache(Platform::mmio_to_virt(Board::PL310_MMIO_BASE));
return cache;
}

66
repos/base-hw/src/core/spec/cortex_a9/board_support.h
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@ -1,66 +0,0 @@
/*
* \brief Board driver definitions common to Cortex A9 SoCs
* \author Stefan Kalkowski
* \date 2015-02-09
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__CORTEX_A9__BOARD_SUPPORT_H_
#define _CORE__SPEC__CORTEX_A9__BOARD_SUPPORT_H_
/* core includes */
#include <drivers/board_base.h>
#include <hw/spec/arm/pl310.h>
namespace Cortex_a9 { class Board; }
class Cortex_a9::Board : public Genode::Board_base
{
public:
using L2_cache = Hw::Pl310;
static constexpr bool SMP = true;
enum Errata {
ARM_754322,
ARM_764369,
ARM_775420,
PL310_588369,
PL310_727915,
PL310_769419,
};
enum {
/* interrupt controller */
IRQ_CONTROLLER_DISTR_BASE = CORTEX_A9_PRIVATE_MEM_BASE + 0x1000,
IRQ_CONTROLLER_DISTR_SIZE = 0x1000,
IRQ_CONTROLLER_CPU_BASE = CORTEX_A9_PRIVATE_MEM_BASE + 0x100,
IRQ_CONTROLLER_CPU_SIZE = 0x100,
/* timer */
PRIVATE_TIMER_MMIO_BASE = CORTEX_A9_PRIVATE_MEM_BASE + 0x600,
PRIVATE_TIMER_MMIO_SIZE = 0x10,
PRIVATE_TIMER_IRQ = 29,
};
Board();
L2_cache & l2_cache() { return _l2_cache; }
void init() { }
void wake_up_all_cpus(void * const ip);
bool errata(Errata);
protected:
L2_cache _l2_cache;
};
#endif /* _CORE__SPEC__CORTEX_A9__BOARD_SUPPORT_H_ */

6
repos/base-hw/src/core/spec/cortex_a9/cpu.h
View File

@ -80,7 +80,7 @@ class Genode::Cpu : public Arm_v7_cpu
void clean_invalidate_data_cache()
{
clean_invalidate_inner_data_cache();
Kernel::board().l2_cache().clean_invalidate();
Board::l2_cache().clean_invalidate();
}
/**
@ -89,7 +89,7 @@ class Genode::Cpu : public Arm_v7_cpu
void invalidate_data_cache()
{
invalidate_inner_data_cache();
Kernel::board().l2_cache().invalidate();
Board::l2_cache().invalidate();
}
/**
@ -100,7 +100,7 @@ class Genode::Cpu : public Arm_v7_cpu
size_t const size)
{
Arm_cpu::clean_invalidate_data_cache_by_virt_region(base, size);
Kernel::board().l2_cache().clean_invalidate();
Board::l2_cache().clean_invalidate();
}
static unsigned executing_id() { return Mpidr::Aff_0::get(Mpidr::read()); }

10
repos/base-hw/src/core/spec/cortex_a9/timer.cc
View File

@ -14,14 +14,18 @@
#include <platform.h>
#include <timer.h>
Genode::Timer::Timer()
: Genode::Mmio(Genode::Platform::mmio_to_virt(Board::PRIVATE_TIMER_MMIO_BASE))
using Genode::Timer;
using Genode::Mmio;
using Genode::Platform;
Timer::Timer()
: Mmio(Platform::mmio_to_virt(Board::Cpu_mmio::PRIVATE_TIMER_MMIO_BASE))
{
write<Control::Timer_enable>(0);
}
void Genode::Timer::start_one_shot(time_t const tics, unsigned const)
void Timer::start_one_shot(time_t const tics, unsigned const)
{
enum { PRESCALER = Board::CORTEX_A9_PRIVATE_TIMER_DIV - 1 };

2
repos/base-hw/src/core/spec/cortex_a9/timer.h
View File

@ -76,7 +76,7 @@ class Genode::Timer : public Mmio
* Return kernel name of timer interrupt
*/
static unsigned interrupt_id(unsigned const) {
return Board::PRIVATE_TIMER_IRQ; }
return Board::Cpu_mmio::PRIVATE_TIMER_IRQ; }
/**
* Start single timeout run

43
repos/base-hw/src/core/spec/exynos5/board.h
View File

@ -1,43 +0,0 @@
/*
* \brief Board driver for core
* \author Martin Stein
* \author Stefan Kalkowski
* \date 2012-04-23
*/
/*
* Copyright (C) 2012-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__EXYNOS5__BOARD_H_
#define _CORE__SPEC__EXYNOS5__BOARD_H_
/* core includes */
#include <spec/cortex_a15/board_support.h>
namespace Genode
{
class Board : public Cortex_a15::Board_base
{
public:
static void init() { }
/**
* Tell secondary CPUs to start execution from instr. pointer 'ip'
*/
static void wake_up_all_cpus(void * const ip)
{
*(void * volatile *)IRAM_BASE = ip;
asm volatile("dsb\n"
"sev\n");
}
static constexpr bool SMP = true;
};
}
#endif /* _CORE__SPEC__EXYNOS5__BOARD_H_ */

8
repos/base-hw/src/core/spec/exynos5/serial.h
View File

@ -20,14 +20,14 @@
#include <platform.h>
/* Genode includes */
#include <drivers/uart_base.h>
#include <drivers/uart/exynos.h>
namespace Genode
{
/**
* Serial output driver for core
*/
class Serial : public Exynos_uart_base
class Serial : public Exynos_uart
{
public:
@ -38,8 +38,8 @@ namespace Genode
*/
Serial(unsigned const baud_rate)
:
Exynos_uart_base(Platform::mmio_to_virt(Board::UART_2_MMIO_BASE),
Board::UART_2_CLOCK, baud_rate)
Exynos_uart(Platform::mmio_to_virt(Board::UART_2_MMIO_BASE),
Board::UART_2_CLOCK, baud_rate)
{ }
};
}

27
repos/base-hw/src/core/spec/exynos5/timer.cc Normal file
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@ -0,0 +1,27 @@
/*
* \brief Timer driver for core
* \author Martin stein
* \date 2013-01-10
*/
/*
* Copyright (C) 2013-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <platform.h>
#include <timer.h>
Genode::Timer::Timer()
: Mmio(Platform::mmio_to_virt(Board::MCT_MMIO_BASE)),
_tics_per_ms(_calc_tics_per_ms(Board::MCT_CLOCK))
{
Mct_cfg::access_t mct_cfg = 0;
Mct_cfg::Prescaler::set(mct_cfg, PRESCALER);
Mct_cfg::Div_mux::set(mct_cfg, DIV_MUX);
write<Mct_cfg>(mct_cfg);
write<L0_int_enb>(L0_int_enb::Frceie::bits(1));
write<L1_int_enb>(L1_int_enb::Frceie::bits(1));
}

17
repos/base-hw/src/core/spec/exynos5/timer.h
View File

@ -19,7 +19,6 @@
/* core include */
#include <board.h>
#include <platform.h>
/* Genode includes */
#include <util/mmio.h>
@ -203,21 +202,7 @@ class Genode::Timer : public Mmio
}
}
/**
* Constructor
*/
Timer()
:
Mmio(Platform::mmio_to_virt(Board::MCT_MMIO_BASE)),
_tics_per_ms(_calc_tics_per_ms(Board::MCT_CLOCK))
{
Mct_cfg::access_t mct_cfg = 0;
Mct_cfg::Prescaler::set(mct_cfg, PRESCALER);
Mct_cfg::Div_mux::set(mct_cfg, DIV_MUX);
write<Mct_cfg>(mct_cfg);
write<L0_int_enb>(L0_int_enb::Frceie::bits(1));
write<L1_int_enb>(L1_int_enb::Frceie::bits(1));
}
Timer();
/**
* Raise interrupt of CPU 'cpu' once after timeout 'tics'

6
repos/base-hw/src/core/spec/imx/serial.h
View File

@ -19,19 +19,19 @@
#include <platform.h>
/* Genode includes */
#include <drivers/uart_base.h>
#include <drivers/uart/imx.h>
namespace Genode
{
/**
* Serial output driver for core
*/
class Serial : public Imx_uart_base
class Serial : public Imx_uart
{
public:
Serial(unsigned baudrate)
: Imx_uart_base(Platform::mmio_to_virt(Board::UART_1_MMIO_BASE),
: Imx_uart(Platform::mmio_to_virt(Board::UART_1_MMIO_BASE),
/* ignored clock rate */ 0, baudrate) { }
};
}

20
repos/base-hw/src/core/spec/imx53/timer.cc Normal file
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@ -0,0 +1,20 @@
/*
* \brief Timer implementation for core
* \author Stefan Kalkowski
* \date 2017-05-10
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <board.h>
#include <timer.h>
#include <platform.h>
Genode::Timer::Timer()
: Genode::Mmio(Genode::Platform::mmio_to_virt(Board::EPIT_1_MMIO_BASE)) { }

3
repos/base-hw/src/core/spec/imx53/timer.h
View File

@ -22,7 +22,6 @@
/* core includes */
#include <board.h>
#include <platform.h>
namespace Genode { class Timer; }
@ -136,7 +135,7 @@ class Genode::Timer : public Mmio
return Board::EPIT_1_IRQ;
}
Timer() : Mmio(Platform::mmio_to_virt(Board::EPIT_1_MMIO_BASE)) { }
Timer();
/**
* Start single timeout run

15
repos/base-hw/src/core/spec/imx53/board.h → repos/base-hw/src/core/spec/imx53_qsb/board.h
View File

@ -12,13 +12,14 @@
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__IMX53__BOARD_H_
#define _CORE__SPEC__IMX53__BOARD_H_
#ifndef _CORE__SPEC__IMX53_QSB__BOARD_H_
#define _CORE__SPEC__IMX53_QSB__BOARD_H_
#include <drivers/board_base.h>
#include <drivers/defs/imx53_qsb.h>
namespace Genode { struct Board; }
namespace Board {
using namespace Imx53_qsb;
static constexpr bool SMP = false;
}
struct Genode::Board : Genode::Board_base { static constexpr bool SMP = false; };
#endif /* _CORE__SPEC__IMX53__BOARD_H_ */
#endif /* _CORE__SPEC__IMX53_QSB__BOARD_H_ */

23
repos/base-hw/src/core/spec/imx6/board.h
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@ -1,23 +0,0 @@
/*
* \brief Board driver
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2014-02-25
*/
/*
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__IMX6__BOARD_H_
#define _CORE__SPEC__IMX6__BOARD_H_
/* core includes */
#include <spec/cortex_a9/board_support.h>
namespace Genode { using Board = Cortex_a9::Board; }
#endif /* _CORE__SPEC__IMX6__BOARD_H_ */

29
repos/base-hw/src/core/spec/odroid_xu/board.h Normal file
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@ -0,0 +1,29 @@
/*
* \brief Board driver for core
* \author Stefan Kalkowski
* \date 2017-04-27
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__ODROID_XU__BOARD_H_
#define _CORE__SPEC__ODROID_XU__BOARD_H_
/* base includes */
#include <drivers/defs/odroid_xu.h>
#include <hw/spec/arm/cortex_a15.h>
namespace Board {
using namespace Odroid_xu;
using Cpu_mmio = Hw::Cortex_a15_mmio<IRQ_CONTROLLER_BASE>;
static constexpr bool SMP = true;
}
#endif /* _CORE__SPEC__ODROID_XU__BOARD_H_ */

64
repos/base-hw/src/core/spec/panda/board.h
View File

@ -15,48 +15,46 @@
#ifndef _CORE__SPEC__PANDA__BOARD_H_
#define _CORE__SPEC__PANDA__BOARD_H_
/* base includes */
#include <drivers/defs/panda.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/panda_trustzone_firmware.h>
#include <spec/cortex_a9/board_support.h>
namespace Genode { class Board; }
namespace Board {
using namespace Panda;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
class Genode::Board : public Cortex_a9::Board
{
public:
static constexpr bool SMP = true;
using Base = Cortex_a9::Board;
class L2_cache : public Hw::Pl310
{
private:
class L2_cache : public Base::L2_cache
{
private:
unsigned long _debug_value()
{
Debug::access_t v = 0;
Debug::Dwb::set(v, 1);
Debug::Dcl::set(v, 1);
return v;
}
unsigned long _debug_value()
{
Debug::access_t v = 0;
Debug::Dwb::set(v, 1);
Debug::Dcl::set(v, 1);
return v;
}
public:
public:
L2_cache(Genode::addr_t mmio) : Hw::Pl310(mmio) { }
L2_cache(Genode::addr_t mmio) : Base::L2_cache(mmio) { }
void clean_invalidate()
{
using namespace Hw;
call_panda_firmware(L2_CACHE_SET_DEBUG_REG, _debug_value());
Pl310::clean_invalidate();
call_panda_firmware(L2_CACHE_SET_DEBUG_REG, 0);
}
};
void clean_invalidate()
{
using namespace Hw;
call_panda_firmware(L2_CACHE_SET_DEBUG_REG, _debug_value());
Base::L2_cache::clean_invalidate();
call_panda_firmware(L2_CACHE_SET_DEBUG_REG, 0);
}
};
L2_cache & l2_cache() { return _l2_cache; }
private:
L2_cache _l2_cache { Base::l2_cache().base() };
};
L2_cache & l2_cache();
}
#endif /* _CORE__SPEC__PANDA__BOARD_H_ */

45
repos/base-hw/src/core/spec/pbxa9/board.cc
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@ -1,45 +0,0 @@
/*
* \brief Board implementation specific to PBXA9
* \author Stefan Kalkowski
* \date 2016-01-07
*/
/*
* Copyright (C) 2016-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <util/mmio.h>
#include <board.h>
#include <kernel/kernel.h>
bool Cortex_a9::Board::errata(Cortex_a9::Board::Errata err) {
return false; }
void Cortex_a9::Board::wake_up_all_cpus(void * const ip)
{
/**
* set the entrypoint for the other CPUs via the flags register
* of the system control registers. ARMs boot monitor code will
* read out this register and jump to it after the cpu received
* an interrupt
*/
struct System_control : Genode::Mmio
{
struct Flagsset : Register<0x30, 32> { };
struct Flagsclr : Register<0x34, 32> { };
System_control(void * const ip)
: Mmio(SYSTEM_CONTROL_MMIO_BASE)
{
write<Flagsclr>(~0UL);
write<Flagsset>(reinterpret_cast<Flagsset::access_t>(ip));
}
} sc(ip);
/* send an IPI to all other cpus */
Kernel::pic()->send_ipi();
}

18
repos/base-hw/src/core/spec/pbxa9/board.h
View File

@ -14,12 +14,20 @@
#ifndef _CORE__SPEC__PBXA9__BOARD_H_
#define _CORE__SPEC__PBXA9__BOARD_H_
/* core includes */
#include <spec/cortex_a9/board_support.h>
/* base includes */
#include <drivers/defs/pbxa9.h>
namespace Genode
{
using Board = Cortex_a9::Board;
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Board {
using namespace Pbxa9;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
static constexpr bool SMP = true;
L2_cache & l2_cache();
}
#endif /* _CORE__SPEC__PBXA9__BOARD_H_ */

6
repos/base-hw/src/core/spec/pl011/serial.h
View File

@ -19,12 +19,12 @@
#include <platform.h>
/* Genode includes */
#include <drivers/uart_base.h>
#include <drivers/uart/pl011.h>
namespace Genode { class Serial; }
class Genode::Serial : public Pl011_base
class Genode::Serial : public Pl011_uart
{
public:
@ -35,7 +35,7 @@ class Genode::Serial : public Pl011_base
*/
Serial(unsigned const baud_rate)
:
Pl011_base(Platform::mmio_to_virt(Board::PL011_0_MMIO_BASE),
Pl011_uart(Platform::mmio_to_virt(Board::PL011_0_MMIO_BASE),
Board::PL011_0_CLOCK, baud_rate)
{ }
};

2
repos/base-hw/src/core/spec/riscv/board.h
View File

@ -14,6 +14,6 @@
#ifndef _CORE__SPEC__RISCV__BOARD_H_
#define _CORE__SPEC__RISCV__BOARD_H_
namespace Genode { struct Board { void init() { } }; }
namespace Board { }
#endif /* _CORE__SPEC__RISCV__BOARD_H_ */

9
repos/base-hw/src/core/spec/rpi/board.h
View File

@ -16,13 +16,10 @@
#define _CORE__SPEC__RPI__BOARD_H_
/* core includes */
#include <drivers/board_base.h>
#include <drivers/defs/rpi.h>
namespace Genode { struct Board; }
struct Genode::Board : Board_base
{
void init() { }
namespace Board {
using namespace Rpi;
static constexpr bool SMP = false;
};

4
repos/base-hw/src/core/spec/rpi/pic.cc
View File

@ -92,10 +92,10 @@ bool Genode::Pic::take_request(unsigned &irq)
if (!_is_pending(i, p1, p2))
continue;
irq = Board_base::GPU_IRQ_BASE + i;
irq = Board::GPU_IRQ_BASE + i;
/* handle SOF interrupts locally, filter from the user land */
if (irq == Board_base::DWC_IRQ)
if (irq == Board::DWC_IRQ)
if (_usb.handle_sof())
return false;

6
repos/base-hw/src/core/spec/tl16c750/serial.h
View File

@ -19,14 +19,14 @@
#include <platform.h>
/* Genode includes */
#include <drivers/uart_base.h>
#include <drivers/uart/tl16c750.h>
namespace Genode
{
/**
* Serial output driver for core
*/
class Serial : public Tl16c750_base
class Serial : public Tl16c750_uart
{
public:
@ -37,7 +37,7 @@ namespace Genode
*/
Serial(unsigned const baud_rate)
:
Tl16c750_base(Platform::mmio_to_virt(Board::TL16C750_3_MMIO_BASE),
Tl16c750_uart(Platform::mmio_to_virt(Board::TL16C750_3_MMIO_BASE),
Board::TL16C750_CLOCK, baud_rate)
{ }
};

25
repos/base-hw/src/core/spec/usb_armory/board.h Normal file
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@ -0,0 +1,25 @@
/*
* \brief Board driver
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__USB_ARMORY__BOARD_H_
#define _CORE__SPEC__USB_ARMORY__BOARD_H_
#include <drivers/defs/usb_armory.h>
namespace Board {
using namespace Usb_armory;
static constexpr bool SMP = false;
}
#endif /* _CORE__SPEC__USB_ARMORY__BOARD_H_ */

34
repos/base-hw/src/core/spec/wand_quad/board.h Normal file
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@ -0,0 +1,34 @@
/*
* \brief Board driver
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2014-02-25
*/
/*
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__WAND_QUAD__BOARD_H_
#define _CORE__SPEC__WAND_QUAD__BOARD_H_
/* base includes */
#include <drivers/defs/wand_quad.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Board {
using namespace Wand_quad;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
static constexpr bool SMP = true;
L2_cache & l2_cache();
}
#endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */

6
repos/base-hw/src/core/spec/x86_64/muen/serial.h
View File

@ -16,14 +16,14 @@
#define _CORE__SPEC__X86_64__MUEN__SERIAL_H_
/* Genode includes */
#include <drivers/uart_base.h>
#include <drivers/uart/x86_pc.h>
namespace Genode { class Serial; }
/**
* Serial output driver for core
*/
class Genode::Serial : public X86_uart_base
class Genode::Serial : public X86_uart
{
private:
@ -36,7 +36,7 @@ class Genode::Serial : public X86_uart_base
Serial(unsigned baud_rate)
:
X86_uart_base(COM1_PORT, CLOCK_UNUSED, baud_rate)
X86_uart(COM1_PORT, CLOCK_UNUSED, baud_rate)
{ }
};

21
repos/base-hw/src/core/spec/x86_64/muen/sinfo_instance.cc Normal file
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@ -0,0 +1,21 @@
/*
* \brief Sinfo kernel singleton
* \author Reto Buerki
* \date 2016-05-09
*/
/*
* Copyright (C) 2016-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <sinfo_instance.h>
#include <platform.h>
Genode::Sinfo * Genode::sinfo()
{
static Sinfo singleton(Platform::mmio_to_virt(Sinfo::PHYSICAL_BASE_ADDR));
return &singleton;
}

6
repos/base-hw/src/core/spec/x86_64/muen/sinfo_instance.h
View File

@ -16,17 +16,13 @@
/* base includes */
#include <muen/sinfo.h>
#include <platform.h>
namespace Genode
{
/**
* Return sinfo singleton
*/
static Sinfo * sinfo() {
static Sinfo singleton(Platform::mmio_to_virt(Sinfo::PHYSICAL_BASE_ADDR));
return &singleton;
}
Sinfo * sinfo();
}
#endif /* _CORE__SPEC__X86_64__MUEN__SINFO_INSTANCE_H_ */

42
repos/base-hw/src/core/spec/x86_64/muen/timer.cc Normal file
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@ -0,0 +1,42 @@
/*
* \brief Timer driver for core
* \author Reto Buerki
* \date 2015-04-14
*/
/*
* Copyright (C) 2015-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <timer.h>
#include <platform.h>
Genode::Timer::Timer() : _tics_per_ms(sinfo()->get_tsc_khz())
{
/* first sinfo instance, output status */
sinfo()->log_status();
struct Sinfo::Memregion_info region;
if (!sinfo()->get_memregion_info("timed_event", &region)) {
error("muen-timer: Unable to retrieve timed event region");
throw Invalid_region();
}
_event_page = (Subject_timed_event *)Platform::mmio_to_virt(region.address);
_event_page->event_nr = Board::TIMER_EVENT_KERNEL;
log("muen-timer: Page @", Hex(region.address), ", "
"frequency ", _tics_per_ms, " kHz, "
"event ", (unsigned)_event_page->event_nr);
if (sinfo()->get_memregion_info("monitor_timed_event", &region)) {
log("muen-timer: Found guest timed event page @", Hex(region.address),
" -> enabling preemption");
_guest_event_page = (Subject_timed_event *)Platform::mmio_to_virt(region.address);
_guest_event_page->event_nr = Board::TIMER_EVENT_PREEMPT;
}
}

27
repos/base-hw/src/core/spec/x86_64/muen/timer.h
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@ -61,32 +61,7 @@ class Genode::Timer
public:
Timer() :
_tics_per_ms(sinfo()->get_tsc_khz())
{
/* first sinfo instance, output status */
sinfo()->log_status();
struct Sinfo::Memregion_info region;
if (!sinfo()->get_memregion_info("timed_event", &region)) {
error("muen-timer: Unable to retrieve timed event region");
throw Invalid_region();
}
_event_page = (Subject_timed_event *)Platform::mmio_to_virt(region.address);
_event_page->event_nr = Board::TIMER_EVENT_KERNEL;
log("muen-timer: Page @", Hex(region.address), ", "
"frequency ", _tics_per_ms, " kHz, "
"event ", (unsigned)_event_page->event_nr);
if (sinfo()->get_memregion_info("monitor_timed_event", &region)) {
log("muen-timer: Found guest timed event page @", Hex(region.address),
" -> enabling preemption");
_guest_event_page = (Subject_timed_event *)Platform::mmio_to_virt(region.address);
_guest_event_page->event_nr = Board::TIMER_EVENT_PREEMPT;
}
}
Timer();
static unsigned interrupt_id(int) {
return Board::TIMER_VECTOR_KERNEL; }

8
repos/base-hw/src/core/spec/x86_64/serial.h
View File

@ -16,14 +16,14 @@
/* Genode includes */
#include <bios_data_area.h>
#include <drivers/uart_base.h>
#include <drivers/uart/x86_pc.h>
namespace Genode { class Serial; }
/**
* Serial output driver for core
*/
class Genode::Serial : public X86_uart_base
class Genode::Serial : public X86_uart
{
private:
@ -33,8 +33,8 @@ class Genode::Serial : public X86_uart_base
Serial(unsigned baud_rate)
:
X86_uart_base(Bios_data_area::singleton()->serial_port(),
CLOCK_UNUSED, baud_rate)
X86_uart(Bios_data_area::singleton()->serial_port(),
CLOCK_UNUSED, baud_rate)
{ }
};

8
repos/base-hw/src/core/spec/xilinx_uartps_0/serial.h
View File

@ -19,14 +19,14 @@
#include <platform.h>
/* Genode includes */
#include <drivers/uart_base.h>
#include <drivers/uart/xilinx.h>
namespace Genode { class Serial; }
/**
* Serial output driver for core
*/
class Genode::Serial : public Xilinx_uartps_base
class Genode::Serial : public Xilinx_uart
{
public:
@ -37,8 +37,8 @@ class Genode::Serial : public Xilinx_uartps_base
*/
Serial(unsigned const baud_rate)
:
Xilinx_uartps_base(Platform::mmio_to_virt(Board::UART_0_MMIO_BASE),
Board::UART_CLOCK, baud_rate)
Xilinx_uart(Platform::mmio_to_virt(Board::UART_0_MMIO_BASE),
Board::UART_CLOCK, baud_rate)
{ }
};

24
repos/base-hw/src/core/spec/zynq_qemu/board.h
View File

@ -16,18 +16,20 @@
#ifndef _CORE__SPEC__ZYNQ_QEMU__BOARD_H_
#define _CORE__SPEC__ZYNQ_QEMU__BOARD_H_
/* core includes */
#include <spec/cortex_a9/board_support.h>
/* base includes */
#include <drivers/defs/zynq_qemu.h>
namespace Genode
{
struct Board : Cortex_a9::Board
{
enum {
KERNEL_UART_BASE = UART_0_MMIO_BASE,
KERNEL_UART_SIZE = UART_SIZE,
};
};
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Board {
using namespace Zynq_qemu;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using L2_cache = Hw::Pl310;
static constexpr bool SMP = true;
L2_cache & l2_cache();
}
#endif /* _CORE__SPEC__ZYNQ_QEMU__BOARD_H_ */

4
repos/base-hw/src/lib/hw/spec/arm/cortex_a15.h
View File

@ -16,10 +16,10 @@
#include <base/stdint.h>
namespace Hw { template <Genode::addr_t> struct Cpu_memory_map; }
namespace Hw { template <Genode::addr_t> struct Cortex_a15_mmio; }
template <typename Genode::addr_t BASE>
struct Hw::Cpu_memory_map
struct Hw::Cortex_a15_mmio
{
enum {
IRQ_CONTROLLER_DISTR_BASE = BASE + 0x1000,

4
repos/base-hw/src/lib/hw/spec/arm/cortex_a9.h
View File

@ -16,10 +16,10 @@
#include <base/stdint.h>
namespace Hw { template <Genode::addr_t> struct Cpu_memory_map; }
namespace Hw { template <Genode::addr_t> struct Cortex_a9_mmio; }
template <typename Genode::addr_t BASE>
struct Hw::Cpu_memory_map
struct Hw::Cortex_a9_mmio
{
enum {
SCU_MMIO_BASE = BASE,

6
repos/base-nova/src/core/core_log.cc
View File

@ -16,14 +16,14 @@
/* Genode includes */
#include <bios_data_area.h>
#include <drivers/uart_base.h>
#include <drivers/uart/x86_pc.h>
void Genode::Core_log::out(char const c)
{
enum { CLOCK = 0, BAUDRATE = 115200 };
static X86_uart_base uart(Bios_data_area::singleton()->serial_port(),
CLOCK, BAUDRATE);
static X86_uart uart(Bios_data_area::singleton()->serial_port(),
CLOCK, BAUDRATE);
if (c == '\n')
uart.put_char('\r');
uart.put_char(c);

21
repos/base/include/spec/arndale/drivers/board_base.h → repos/base/include/drivers/defs/arndale.h
View File

@ -1,5 +1,5 @@
/*
* \brief Driver base for the InSignal Arndale 5 board
* \brief MMIO and IRQ definitions for the InSignal Arndale 5 board
* \author Martin stein
* \date 2013-01-09
*/
@ -11,20 +11,16 @@
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__SPEC__ARNDALE__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__SPEC__ARNDALE__DRIVERS__BOARD_BASE_H_
#ifndef _INCLUDE__DRIVERS__DEFS__ARNDALE_H_
#define _INCLUDE__DRIVERS__DEFS__ARNDALE_H_
/* Genode includes */
#include <spec/exynos5/board_base.h>
#include <drivers/defs/exynos5.h>
namespace Genode { struct Board_base; }
namespace Arndale {
using namespace Exynos5;
/**
* Board driver base
*/
struct Genode::Board_base : Exynos5
{
enum
{
/* clock management unit */
@ -41,10 +37,7 @@ struct Genode::Board_base : Exynos5
/* UART */
UART_2_CLOCK = 100000000,
/* wether board provides security extension */
SECURITY_EXTENSION = 1,
};
};
#endif /* _INCLUDE__SPEC__ARNDALE__DRIVERS__BOARD_BASE_H_ */
#endif /* _INCLUDE__DRIVERS__DEFS__ARNDALE_H_ */

17
repos/base/include/spec/exynos5/board_base.h → repos/base/include/drivers/defs/exynos5.h
View File

@ -1,5 +1,5 @@
/*
* \brief Board-driver base
* \brief MMIO and IRQ definitions common to Exynos5 SoC
* \author Stefan Kalkowski
* \date 2013-11-25
*/
@ -11,17 +11,10 @@
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__SPEC__EXYNOS5__BOARD_BASE_H_
#define _INCLUDE__SPEC__EXYNOS5__BOARD_BASE_H_
#ifndef _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
#define _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
namespace Genode { struct Exynos5; }
/**
* Board-driver base
*/
struct Genode::Exynos5
{
namespace Exynos5 {
enum {
/* normal RAM */
RAM_0_BASE = 0x40000000,
@ -95,4 +88,4 @@ struct Genode::Exynos5
};
};
#endif /* _INCLUDE__SPEC__EXYNOS5__BOARD_BASE_H_ */
#endif /* _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_ */

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